1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "qemu/host-utils.h" 27 #include "qemu/thread.h" 28 #ifndef CONFIG_USER_ONLY 29 #include "exec/hwaddr.h" 30 #endif 31 #include "exec/memattrs.h" 32 #include "hw/core/cpu.h" 33 34 #include "cpu-param.h" 35 36 #ifndef TARGET_LONG_BITS 37 # error TARGET_LONG_BITS must be defined in cpu-param.h 38 #endif 39 #ifndef NB_MMU_MODES 40 # error NB_MMU_MODES must be defined in cpu-param.h 41 #endif 42 #ifndef TARGET_PHYS_ADDR_SPACE_BITS 43 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h 44 #endif 45 #ifndef TARGET_VIRT_ADDR_SPACE_BITS 46 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h 47 #endif 48 #ifndef TARGET_PAGE_BITS 49 # ifdef TARGET_PAGE_BITS_VARY 50 # ifndef TARGET_PAGE_BITS_MIN 51 # error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h 52 # endif 53 # else 54 # error TARGET_PAGE_BITS must be defined in cpu-param.h 55 # endif 56 #endif 57 #ifndef TARGET_TB_PCREL 58 # define TARGET_TB_PCREL 0 59 #endif 60 61 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 62 63 /* target_ulong is the type of a virtual address */ 64 #if TARGET_LONG_SIZE == 4 65 typedef int32_t target_long; 66 typedef uint32_t target_ulong; 67 #define TARGET_FMT_lx "%08x" 68 #define TARGET_FMT_ld "%d" 69 #define TARGET_FMT_lu "%u" 70 #elif TARGET_LONG_SIZE == 8 71 typedef int64_t target_long; 72 typedef uint64_t target_ulong; 73 #define TARGET_FMT_lx "%016" PRIx64 74 #define TARGET_FMT_ld "%" PRId64 75 #define TARGET_FMT_lu "%" PRIu64 76 #else 77 #error TARGET_LONG_SIZE undefined 78 #endif 79 80 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 81 82 /* use a fully associative victim tlb of 8 entries */ 83 #define CPU_VTLB_SIZE 8 84 85 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 86 #define CPU_TLB_ENTRY_BITS 4 87 #else 88 #define CPU_TLB_ENTRY_BITS 5 89 #endif 90 91 #define CPU_TLB_DYN_MIN_BITS 6 92 #define CPU_TLB_DYN_DEFAULT_BITS 8 93 94 # if HOST_LONG_BITS == 32 95 /* Make sure we do not require a double-word shift for the TLB load */ 96 # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 97 # else /* HOST_LONG_BITS == 64 */ 98 /* 99 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 100 * 2**34 == 16G of address space. This is roughly what one would expect a 101 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 102 * Skylake's Level-2 STLB has 16 1G entries. 103 * Also, make sure we do not size the TLB past the guest's address space. 104 */ 105 # ifdef TARGET_PAGE_BITS_VARY 106 # define CPU_TLB_DYN_MAX_BITS \ 107 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 108 # else 109 # define CPU_TLB_DYN_MAX_BITS \ 110 MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 111 # endif 112 # endif 113 114 /* Minimalized TLB entry for use by TCG fast path. */ 115 typedef struct CPUTLBEntry { 116 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 117 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 118 go directly to ram. 119 bit 3 : indicates that the entry is invalid 120 bit 2..0 : zero 121 */ 122 union { 123 struct { 124 target_ulong addr_read; 125 target_ulong addr_write; 126 target_ulong addr_code; 127 /* Addend to virtual address to get host address. IO accesses 128 use the corresponding iotlb value. */ 129 uintptr_t addend; 130 }; 131 /* padding to get a power of two size */ 132 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; 133 }; 134 } CPUTLBEntry; 135 136 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 137 138 139 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 140 141 #if !defined(CONFIG_USER_ONLY) 142 /* 143 * The full TLB entry, which is not accessed by generated TCG code, 144 * so the layout is not as critical as that of CPUTLBEntry. This is 145 * also why we don't want to combine the two structs. 146 */ 147 typedef struct CPUTLBEntryFull { 148 /* 149 * @xlat_section contains: 150 * - in the lower TARGET_PAGE_BITS, a physical section number 151 * - with the lower TARGET_PAGE_BITS masked off, an offset which 152 * must be added to the virtual address to obtain: 153 * + the ram_addr_t of the target RAM (if the physical section 154 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) 155 * + the offset within the target MemoryRegion (otherwise) 156 */ 157 hwaddr xlat_section; 158 159 /* 160 * @phys_addr contains the physical address in the address space 161 * given by cpu_asidx_from_attrs(cpu, @attrs). 162 */ 163 hwaddr phys_addr; 164 165 /* @attrs contains the memory transaction attributes for the page. */ 166 MemTxAttrs attrs; 167 168 /* @prot contains the complete protections for the page. */ 169 uint8_t prot; 170 171 /* @lg_page_size contains the log2 of the page size. */ 172 uint8_t lg_page_size; 173 174 /* 175 * Allow target-specific additions to this structure. 176 * This may be used to cache items from the guest cpu 177 * page tables for later use by the implementation. 178 */ 179 #ifdef TARGET_PAGE_ENTRY_EXTRA 180 TARGET_PAGE_ENTRY_EXTRA 181 #endif 182 } CPUTLBEntryFull; 183 #endif /* !CONFIG_USER_ONLY */ 184 185 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 186 /* 187 * Data elements that are per MMU mode, minus the bits accessed by 188 * the TCG fast path. 189 */ 190 typedef struct CPUTLBDesc { 191 /* 192 * Describe a region covering all of the large pages allocated 193 * into the tlb. When any page within this region is flushed, 194 * we must flush the entire tlb. The region is matched if 195 * (addr & large_page_mask) == large_page_addr. 196 */ 197 target_ulong large_page_addr; 198 target_ulong large_page_mask; 199 /* host time (in ns) at the beginning of the time window */ 200 int64_t window_begin_ns; 201 /* maximum number of entries observed in the window */ 202 size_t window_max_entries; 203 size_t n_used_entries; 204 /* The next index to use in the tlb victim table. */ 205 size_t vindex; 206 /* The tlb victim table, in two parts. */ 207 CPUTLBEntry vtable[CPU_VTLB_SIZE]; 208 CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; 209 CPUTLBEntryFull *fulltlb; 210 } CPUTLBDesc; 211 212 /* 213 * Data elements that are per MMU mode, accessed by the fast path. 214 * The structure is aligned to aid loading the pair with one insn. 215 */ 216 typedef struct CPUTLBDescFast { 217 /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ 218 uintptr_t mask; 219 /* The array of tlb entries itself. */ 220 CPUTLBEntry *table; 221 } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); 222 223 /* 224 * Data elements that are shared between all MMU modes. 225 */ 226 typedef struct CPUTLBCommon { 227 /* Serialize updates to f.table and d.vtable, and others as noted. */ 228 QemuSpin lock; 229 /* 230 * Within dirty, for each bit N, modifications have been made to 231 * mmu_idx N since the last time that mmu_idx was flushed. 232 * Protected by tlb_c.lock. 233 */ 234 uint16_t dirty; 235 /* 236 * Statistics. These are not lock protected, but are read and 237 * written atomically. This allows the monitor to print a snapshot 238 * of the stats without interfering with the cpu. 239 */ 240 size_t full_flush_count; 241 size_t part_flush_count; 242 size_t elide_flush_count; 243 } CPUTLBCommon; 244 245 /* 246 * The entire softmmu tlb, for all MMU modes. 247 * The meaning of each of the MMU modes is defined in the target code. 248 * Since this is placed within CPUNegativeOffsetState, the smallest 249 * negative offsets are at the end of the struct. 250 */ 251 252 typedef struct CPUTLB { 253 CPUTLBCommon c; 254 CPUTLBDesc d[NB_MMU_MODES]; 255 CPUTLBDescFast f[NB_MMU_MODES]; 256 } CPUTLB; 257 258 /* This will be used by TCG backends to compute offsets. */ 259 #define TLB_MASK_TABLE_OFS(IDX) \ 260 ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) 261 262 #else 263 264 typedef struct CPUTLB { } CPUTLB; 265 266 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 267 268 /* 269 * This structure must be placed in ArchCPU immediately 270 * before CPUArchState, as a field named "neg". 271 */ 272 typedef struct CPUNegativeOffsetState { 273 CPUTLB tlb; 274 IcountDecr icount_decr; 275 } CPUNegativeOffsetState; 276 277 #endif 278