1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "qemu/host-utils.h" 27 #include "qemu/thread.h" 28 #ifndef CONFIG_USER_ONLY 29 #include "exec/hwaddr.h" 30 #endif 31 #include "exec/memattrs.h" 32 #include "hw/core/cpu.h" 33 34 #include "cpu-param.h" 35 36 #ifndef TARGET_LONG_BITS 37 # error TARGET_LONG_BITS must be defined in cpu-param.h 38 #endif 39 #ifndef TARGET_PHYS_ADDR_SPACE_BITS 40 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h 41 #endif 42 #ifndef TARGET_VIRT_ADDR_SPACE_BITS 43 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h 44 #endif 45 #ifndef TARGET_PAGE_BITS 46 # ifdef TARGET_PAGE_BITS_VARY 47 # ifndef TARGET_PAGE_BITS_MIN 48 # error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h 49 # endif 50 # else 51 # error TARGET_PAGE_BITS must be defined in cpu-param.h 52 # endif 53 #endif 54 55 #include "exec/target_long.h" 56 57 /* 58 * Fix the number of mmu modes to 16, which is also the maximum 59 * supported by the softmmu tlb api. 60 */ 61 #define NB_MMU_MODES 16 62 63 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 64 65 /* use a fully associative victim tlb of 8 entries */ 66 #define CPU_VTLB_SIZE 8 67 68 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 69 #define CPU_TLB_ENTRY_BITS 4 70 #else 71 #define CPU_TLB_ENTRY_BITS 5 72 #endif 73 74 #define CPU_TLB_DYN_MIN_BITS 6 75 #define CPU_TLB_DYN_DEFAULT_BITS 8 76 77 # if HOST_LONG_BITS == 32 78 /* Make sure we do not require a double-word shift for the TLB load */ 79 # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 80 # else /* HOST_LONG_BITS == 64 */ 81 /* 82 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 83 * 2**34 == 16G of address space. This is roughly what one would expect a 84 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 85 * Skylake's Level-2 STLB has 16 1G entries. 86 * Also, make sure we do not size the TLB past the guest's address space. 87 */ 88 # ifdef TARGET_PAGE_BITS_VARY 89 # define CPU_TLB_DYN_MAX_BITS \ 90 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 91 # else 92 # define CPU_TLB_DYN_MAX_BITS \ 93 MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 94 # endif 95 # endif 96 97 /* Minimalized TLB entry for use by TCG fast path. */ 98 typedef struct CPUTLBEntry { 99 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 100 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 101 go directly to ram. 102 bit 3 : indicates that the entry is invalid 103 bit 2..0 : zero 104 */ 105 union { 106 struct { 107 target_ulong addr_read; 108 target_ulong addr_write; 109 target_ulong addr_code; 110 /* Addend to virtual address to get host address. IO accesses 111 use the corresponding iotlb value. */ 112 uintptr_t addend; 113 }; 114 /* 115 * Padding to get a power of two size, as well as index 116 * access to addr_{read,write,code}. 117 */ 118 target_ulong addr_idx[(1 << CPU_TLB_ENTRY_BITS) / TARGET_LONG_SIZE]; 119 }; 120 } CPUTLBEntry; 121 122 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 123 124 125 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 126 127 #if !defined(CONFIG_USER_ONLY) 128 /* 129 * The full TLB entry, which is not accessed by generated TCG code, 130 * so the layout is not as critical as that of CPUTLBEntry. This is 131 * also why we don't want to combine the two structs. 132 */ 133 typedef struct CPUTLBEntryFull { 134 /* 135 * @xlat_section contains: 136 * - in the lower TARGET_PAGE_BITS, a physical section number 137 * - with the lower TARGET_PAGE_BITS masked off, an offset which 138 * must be added to the virtual address to obtain: 139 * + the ram_addr_t of the target RAM (if the physical section 140 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) 141 * + the offset within the target MemoryRegion (otherwise) 142 */ 143 hwaddr xlat_section; 144 145 /* 146 * @phys_addr contains the physical address in the address space 147 * given by cpu_asidx_from_attrs(cpu, @attrs). 148 */ 149 hwaddr phys_addr; 150 151 /* @attrs contains the memory transaction attributes for the page. */ 152 MemTxAttrs attrs; 153 154 /* @prot contains the complete protections for the page. */ 155 uint8_t prot; 156 157 /* @lg_page_size contains the log2 of the page size. */ 158 uint8_t lg_page_size; 159 160 /* 161 * Allow target-specific additions to this structure. 162 * This may be used to cache items from the guest cpu 163 * page tables for later use by the implementation. 164 */ 165 #ifdef TARGET_PAGE_ENTRY_EXTRA 166 TARGET_PAGE_ENTRY_EXTRA 167 #endif 168 } CPUTLBEntryFull; 169 #endif /* !CONFIG_USER_ONLY */ 170 171 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 172 /* 173 * Data elements that are per MMU mode, minus the bits accessed by 174 * the TCG fast path. 175 */ 176 typedef struct CPUTLBDesc { 177 /* 178 * Describe a region covering all of the large pages allocated 179 * into the tlb. When any page within this region is flushed, 180 * we must flush the entire tlb. The region is matched if 181 * (addr & large_page_mask) == large_page_addr. 182 */ 183 target_ulong large_page_addr; 184 target_ulong large_page_mask; 185 /* host time (in ns) at the beginning of the time window */ 186 int64_t window_begin_ns; 187 /* maximum number of entries observed in the window */ 188 size_t window_max_entries; 189 size_t n_used_entries; 190 /* The next index to use in the tlb victim table. */ 191 size_t vindex; 192 /* The tlb victim table, in two parts. */ 193 CPUTLBEntry vtable[CPU_VTLB_SIZE]; 194 CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; 195 CPUTLBEntryFull *fulltlb; 196 } CPUTLBDesc; 197 198 /* 199 * Data elements that are per MMU mode, accessed by the fast path. 200 * The structure is aligned to aid loading the pair with one insn. 201 */ 202 typedef struct CPUTLBDescFast { 203 /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ 204 uintptr_t mask; 205 /* The array of tlb entries itself. */ 206 CPUTLBEntry *table; 207 } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); 208 209 /* 210 * Data elements that are shared between all MMU modes. 211 */ 212 typedef struct CPUTLBCommon { 213 /* Serialize updates to f.table and d.vtable, and others as noted. */ 214 QemuSpin lock; 215 /* 216 * Within dirty, for each bit N, modifications have been made to 217 * mmu_idx N since the last time that mmu_idx was flushed. 218 * Protected by tlb_c.lock. 219 */ 220 uint16_t dirty; 221 /* 222 * Statistics. These are not lock protected, but are read and 223 * written atomically. This allows the monitor to print a snapshot 224 * of the stats without interfering with the cpu. 225 */ 226 size_t full_flush_count; 227 size_t part_flush_count; 228 size_t elide_flush_count; 229 } CPUTLBCommon; 230 231 /* 232 * The entire softmmu tlb, for all MMU modes. 233 * The meaning of each of the MMU modes is defined in the target code. 234 * Since this is placed within CPUNegativeOffsetState, the smallest 235 * negative offsets are at the end of the struct. 236 */ 237 238 typedef struct CPUTLB { 239 CPUTLBCommon c; 240 CPUTLBDesc d[NB_MMU_MODES]; 241 CPUTLBDescFast f[NB_MMU_MODES]; 242 } CPUTLB; 243 244 /* This will be used by TCG backends to compute offsets. */ 245 #define TLB_MASK_TABLE_OFS(IDX) \ 246 ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) 247 248 #else 249 250 typedef struct CPUTLB { } CPUTLB; 251 252 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 253 254 /* 255 * This structure must be placed in ArchCPU immediately 256 * before CPUArchState, as a field named "neg". 257 */ 258 typedef struct CPUNegativeOffsetState { 259 CPUTLB tlb; 260 IcountDecr icount_decr; 261 } CPUNegativeOffsetState; 262 263 #endif 264