1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "qemu/host-utils.h" 27 #include "qemu/thread.h" 28 #ifndef CONFIG_USER_ONLY 29 #include "exec/hwaddr.h" 30 #endif 31 #include "exec/memattrs.h" 32 #include "hw/core/cpu.h" 33 34 #include "cpu-param.h" 35 36 #ifndef TARGET_LONG_BITS 37 # error TARGET_LONG_BITS must be defined in cpu-param.h 38 #endif 39 #ifndef TARGET_PHYS_ADDR_SPACE_BITS 40 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h 41 #endif 42 #ifndef TARGET_VIRT_ADDR_SPACE_BITS 43 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h 44 #endif 45 #ifndef TARGET_PAGE_BITS 46 # ifdef TARGET_PAGE_BITS_VARY 47 # ifndef TARGET_PAGE_BITS_MIN 48 # error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h 49 # endif 50 # else 51 # error TARGET_PAGE_BITS must be defined in cpu-param.h 52 # endif 53 #endif 54 55 #include "exec/target_long.h" 56 57 /* 58 * Fix the number of mmu modes to 16, which is also the maximum 59 * supported by the softmmu tlb api. 60 */ 61 #define NB_MMU_MODES 16 62 63 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 64 65 /* use a fully associative victim tlb of 8 entries */ 66 #define CPU_VTLB_SIZE 8 67 68 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 69 #define CPU_TLB_ENTRY_BITS 4 70 #else 71 #define CPU_TLB_ENTRY_BITS 5 72 #endif 73 74 #define CPU_TLB_DYN_MIN_BITS 6 75 #define CPU_TLB_DYN_DEFAULT_BITS 8 76 77 # if HOST_LONG_BITS == 32 78 /* Make sure we do not require a double-word shift for the TLB load */ 79 # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 80 # else /* HOST_LONG_BITS == 64 */ 81 /* 82 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 83 * 2**34 == 16G of address space. This is roughly what one would expect a 84 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 85 * Skylake's Level-2 STLB has 16 1G entries. 86 * Also, make sure we do not size the TLB past the guest's address space. 87 */ 88 # ifdef TARGET_PAGE_BITS_VARY 89 # define CPU_TLB_DYN_MAX_BITS \ 90 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 91 # else 92 # define CPU_TLB_DYN_MAX_BITS \ 93 MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 94 # endif 95 # endif 96 97 /* Minimalized TLB entry for use by TCG fast path. */ 98 typedef struct CPUTLBEntry { 99 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 100 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 101 go directly to ram. 102 bit 3 : indicates that the entry is invalid 103 bit 2..0 : zero 104 */ 105 union { 106 struct { 107 target_ulong addr_read; 108 target_ulong addr_write; 109 target_ulong addr_code; 110 /* Addend to virtual address to get host address. IO accesses 111 use the corresponding iotlb value. */ 112 uintptr_t addend; 113 }; 114 /* padding to get a power of two size */ 115 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; 116 }; 117 } CPUTLBEntry; 118 119 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 120 121 122 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 123 124 #if !defined(CONFIG_USER_ONLY) 125 /* 126 * The full TLB entry, which is not accessed by generated TCG code, 127 * so the layout is not as critical as that of CPUTLBEntry. This is 128 * also why we don't want to combine the two structs. 129 */ 130 typedef struct CPUTLBEntryFull { 131 /* 132 * @xlat_section contains: 133 * - in the lower TARGET_PAGE_BITS, a physical section number 134 * - with the lower TARGET_PAGE_BITS masked off, an offset which 135 * must be added to the virtual address to obtain: 136 * + the ram_addr_t of the target RAM (if the physical section 137 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) 138 * + the offset within the target MemoryRegion (otherwise) 139 */ 140 hwaddr xlat_section; 141 142 /* 143 * @phys_addr contains the physical address in the address space 144 * given by cpu_asidx_from_attrs(cpu, @attrs). 145 */ 146 hwaddr phys_addr; 147 148 /* @attrs contains the memory transaction attributes for the page. */ 149 MemTxAttrs attrs; 150 151 /* @prot contains the complete protections for the page. */ 152 uint8_t prot; 153 154 /* @lg_page_size contains the log2 of the page size. */ 155 uint8_t lg_page_size; 156 157 /* 158 * Allow target-specific additions to this structure. 159 * This may be used to cache items from the guest cpu 160 * page tables for later use by the implementation. 161 */ 162 #ifdef TARGET_PAGE_ENTRY_EXTRA 163 TARGET_PAGE_ENTRY_EXTRA 164 #endif 165 } CPUTLBEntryFull; 166 #endif /* !CONFIG_USER_ONLY */ 167 168 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 169 /* 170 * Data elements that are per MMU mode, minus the bits accessed by 171 * the TCG fast path. 172 */ 173 typedef struct CPUTLBDesc { 174 /* 175 * Describe a region covering all of the large pages allocated 176 * into the tlb. When any page within this region is flushed, 177 * we must flush the entire tlb. The region is matched if 178 * (addr & large_page_mask) == large_page_addr. 179 */ 180 target_ulong large_page_addr; 181 target_ulong large_page_mask; 182 /* host time (in ns) at the beginning of the time window */ 183 int64_t window_begin_ns; 184 /* maximum number of entries observed in the window */ 185 size_t window_max_entries; 186 size_t n_used_entries; 187 /* The next index to use in the tlb victim table. */ 188 size_t vindex; 189 /* The tlb victim table, in two parts. */ 190 CPUTLBEntry vtable[CPU_VTLB_SIZE]; 191 CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; 192 CPUTLBEntryFull *fulltlb; 193 } CPUTLBDesc; 194 195 /* 196 * Data elements that are per MMU mode, accessed by the fast path. 197 * The structure is aligned to aid loading the pair with one insn. 198 */ 199 typedef struct CPUTLBDescFast { 200 /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ 201 uintptr_t mask; 202 /* The array of tlb entries itself. */ 203 CPUTLBEntry *table; 204 } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); 205 206 /* 207 * Data elements that are shared between all MMU modes. 208 */ 209 typedef struct CPUTLBCommon { 210 /* Serialize updates to f.table and d.vtable, and others as noted. */ 211 QemuSpin lock; 212 /* 213 * Within dirty, for each bit N, modifications have been made to 214 * mmu_idx N since the last time that mmu_idx was flushed. 215 * Protected by tlb_c.lock. 216 */ 217 uint16_t dirty; 218 /* 219 * Statistics. These are not lock protected, but are read and 220 * written atomically. This allows the monitor to print a snapshot 221 * of the stats without interfering with the cpu. 222 */ 223 size_t full_flush_count; 224 size_t part_flush_count; 225 size_t elide_flush_count; 226 } CPUTLBCommon; 227 228 /* 229 * The entire softmmu tlb, for all MMU modes. 230 * The meaning of each of the MMU modes is defined in the target code. 231 * Since this is placed within CPUNegativeOffsetState, the smallest 232 * negative offsets are at the end of the struct. 233 */ 234 235 typedef struct CPUTLB { 236 CPUTLBCommon c; 237 CPUTLBDesc d[NB_MMU_MODES]; 238 CPUTLBDescFast f[NB_MMU_MODES]; 239 } CPUTLB; 240 241 /* This will be used by TCG backends to compute offsets. */ 242 #define TLB_MASK_TABLE_OFS(IDX) \ 243 ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) 244 245 #else 246 247 typedef struct CPUTLB { } CPUTLB; 248 249 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 250 251 /* 252 * This structure must be placed in ArchCPU immediately 253 * before CPUArchState, as a field named "neg". 254 */ 255 typedef struct CPUNegativeOffsetState { 256 CPUTLB tlb; 257 IcountDecr icount_decr; 258 } CPUNegativeOffsetState; 259 260 #endif 261