1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 3 4 /* CPU interfaces that are target independent. */ 5 6 #ifndef CONFIG_USER_ONLY 7 #include "exec/hwaddr.h" 8 #endif 9 10 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 11 * when intptr_t is 32-bit and we are aligning a long long. 12 */ 13 extern uintptr_t qemu_host_page_size; 14 extern intptr_t qemu_host_page_mask; 15 16 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) 17 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size) 18 19 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 20 void qemu_init_cpu_list(void); 21 void cpu_list_lock(void); 22 void cpu_list_unlock(void); 23 24 void tcg_flush_softmmu_tlb(CPUState *cs); 25 26 void tcg_iommu_init_notifier_list(CPUState *cpu); 27 void tcg_iommu_free_notifier_list(CPUState *cpu); 28 29 #if !defined(CONFIG_USER_ONLY) 30 31 enum device_endian { 32 DEVICE_NATIVE_ENDIAN, 33 DEVICE_BIG_ENDIAN, 34 DEVICE_LITTLE_ENDIAN, 35 }; 36 37 #if defined(HOST_WORDS_BIGENDIAN) 38 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 39 #else 40 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 41 #endif 42 43 /* address in the RAM (different from a physical address) */ 44 #if defined(CONFIG_XEN_BACKEND) 45 typedef uint64_t ram_addr_t; 46 # define RAM_ADDR_MAX UINT64_MAX 47 # define RAM_ADDR_FMT "%" PRIx64 48 #else 49 typedef uintptr_t ram_addr_t; 50 # define RAM_ADDR_MAX UINTPTR_MAX 51 # define RAM_ADDR_FMT "%" PRIxPTR 52 #endif 53 54 /* memory API */ 55 56 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 57 /* This should not be used by devices. */ 58 ram_addr_t qemu_ram_addr_from_host(void *ptr); 59 RAMBlock *qemu_ram_block_by_name(const char *name); 60 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 61 ram_addr_t *offset); 62 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 63 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 64 void qemu_ram_unset_idstr(RAMBlock *block); 65 const char *qemu_ram_get_idstr(RAMBlock *rb); 66 void *qemu_ram_get_host_addr(RAMBlock *rb); 67 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 68 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 69 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 70 bool qemu_ram_is_shared(RAMBlock *rb); 71 bool qemu_ram_is_noreserve(RAMBlock *rb); 72 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 73 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 74 bool qemu_ram_is_migratable(RAMBlock *rb); 75 void qemu_ram_set_migratable(RAMBlock *rb); 76 void qemu_ram_unset_migratable(RAMBlock *rb); 77 78 size_t qemu_ram_pagesize(RAMBlock *block); 79 size_t qemu_ram_pagesize_largest(void); 80 81 void cpu_physical_memory_rw(hwaddr addr, void *buf, 82 hwaddr len, bool is_write); 83 static inline void cpu_physical_memory_read(hwaddr addr, 84 void *buf, hwaddr len) 85 { 86 cpu_physical_memory_rw(addr, buf, len, false); 87 } 88 static inline void cpu_physical_memory_write(hwaddr addr, 89 const void *buf, hwaddr len) 90 { 91 cpu_physical_memory_rw(addr, (void *)buf, len, true); 92 } 93 void *cpu_physical_memory_map(hwaddr addr, 94 hwaddr *plen, 95 bool is_write); 96 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 97 bool is_write, hwaddr access_len); 98 void cpu_register_map_client(QEMUBH *bh); 99 void cpu_unregister_map_client(QEMUBH *bh); 100 101 bool cpu_physical_memory_is_io(hwaddr phys_addr); 102 103 /* Coalesced MMIO regions are areas where write operations can be reordered. 104 * This usually implies that write operations are side-effect free. This allows 105 * batching which can make a major impact on performance when using 106 * virtualization. 107 */ 108 void qemu_flush_coalesced_mmio_buffer(void); 109 110 void cpu_flush_icache_range(hwaddr start, hwaddr len); 111 112 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 113 114 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 115 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 116 117 #endif 118 119 /* vl.c */ 120 extern int singlestep; 121 122 #endif /* CPU_COMMON_H */ 123