1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 3 4 /* CPU interfaces that are target independent. */ 5 6 #ifndef CONFIG_USER_ONLY 7 #include "exec/hwaddr.h" 8 #endif 9 10 /** 11 * vaddr: 12 * Type wide enough to contain any #target_ulong virtual address. 13 */ 14 typedef uint64_t vaddr; 15 #define VADDR_PRId PRId64 16 #define VADDR_PRIu PRIu64 17 #define VADDR_PRIo PRIo64 18 #define VADDR_PRIx PRIx64 19 #define VADDR_PRIX PRIX64 20 #define VADDR_MAX UINT64_MAX 21 22 void cpu_exec_init_all(void); 23 void cpu_exec_step_atomic(CPUState *cpu); 24 25 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 26 * when intptr_t is 32-bit and we are aligning a long long. 27 */ 28 extern uintptr_t qemu_host_page_size; 29 extern intptr_t qemu_host_page_mask; 30 31 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) 32 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size()) 33 34 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 35 void qemu_init_cpu_list(void); 36 void cpu_list_lock(void); 37 void cpu_list_unlock(void); 38 unsigned int cpu_list_generation_id_get(void); 39 40 void tcg_flush_softmmu_tlb(CPUState *cs); 41 42 void tcg_iommu_init_notifier_list(CPUState *cpu); 43 void tcg_iommu_free_notifier_list(CPUState *cpu); 44 45 #if !defined(CONFIG_USER_ONLY) 46 47 enum device_endian { 48 DEVICE_NATIVE_ENDIAN, 49 DEVICE_BIG_ENDIAN, 50 DEVICE_LITTLE_ENDIAN, 51 }; 52 53 #if HOST_BIG_ENDIAN 54 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 55 #else 56 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 57 #endif 58 59 /* address in the RAM (different from a physical address) */ 60 #if defined(CONFIG_XEN_BACKEND) 61 typedef uint64_t ram_addr_t; 62 # define RAM_ADDR_MAX UINT64_MAX 63 # define RAM_ADDR_FMT "%" PRIx64 64 #else 65 typedef uintptr_t ram_addr_t; 66 # define RAM_ADDR_MAX UINTPTR_MAX 67 # define RAM_ADDR_FMT "%" PRIxPTR 68 #endif 69 70 /* memory API */ 71 72 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 73 /* This should not be used by devices. */ 74 ram_addr_t qemu_ram_addr_from_host(void *ptr); 75 RAMBlock *qemu_ram_block_by_name(const char *name); 76 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 77 ram_addr_t *offset); 78 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 79 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 80 void qemu_ram_unset_idstr(RAMBlock *block); 81 const char *qemu_ram_get_idstr(RAMBlock *rb); 82 void *qemu_ram_get_host_addr(RAMBlock *rb); 83 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 84 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 85 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 86 bool qemu_ram_is_shared(RAMBlock *rb); 87 bool qemu_ram_is_noreserve(RAMBlock *rb); 88 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 89 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 90 bool qemu_ram_is_migratable(RAMBlock *rb); 91 void qemu_ram_set_migratable(RAMBlock *rb); 92 void qemu_ram_unset_migratable(RAMBlock *rb); 93 94 size_t qemu_ram_pagesize(RAMBlock *block); 95 size_t qemu_ram_pagesize_largest(void); 96 97 /** 98 * cpu_address_space_init: 99 * @cpu: CPU to add this address space to 100 * @asidx: integer index of this address space 101 * @prefix: prefix to be used as name of address space 102 * @mr: the root memory region of address space 103 * 104 * Add the specified address space to the CPU's cpu_ases list. 105 * The address space added with @asidx 0 is the one used for the 106 * convenience pointer cpu->as. 107 * The target-specific code which registers ASes is responsible 108 * for defining what semantics address space 0, 1, 2, etc have. 109 * 110 * Before the first call to this function, the caller must set 111 * cpu->num_ases to the total number of address spaces it needs 112 * to support. 113 * 114 * Note that with KVM only one address space is supported. 115 */ 116 void cpu_address_space_init(CPUState *cpu, int asidx, 117 const char *prefix, MemoryRegion *mr); 118 119 void cpu_physical_memory_rw(hwaddr addr, void *buf, 120 hwaddr len, bool is_write); 121 static inline void cpu_physical_memory_read(hwaddr addr, 122 void *buf, hwaddr len) 123 { 124 cpu_physical_memory_rw(addr, buf, len, false); 125 } 126 static inline void cpu_physical_memory_write(hwaddr addr, 127 const void *buf, hwaddr len) 128 { 129 cpu_physical_memory_rw(addr, (void *)buf, len, true); 130 } 131 void cpu_reloading_memory_map(void); 132 void *cpu_physical_memory_map(hwaddr addr, 133 hwaddr *plen, 134 bool is_write); 135 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 136 bool is_write, hwaddr access_len); 137 void cpu_register_map_client(QEMUBH *bh); 138 void cpu_unregister_map_client(QEMUBH *bh); 139 140 bool cpu_physical_memory_is_io(hwaddr phys_addr); 141 142 /* Coalesced MMIO regions are areas where write operations can be reordered. 143 * This usually implies that write operations are side-effect free. This allows 144 * batching which can make a major impact on performance when using 145 * virtualization. 146 */ 147 void qemu_flush_coalesced_mmio_buffer(void); 148 149 void cpu_flush_icache_range(hwaddr start, hwaddr len); 150 151 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 152 153 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 154 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 155 156 #endif 157 158 /* Returns: 0 on success, -1 on error */ 159 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 160 void *ptr, size_t len, bool is_write); 161 162 /* vl.c */ 163 extern int singlestep; 164 165 void list_cpus(const char *optarg); 166 167 #endif /* CPU_COMMON_H */ 168