1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 3 4 /* CPU interfaces that are target independent. */ 5 6 #ifndef CONFIG_USER_ONLY 7 #include "exec/hwaddr.h" 8 #endif 9 10 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 11 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 12 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 13 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 14 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 15 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 16 17 /** 18 * vaddr: 19 * Type wide enough to contain any #target_ulong virtual address. 20 */ 21 typedef uint64_t vaddr; 22 #define VADDR_PRId PRId64 23 #define VADDR_PRIu PRIu64 24 #define VADDR_PRIo PRIo64 25 #define VADDR_PRIx PRIx64 26 #define VADDR_PRIX PRIX64 27 #define VADDR_MAX UINT64_MAX 28 29 void cpu_exec_init_all(void); 30 void cpu_exec_step_atomic(CPUState *cpu); 31 32 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 33 * when intptr_t is 32-bit and we are aligning a long long. 34 */ 35 extern uintptr_t qemu_host_page_size; 36 extern intptr_t qemu_host_page_mask; 37 38 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) 39 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size()) 40 41 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 42 extern QemuMutex qemu_cpu_list_lock; 43 void qemu_init_cpu_list(void); 44 void cpu_list_lock(void); 45 void cpu_list_unlock(void); 46 unsigned int cpu_list_generation_id_get(void); 47 48 void tcg_flush_softmmu_tlb(CPUState *cs); 49 void tcg_flush_jmp_cache(CPUState *cs); 50 51 void tcg_iommu_init_notifier_list(CPUState *cpu); 52 void tcg_iommu_free_notifier_list(CPUState *cpu); 53 54 #if !defined(CONFIG_USER_ONLY) 55 56 enum device_endian { 57 DEVICE_NATIVE_ENDIAN, 58 DEVICE_BIG_ENDIAN, 59 DEVICE_LITTLE_ENDIAN, 60 }; 61 62 #if HOST_BIG_ENDIAN 63 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 64 #else 65 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 66 #endif 67 68 /* address in the RAM (different from a physical address) */ 69 #if defined(CONFIG_XEN_BACKEND) 70 typedef uint64_t ram_addr_t; 71 # define RAM_ADDR_MAX UINT64_MAX 72 # define RAM_ADDR_FMT "%" PRIx64 73 #else 74 typedef uintptr_t ram_addr_t; 75 # define RAM_ADDR_MAX UINTPTR_MAX 76 # define RAM_ADDR_FMT "%" PRIxPTR 77 #endif 78 79 /* memory API */ 80 81 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 82 /* This should not be used by devices. */ 83 ram_addr_t qemu_ram_addr_from_host(void *ptr); 84 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 85 RAMBlock *qemu_ram_block_by_name(const char *name); 86 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 87 ram_addr_t *offset); 88 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 89 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 90 void qemu_ram_unset_idstr(RAMBlock *block); 91 const char *qemu_ram_get_idstr(RAMBlock *rb); 92 void *qemu_ram_get_host_addr(RAMBlock *rb); 93 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 94 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 95 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 96 bool qemu_ram_is_shared(RAMBlock *rb); 97 bool qemu_ram_is_noreserve(RAMBlock *rb); 98 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 99 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 100 bool qemu_ram_is_migratable(RAMBlock *rb); 101 void qemu_ram_set_migratable(RAMBlock *rb); 102 void qemu_ram_unset_migratable(RAMBlock *rb); 103 bool qemu_ram_is_named_file(RAMBlock *rb); 104 int qemu_ram_get_fd(RAMBlock *rb); 105 106 size_t qemu_ram_pagesize(RAMBlock *block); 107 size_t qemu_ram_pagesize_largest(void); 108 109 /** 110 * cpu_address_space_init: 111 * @cpu: CPU to add this address space to 112 * @asidx: integer index of this address space 113 * @prefix: prefix to be used as name of address space 114 * @mr: the root memory region of address space 115 * 116 * Add the specified address space to the CPU's cpu_ases list. 117 * The address space added with @asidx 0 is the one used for the 118 * convenience pointer cpu->as. 119 * The target-specific code which registers ASes is responsible 120 * for defining what semantics address space 0, 1, 2, etc have. 121 * 122 * Before the first call to this function, the caller must set 123 * cpu->num_ases to the total number of address spaces it needs 124 * to support. 125 * 126 * Note that with KVM only one address space is supported. 127 */ 128 void cpu_address_space_init(CPUState *cpu, int asidx, 129 const char *prefix, MemoryRegion *mr); 130 131 void cpu_physical_memory_rw(hwaddr addr, void *buf, 132 hwaddr len, bool is_write); 133 static inline void cpu_physical_memory_read(hwaddr addr, 134 void *buf, hwaddr len) 135 { 136 cpu_physical_memory_rw(addr, buf, len, false); 137 } 138 static inline void cpu_physical_memory_write(hwaddr addr, 139 const void *buf, hwaddr len) 140 { 141 cpu_physical_memory_rw(addr, (void *)buf, len, true); 142 } 143 void *cpu_physical_memory_map(hwaddr addr, 144 hwaddr *plen, 145 bool is_write); 146 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 147 bool is_write, hwaddr access_len); 148 void cpu_register_map_client(QEMUBH *bh); 149 void cpu_unregister_map_client(QEMUBH *bh); 150 151 bool cpu_physical_memory_is_io(hwaddr phys_addr); 152 153 /* Coalesced MMIO regions are areas where write operations can be reordered. 154 * This usually implies that write operations are side-effect free. This allows 155 * batching which can make a major impact on performance when using 156 * virtualization. 157 */ 158 void qemu_flush_coalesced_mmio_buffer(void); 159 160 void cpu_flush_icache_range(hwaddr start, hwaddr len); 161 162 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 163 164 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 165 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 166 167 #endif 168 169 /* Returns: 0 on success, -1 on error */ 170 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 171 void *ptr, size_t len, bool is_write); 172 173 /* vl.c */ 174 void list_cpus(void); 175 176 #ifdef CONFIG_TCG 177 /** 178 * cpu_unwind_state_data: 179 * @cpu: the cpu context 180 * @host_pc: the host pc within the translation 181 * @data: output data 182 * 183 * Attempt to load the the unwind state for a host pc occurring in 184 * translated code. If @host_pc is not in translated code, the 185 * function returns false; otherwise @data is loaded. 186 * This is the same unwind info as given to restore_state_to_opc. 187 */ 188 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); 189 190 /** 191 * cpu_restore_state: 192 * @cpu: the cpu context 193 * @host_pc: the host pc within the translation 194 * @return: true if state was restored, false otherwise 195 * 196 * Attempt to restore the state for a fault occurring in translated 197 * code. If @host_pc is not in translated code no state is 198 * restored and the function returns false. 199 */ 200 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); 201 202 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); 203 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 204 #endif /* CONFIG_TCG */ 205 G_NORETURN void cpu_loop_exit(CPUState *cpu); 206 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 207 208 #endif /* CPU_COMMON_H */ 209