1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 3 4 /* CPU interfaces that are target independent. */ 5 6 #include "exec/vaddr.h" 7 #ifndef CONFIG_USER_ONLY 8 #include "exec/hwaddr.h" 9 #endif 10 #include "hw/core/cpu.h" 11 #include "tcg/debug-assert.h" 12 13 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 14 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 15 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 16 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 17 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 18 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 19 20 void cpu_exec_init_all(void); 21 void cpu_exec_step_atomic(CPUState *cpu); 22 23 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 24 * when intptr_t is 32-bit and we are aligning a long long. 25 */ 26 extern uintptr_t qemu_host_page_size; 27 extern intptr_t qemu_host_page_mask; 28 29 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) 30 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size()) 31 32 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 33 extern QemuMutex qemu_cpu_list_lock; 34 void qemu_init_cpu_list(void); 35 void cpu_list_lock(void); 36 void cpu_list_unlock(void); 37 unsigned int cpu_list_generation_id_get(void); 38 39 void tcg_iommu_init_notifier_list(CPUState *cpu); 40 void tcg_iommu_free_notifier_list(CPUState *cpu); 41 42 #if !defined(CONFIG_USER_ONLY) 43 44 enum device_endian { 45 DEVICE_NATIVE_ENDIAN, 46 DEVICE_BIG_ENDIAN, 47 DEVICE_LITTLE_ENDIAN, 48 }; 49 50 #if HOST_BIG_ENDIAN 51 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 52 #else 53 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 54 #endif 55 56 /* address in the RAM (different from a physical address) */ 57 #if defined(CONFIG_XEN_BACKEND) 58 typedef uint64_t ram_addr_t; 59 # define RAM_ADDR_MAX UINT64_MAX 60 # define RAM_ADDR_FMT "%" PRIx64 61 #else 62 typedef uintptr_t ram_addr_t; 63 # define RAM_ADDR_MAX UINTPTR_MAX 64 # define RAM_ADDR_FMT "%" PRIxPTR 65 #endif 66 67 /* memory API */ 68 69 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 70 /* This should not be used by devices. */ 71 ram_addr_t qemu_ram_addr_from_host(void *ptr); 72 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 73 RAMBlock *qemu_ram_block_by_name(const char *name); 74 75 /* 76 * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock. 77 * 78 * @ptr: The host pointer to translate. 79 * @round_offset: Whether to round the result offset down to a target page 80 * @offset: Will be set to the offset within the returned RAMBlock. 81 * 82 * Returns: RAMBlock (or NULL if not found) 83 * 84 * By the time this function returns, the returned pointer is not protected 85 * by RCU anymore. If the caller is not within an RCU critical section and 86 * does not hold the BQL, it must have other means of protecting the 87 * pointer, such as a reference to the memory region that owns the RAMBlock. 88 */ 89 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 90 ram_addr_t *offset); 91 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 92 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 93 void qemu_ram_unset_idstr(RAMBlock *block); 94 const char *qemu_ram_get_idstr(RAMBlock *rb); 95 void *qemu_ram_get_host_addr(RAMBlock *rb); 96 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 97 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 98 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 99 bool qemu_ram_is_shared(RAMBlock *rb); 100 bool qemu_ram_is_noreserve(RAMBlock *rb); 101 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 102 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 103 bool qemu_ram_is_migratable(RAMBlock *rb); 104 void qemu_ram_set_migratable(RAMBlock *rb); 105 void qemu_ram_unset_migratable(RAMBlock *rb); 106 bool qemu_ram_is_named_file(RAMBlock *rb); 107 int qemu_ram_get_fd(RAMBlock *rb); 108 109 size_t qemu_ram_pagesize(RAMBlock *block); 110 size_t qemu_ram_pagesize_largest(void); 111 112 /** 113 * cpu_address_space_init: 114 * @cpu: CPU to add this address space to 115 * @asidx: integer index of this address space 116 * @prefix: prefix to be used as name of address space 117 * @mr: the root memory region of address space 118 * 119 * Add the specified address space to the CPU's cpu_ases list. 120 * The address space added with @asidx 0 is the one used for the 121 * convenience pointer cpu->as. 122 * The target-specific code which registers ASes is responsible 123 * for defining what semantics address space 0, 1, 2, etc have. 124 * 125 * Before the first call to this function, the caller must set 126 * cpu->num_ases to the total number of address spaces it needs 127 * to support. 128 * 129 * Note that with KVM only one address space is supported. 130 */ 131 void cpu_address_space_init(CPUState *cpu, int asidx, 132 const char *prefix, MemoryRegion *mr); 133 134 void cpu_physical_memory_rw(hwaddr addr, void *buf, 135 hwaddr len, bool is_write); 136 static inline void cpu_physical_memory_read(hwaddr addr, 137 void *buf, hwaddr len) 138 { 139 cpu_physical_memory_rw(addr, buf, len, false); 140 } 141 static inline void cpu_physical_memory_write(hwaddr addr, 142 const void *buf, hwaddr len) 143 { 144 cpu_physical_memory_rw(addr, (void *)buf, len, true); 145 } 146 void *cpu_physical_memory_map(hwaddr addr, 147 hwaddr *plen, 148 bool is_write); 149 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 150 bool is_write, hwaddr access_len); 151 void cpu_register_map_client(QEMUBH *bh); 152 void cpu_unregister_map_client(QEMUBH *bh); 153 154 bool cpu_physical_memory_is_io(hwaddr phys_addr); 155 156 /* Coalesced MMIO regions are areas where write operations can be reordered. 157 * This usually implies that write operations are side-effect free. This allows 158 * batching which can make a major impact on performance when using 159 * virtualization. 160 */ 161 void qemu_flush_coalesced_mmio_buffer(void); 162 163 void cpu_flush_icache_range(hwaddr start, hwaddr len); 164 165 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 166 167 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 168 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 169 170 #endif 171 172 /* Returns: 0 on success, -1 on error */ 173 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 174 void *ptr, size_t len, bool is_write); 175 176 /* vl.c */ 177 void list_cpus(void); 178 179 #ifdef CONFIG_TCG 180 /** 181 * cpu_unwind_state_data: 182 * @cpu: the cpu context 183 * @host_pc: the host pc within the translation 184 * @data: output data 185 * 186 * Attempt to load the the unwind state for a host pc occurring in 187 * translated code. If @host_pc is not in translated code, the 188 * function returns false; otherwise @data is loaded. 189 * This is the same unwind info as given to restore_state_to_opc. 190 */ 191 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); 192 193 /** 194 * cpu_restore_state: 195 * @cpu: the cpu context 196 * @host_pc: the host pc within the translation 197 * @return: true if state was restored, false otherwise 198 * 199 * Attempt to restore the state for a fault occurring in translated 200 * code. If @host_pc is not in translated code no state is 201 * restored and the function returns false. 202 */ 203 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); 204 205 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); 206 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 207 #endif /* CONFIG_TCG */ 208 G_NORETURN void cpu_loop_exit(CPUState *cpu); 209 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 210 211 /* same as PROT_xxx */ 212 #define PAGE_READ 0x0001 213 #define PAGE_WRITE 0x0002 214 #define PAGE_EXEC 0x0004 215 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 216 #define PAGE_VALID 0x0008 217 /* 218 * Original state of the write flag (used when tracking self-modifying code) 219 */ 220 #define PAGE_WRITE_ORG 0x0010 221 /* 222 * Invalidate the TLB entry immediately, helpful for s390x 223 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() 224 */ 225 #define PAGE_WRITE_INV 0x0020 226 /* For use with page_set_flags: page is being replaced; target_data cleared. */ 227 #define PAGE_RESET 0x0040 228 /* For linux-user, indicates that the page is MAP_ANON. */ 229 #define PAGE_ANON 0x0080 230 231 /* Target-specific bits that will be used via page_get_flags(). */ 232 #define PAGE_TARGET_1 0x0200 233 #define PAGE_TARGET_2 0x0400 234 235 /* 236 * For linux-user, indicates that the page is mapped with the same semantics 237 * in both guest and host. 238 */ 239 #define PAGE_PASSTHROUGH 0x0800 240 241 /* accel/tcg/cpu-exec.c */ 242 int cpu_exec(CPUState *cpu); 243 244 /** 245 * env_archcpu(env) 246 * @env: The architecture environment 247 * 248 * Return the ArchCPU associated with the environment. 249 */ 250 static inline ArchCPU *env_archcpu(CPUArchState *env) 251 { 252 return (void *)env - sizeof(CPUState); 253 } 254 255 /** 256 * env_cpu(env) 257 * @env: The architecture environment 258 * 259 * Return the CPUState associated with the environment. 260 */ 261 static inline CPUState *env_cpu(CPUArchState *env) 262 { 263 return (void *)env - sizeof(CPUState); 264 } 265 266 #ifndef CONFIG_USER_ONLY 267 /** 268 * cpu_mmu_index: 269 * @env: The cpu environment 270 * @ifetch: True for code access, false for data access. 271 * 272 * Return the core mmu index for the current translation regime. 273 * This function is used by generic TCG code paths. 274 * 275 * The user-only version of this function is inline in cpu-all.h, 276 * where it always returns MMU_USER_IDX. 277 */ 278 static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) 279 { 280 CPUState *cs = env_cpu(env); 281 int ret = cs->cc->mmu_index(cs, ifetch); 282 tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); 283 return ret; 284 } 285 #endif /* !CONFIG_USER_ONLY */ 286 287 #endif /* CPU_COMMON_H */ 288