xref: /openbmc/qemu/include/exec/cpu-common.h (revision 907b5105)
1 #ifndef CPU_COMMON_H
2 #define CPU_COMMON_H
3 
4 /* CPU interfaces that are target independent.  */
5 
6 #ifndef CONFIG_USER_ONLY
7 #include "exec/hwaddr.h"
8 #endif
9 
10 /**
11  * vaddr:
12  * Type wide enough to contain any #target_ulong virtual address.
13  */
14 typedef uint64_t vaddr;
15 #define VADDR_PRId PRId64
16 #define VADDR_PRIu PRIu64
17 #define VADDR_PRIo PRIo64
18 #define VADDR_PRIx PRIx64
19 #define VADDR_PRIX PRIX64
20 #define VADDR_MAX UINT64_MAX
21 
22 void cpu_exec_init_all(void);
23 void cpu_exec_step_atomic(CPUState *cpu);
24 
25 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
26  * when intptr_t is 32-bit and we are aligning a long long.
27  */
28 extern uintptr_t qemu_host_page_size;
29 extern intptr_t qemu_host_page_mask;
30 
31 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
32 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size())
33 
34 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
35 void qemu_init_cpu_list(void);
36 void cpu_list_lock(void);
37 void cpu_list_unlock(void);
38 
39 void tcg_flush_softmmu_tlb(CPUState *cs);
40 
41 void tcg_iommu_init_notifier_list(CPUState *cpu);
42 void tcg_iommu_free_notifier_list(CPUState *cpu);
43 
44 #if !defined(CONFIG_USER_ONLY)
45 
46 enum device_endian {
47     DEVICE_NATIVE_ENDIAN,
48     DEVICE_BIG_ENDIAN,
49     DEVICE_LITTLE_ENDIAN,
50 };
51 
52 #if HOST_BIG_ENDIAN
53 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
54 #else
55 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
56 #endif
57 
58 /* address in the RAM (different from a physical address) */
59 #if defined(CONFIG_XEN_BACKEND)
60 typedef uint64_t ram_addr_t;
61 #  define RAM_ADDR_MAX UINT64_MAX
62 #  define RAM_ADDR_FMT "%" PRIx64
63 #else
64 typedef uintptr_t ram_addr_t;
65 #  define RAM_ADDR_MAX UINTPTR_MAX
66 #  define RAM_ADDR_FMT "%" PRIxPTR
67 #endif
68 
69 /* memory API */
70 
71 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
72 /* This should not be used by devices.  */
73 ram_addr_t qemu_ram_addr_from_host(void *ptr);
74 RAMBlock *qemu_ram_block_by_name(const char *name);
75 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
76                                    ram_addr_t *offset);
77 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
78 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
79 void qemu_ram_unset_idstr(RAMBlock *block);
80 const char *qemu_ram_get_idstr(RAMBlock *rb);
81 void *qemu_ram_get_host_addr(RAMBlock *rb);
82 ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
83 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
84 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb);
85 bool qemu_ram_is_shared(RAMBlock *rb);
86 bool qemu_ram_is_noreserve(RAMBlock *rb);
87 bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
88 void qemu_ram_set_uf_zeroable(RAMBlock *rb);
89 bool qemu_ram_is_migratable(RAMBlock *rb);
90 void qemu_ram_set_migratable(RAMBlock *rb);
91 void qemu_ram_unset_migratable(RAMBlock *rb);
92 
93 size_t qemu_ram_pagesize(RAMBlock *block);
94 size_t qemu_ram_pagesize_largest(void);
95 
96 /**
97  * cpu_address_space_init:
98  * @cpu: CPU to add this address space to
99  * @asidx: integer index of this address space
100  * @prefix: prefix to be used as name of address space
101  * @mr: the root memory region of address space
102  *
103  * Add the specified address space to the CPU's cpu_ases list.
104  * The address space added with @asidx 0 is the one used for the
105  * convenience pointer cpu->as.
106  * The target-specific code which registers ASes is responsible
107  * for defining what semantics address space 0, 1, 2, etc have.
108  *
109  * Before the first call to this function, the caller must set
110  * cpu->num_ases to the total number of address spaces it needs
111  * to support.
112  *
113  * Note that with KVM only one address space is supported.
114  */
115 void cpu_address_space_init(CPUState *cpu, int asidx,
116                             const char *prefix, MemoryRegion *mr);
117 
118 void cpu_physical_memory_rw(hwaddr addr, void *buf,
119                             hwaddr len, bool is_write);
120 static inline void cpu_physical_memory_read(hwaddr addr,
121                                             void *buf, hwaddr len)
122 {
123     cpu_physical_memory_rw(addr, buf, len, false);
124 }
125 static inline void cpu_physical_memory_write(hwaddr addr,
126                                              const void *buf, hwaddr len)
127 {
128     cpu_physical_memory_rw(addr, (void *)buf, len, true);
129 }
130 void cpu_reloading_memory_map(void);
131 void *cpu_physical_memory_map(hwaddr addr,
132                               hwaddr *plen,
133                               bool is_write);
134 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
135                                bool is_write, hwaddr access_len);
136 void cpu_register_map_client(QEMUBH *bh);
137 void cpu_unregister_map_client(QEMUBH *bh);
138 
139 bool cpu_physical_memory_is_io(hwaddr phys_addr);
140 
141 /* Coalesced MMIO regions are areas where write operations can be reordered.
142  * This usually implies that write operations are side-effect free.  This allows
143  * batching which can make a major impact on performance when using
144  * virtualization.
145  */
146 void qemu_flush_coalesced_mmio_buffer(void);
147 
148 void cpu_flush_icache_range(hwaddr start, hwaddr len);
149 
150 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
151 
152 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
153 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
154 
155 #endif
156 
157 /* Returns: 0 on success, -1 on error */
158 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
159                         void *ptr, size_t len, bool is_write);
160 
161 /* vl.c */
162 extern int singlestep;
163 
164 void list_cpus(const char *optarg);
165 
166 #endif /* CPU_COMMON_H */
167