1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 1 3 4 /* CPU interfaces that are target independent. */ 5 6 #include "exec/hwaddr.h" 7 8 #ifndef NEED_CPU_H 9 #include "exec/poison.h" 10 #endif 11 12 #include "qemu/bswap.h" 13 #include "qemu/queue.h" 14 15 /** 16 * CPUListState: 17 * @cpu_fprintf: Print function. 18 * @file: File to print to using @cpu_fprint. 19 * 20 * State commonly used for iterating over CPU models. 21 */ 22 typedef struct CPUListState { 23 fprintf_function cpu_fprintf; 24 FILE *file; 25 } CPUListState; 26 27 #if !defined(CONFIG_USER_ONLY) 28 29 enum device_endian { 30 DEVICE_NATIVE_ENDIAN, 31 DEVICE_BIG_ENDIAN, 32 DEVICE_LITTLE_ENDIAN, 33 }; 34 35 /* address in the RAM (different from a physical address) */ 36 #if defined(CONFIG_XEN_BACKEND) 37 typedef uint64_t ram_addr_t; 38 # define RAM_ADDR_MAX UINT64_MAX 39 # define RAM_ADDR_FMT "%" PRIx64 40 #else 41 typedef uintptr_t ram_addr_t; 42 # define RAM_ADDR_MAX UINTPTR_MAX 43 # define RAM_ADDR_FMT "%" PRIxPTR 44 #endif 45 46 /* memory API */ 47 48 typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value); 49 typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); 50 51 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 52 /* This should not be used by devices. */ 53 int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); 54 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 55 void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev); 56 57 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, 58 int len, int is_write); 59 static inline void cpu_physical_memory_read(hwaddr addr, 60 void *buf, int len) 61 { 62 cpu_physical_memory_rw(addr, buf, len, 0); 63 } 64 static inline void cpu_physical_memory_write(hwaddr addr, 65 const void *buf, int len) 66 { 67 cpu_physical_memory_rw(addr, (void *)buf, len, 1); 68 } 69 void *cpu_physical_memory_map(hwaddr addr, 70 hwaddr *plen, 71 int is_write); 72 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 73 int is_write, hwaddr access_len); 74 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); 75 76 bool cpu_physical_memory_is_io(hwaddr phys_addr); 77 78 /* Coalesced MMIO regions are areas where write operations can be reordered. 79 * This usually implies that write operations are side-effect free. This allows 80 * batching which can make a major impact on performance when using 81 * virtualization. 82 */ 83 void qemu_flush_coalesced_mmio_buffer(void); 84 85 uint32_t ldub_phys(hwaddr addr); 86 uint32_t lduw_le_phys(hwaddr addr); 87 uint32_t lduw_be_phys(hwaddr addr); 88 uint32_t ldl_le_phys(hwaddr addr); 89 uint32_t ldl_be_phys(hwaddr addr); 90 uint64_t ldq_le_phys(hwaddr addr); 91 uint64_t ldq_be_phys(hwaddr addr); 92 void stb_phys(hwaddr addr, uint32_t val); 93 void stw_le_phys(hwaddr addr, uint32_t val); 94 void stw_be_phys(hwaddr addr, uint32_t val); 95 void stl_le_phys(hwaddr addr, uint32_t val); 96 void stl_be_phys(hwaddr addr, uint32_t val); 97 void stq_le_phys(hwaddr addr, uint64_t val); 98 void stq_be_phys(hwaddr addr, uint64_t val); 99 100 #ifdef NEED_CPU_H 101 uint32_t lduw_phys(hwaddr addr); 102 uint32_t ldl_phys(hwaddr addr); 103 uint64_t ldq_phys(hwaddr addr); 104 void stl_phys_notdirty(hwaddr addr, uint32_t val); 105 void stw_phys(hwaddr addr, uint32_t val); 106 void stl_phys(hwaddr addr, uint32_t val); 107 void stq_phys(hwaddr addr, uint64_t val); 108 #endif 109 110 void cpu_physical_memory_write_rom(hwaddr addr, 111 const uint8_t *buf, int len); 112 113 extern struct MemoryRegion io_mem_rom; 114 extern struct MemoryRegion io_mem_notdirty; 115 116 #endif 117 118 #endif /* !CPU_COMMON_H */ 119