1 /* 2 * CPU interfaces that are target independent. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * SPDX-License-Identifier: LGPL-2.1+ 7 */ 8 #ifndef CPU_COMMON_H 9 #define CPU_COMMON_H 10 11 #include "exec/vaddr.h" 12 #ifndef CONFIG_USER_ONLY 13 #include "exec/hwaddr.h" 14 #endif 15 #include "hw/core/cpu.h" 16 #include "tcg/debug-assert.h" 17 18 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 19 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 20 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 21 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 22 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 23 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 24 25 void cpu_exec_init_all(void); 26 void cpu_exec_step_atomic(CPUState *cpu); 27 28 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size()) 29 30 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 31 extern QemuMutex qemu_cpu_list_lock; 32 void qemu_init_cpu_list(void); 33 void cpu_list_lock(void); 34 void cpu_list_unlock(void); 35 unsigned int cpu_list_generation_id_get(void); 36 37 void tcg_iommu_init_notifier_list(CPUState *cpu); 38 void tcg_iommu_free_notifier_list(CPUState *cpu); 39 40 #if !defined(CONFIG_USER_ONLY) 41 42 enum device_endian { 43 DEVICE_NATIVE_ENDIAN, 44 DEVICE_BIG_ENDIAN, 45 DEVICE_LITTLE_ENDIAN, 46 }; 47 48 #if HOST_BIG_ENDIAN 49 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 50 #else 51 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 52 #endif 53 54 /* address in the RAM (different from a physical address) */ 55 #if defined(CONFIG_XEN_BACKEND) 56 typedef uint64_t ram_addr_t; 57 # define RAM_ADDR_MAX UINT64_MAX 58 # define RAM_ADDR_FMT "%" PRIx64 59 #else 60 typedef uintptr_t ram_addr_t; 61 # define RAM_ADDR_MAX UINTPTR_MAX 62 # define RAM_ADDR_FMT "%" PRIxPTR 63 #endif 64 65 /* memory API */ 66 67 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 68 /* This should not be used by devices. */ 69 ram_addr_t qemu_ram_addr_from_host(void *ptr); 70 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 71 RAMBlock *qemu_ram_block_by_name(const char *name); 72 73 /* 74 * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock. 75 * 76 * @ptr: The host pointer to translate. 77 * @round_offset: Whether to round the result offset down to a target page 78 * @offset: Will be set to the offset within the returned RAMBlock. 79 * 80 * Returns: RAMBlock (or NULL if not found) 81 * 82 * By the time this function returns, the returned pointer is not protected 83 * by RCU anymore. If the caller is not within an RCU critical section and 84 * does not hold the BQL, it must have other means of protecting the 85 * pointer, such as a reference to the memory region that owns the RAMBlock. 86 */ 87 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 88 ram_addr_t *offset); 89 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 90 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 91 void qemu_ram_unset_idstr(RAMBlock *block); 92 const char *qemu_ram_get_idstr(RAMBlock *rb); 93 void *qemu_ram_get_host_addr(RAMBlock *rb); 94 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 95 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 96 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 97 bool qemu_ram_is_shared(RAMBlock *rb); 98 bool qemu_ram_is_noreserve(RAMBlock *rb); 99 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 100 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 101 bool qemu_ram_is_migratable(RAMBlock *rb); 102 void qemu_ram_set_migratable(RAMBlock *rb); 103 void qemu_ram_unset_migratable(RAMBlock *rb); 104 bool qemu_ram_is_named_file(RAMBlock *rb); 105 int qemu_ram_get_fd(RAMBlock *rb); 106 107 size_t qemu_ram_pagesize(RAMBlock *block); 108 size_t qemu_ram_pagesize_largest(void); 109 110 /** 111 * cpu_address_space_init: 112 * @cpu: CPU to add this address space to 113 * @asidx: integer index of this address space 114 * @prefix: prefix to be used as name of address space 115 * @mr: the root memory region of address space 116 * 117 * Add the specified address space to the CPU's cpu_ases list. 118 * The address space added with @asidx 0 is the one used for the 119 * convenience pointer cpu->as. 120 * The target-specific code which registers ASes is responsible 121 * for defining what semantics address space 0, 1, 2, etc have. 122 * 123 * Before the first call to this function, the caller must set 124 * cpu->num_ases to the total number of address spaces it needs 125 * to support. 126 * 127 * Note that with KVM only one address space is supported. 128 */ 129 void cpu_address_space_init(CPUState *cpu, int asidx, 130 const char *prefix, MemoryRegion *mr); 131 132 void cpu_physical_memory_rw(hwaddr addr, void *buf, 133 hwaddr len, bool is_write); 134 static inline void cpu_physical_memory_read(hwaddr addr, 135 void *buf, hwaddr len) 136 { 137 cpu_physical_memory_rw(addr, buf, len, false); 138 } 139 static inline void cpu_physical_memory_write(hwaddr addr, 140 const void *buf, hwaddr len) 141 { 142 cpu_physical_memory_rw(addr, (void *)buf, len, true); 143 } 144 void *cpu_physical_memory_map(hwaddr addr, 145 hwaddr *plen, 146 bool is_write); 147 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 148 bool is_write, hwaddr access_len); 149 void cpu_register_map_client(QEMUBH *bh); 150 void cpu_unregister_map_client(QEMUBH *bh); 151 152 bool cpu_physical_memory_is_io(hwaddr phys_addr); 153 154 /* Coalesced MMIO regions are areas where write operations can be reordered. 155 * This usually implies that write operations are side-effect free. This allows 156 * batching which can make a major impact on performance when using 157 * virtualization. 158 */ 159 void qemu_flush_coalesced_mmio_buffer(void); 160 161 void cpu_flush_icache_range(hwaddr start, hwaddr len); 162 163 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 164 165 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 166 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 167 int ram_block_discard_guest_memfd_range(RAMBlock *rb, uint64_t start, 168 size_t length); 169 170 #endif 171 172 /* Returns: 0 on success, -1 on error */ 173 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 174 void *ptr, size_t len, bool is_write); 175 176 /* vl.c */ 177 void list_cpus(void); 178 179 #ifdef CONFIG_TCG 180 /** 181 * cpu_unwind_state_data: 182 * @cpu: the cpu context 183 * @host_pc: the host pc within the translation 184 * @data: output data 185 * 186 * Attempt to load the the unwind state for a host pc occurring in 187 * translated code. If @host_pc is not in translated code, the 188 * function returns false; otherwise @data is loaded. 189 * This is the same unwind info as given to restore_state_to_opc. 190 */ 191 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); 192 193 /** 194 * cpu_restore_state: 195 * @cpu: the cpu context 196 * @host_pc: the host pc within the translation 197 * @return: true if state was restored, false otherwise 198 * 199 * Attempt to restore the state for a fault occurring in translated 200 * code. If @host_pc is not in translated code no state is 201 * restored and the function returns false. 202 */ 203 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); 204 205 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); 206 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 207 #endif /* CONFIG_TCG */ 208 G_NORETURN void cpu_loop_exit(CPUState *cpu); 209 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 210 211 /* same as PROT_xxx */ 212 #define PAGE_READ 0x0001 213 #define PAGE_WRITE 0x0002 214 #define PAGE_EXEC 0x0004 215 #define PAGE_RWX (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 216 #define PAGE_VALID 0x0008 217 /* 218 * Original state of the write flag (used when tracking self-modifying code) 219 */ 220 #define PAGE_WRITE_ORG 0x0010 221 /* 222 * Invalidate the TLB entry immediately, helpful for s390x 223 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() 224 */ 225 #define PAGE_WRITE_INV 0x0020 226 /* For use with page_set_flags: page is being replaced; target_data cleared. */ 227 #define PAGE_RESET 0x0040 228 /* For linux-user, indicates that the page is MAP_ANON. */ 229 #define PAGE_ANON 0x0080 230 231 /* Target-specific bits that will be used via page_get_flags(). */ 232 #define PAGE_TARGET_1 0x0200 233 #define PAGE_TARGET_2 0x0400 234 235 /* 236 * For linux-user, indicates that the page is mapped with the same semantics 237 * in both guest and host. 238 */ 239 #define PAGE_PASSTHROUGH 0x0800 240 241 /* accel/tcg/cpu-exec.c */ 242 int cpu_exec(CPUState *cpu); 243 244 /** 245 * env_archcpu(env) 246 * @env: The architecture environment 247 * 248 * Return the ArchCPU associated with the environment. 249 */ 250 static inline ArchCPU *env_archcpu(CPUArchState *env) 251 { 252 return (void *)env - sizeof(CPUState); 253 } 254 255 /** 256 * env_cpu(env) 257 * @env: The architecture environment 258 * 259 * Return the CPUState associated with the environment. 260 */ 261 static inline CPUState *env_cpu(CPUArchState *env) 262 { 263 return (void *)env - sizeof(CPUState); 264 } 265 266 #ifndef CONFIG_USER_ONLY 267 /** 268 * cpu_mmu_index: 269 * @env: The cpu environment 270 * @ifetch: True for code access, false for data access. 271 * 272 * Return the core mmu index for the current translation regime. 273 * This function is used by generic TCG code paths. 274 * 275 * The user-only version of this function is inline in cpu-all.h, 276 * where it always returns MMU_USER_IDX. 277 */ 278 static inline int cpu_mmu_index(CPUState *cs, bool ifetch) 279 { 280 int ret = cs->cc->mmu_index(cs, ifetch); 281 tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); 282 return ret; 283 } 284 #endif /* !CONFIG_USER_ONLY */ 285 286 #endif /* CPU_COMMON_H */ 287