1 /* 2 * CPU interfaces that are target independent. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * SPDX-License-Identifier: LGPL-2.1+ 7 */ 8 #ifndef CPU_COMMON_H 9 #define CPU_COMMON_H 10 11 #include "exec/vaddr.h" 12 #ifndef CONFIG_USER_ONLY 13 #include "exec/hwaddr.h" 14 #endif 15 #include "hw/core/cpu.h" 16 #include "tcg/debug-assert.h" 17 #include "exec/page-protection.h" 18 19 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 20 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 21 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 22 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 23 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 24 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 25 26 void cpu_exec_init_all(void); 27 void cpu_exec_step_atomic(CPUState *cpu); 28 29 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size()) 30 31 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 32 extern QemuMutex qemu_cpu_list_lock; 33 void qemu_init_cpu_list(void); 34 void cpu_list_lock(void); 35 void cpu_list_unlock(void); 36 unsigned int cpu_list_generation_id_get(void); 37 38 void tcg_iommu_init_notifier_list(CPUState *cpu); 39 void tcg_iommu_free_notifier_list(CPUState *cpu); 40 41 #if !defined(CONFIG_USER_ONLY) 42 43 enum device_endian { 44 DEVICE_NATIVE_ENDIAN, 45 DEVICE_BIG_ENDIAN, 46 DEVICE_LITTLE_ENDIAN, 47 }; 48 49 #if HOST_BIG_ENDIAN 50 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 51 #else 52 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 53 #endif 54 55 /* address in the RAM (different from a physical address) */ 56 #if defined(CONFIG_XEN_BACKEND) 57 typedef uint64_t ram_addr_t; 58 # define RAM_ADDR_MAX UINT64_MAX 59 # define RAM_ADDR_FMT "%" PRIx64 60 #else 61 typedef uintptr_t ram_addr_t; 62 # define RAM_ADDR_MAX UINTPTR_MAX 63 # define RAM_ADDR_FMT "%" PRIxPTR 64 #endif 65 66 /* memory API */ 67 68 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 69 /* This should not be used by devices. */ 70 ram_addr_t qemu_ram_addr_from_host(void *ptr); 71 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 72 RAMBlock *qemu_ram_block_by_name(const char *name); 73 74 /* 75 * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock. 76 * 77 * @ptr: The host pointer to translate. 78 * @round_offset: Whether to round the result offset down to a target page 79 * @offset: Will be set to the offset within the returned RAMBlock. 80 * 81 * Returns: RAMBlock (or NULL if not found) 82 * 83 * By the time this function returns, the returned pointer is not protected 84 * by RCU anymore. If the caller is not within an RCU critical section and 85 * does not hold the BQL, it must have other means of protecting the 86 * pointer, such as a reference to the memory region that owns the RAMBlock. 87 */ 88 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 89 ram_addr_t *offset); 90 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 91 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 92 void qemu_ram_unset_idstr(RAMBlock *block); 93 const char *qemu_ram_get_idstr(RAMBlock *rb); 94 void *qemu_ram_get_host_addr(RAMBlock *rb); 95 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 96 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 97 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 98 bool qemu_ram_is_shared(RAMBlock *rb); 99 bool qemu_ram_is_noreserve(RAMBlock *rb); 100 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 101 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 102 bool qemu_ram_is_migratable(RAMBlock *rb); 103 void qemu_ram_set_migratable(RAMBlock *rb); 104 void qemu_ram_unset_migratable(RAMBlock *rb); 105 bool qemu_ram_is_named_file(RAMBlock *rb); 106 int qemu_ram_get_fd(RAMBlock *rb); 107 108 size_t qemu_ram_pagesize(RAMBlock *block); 109 size_t qemu_ram_pagesize_largest(void); 110 111 /** 112 * cpu_address_space_init: 113 * @cpu: CPU to add this address space to 114 * @asidx: integer index of this address space 115 * @prefix: prefix to be used as name of address space 116 * @mr: the root memory region of address space 117 * 118 * Add the specified address space to the CPU's cpu_ases list. 119 * The address space added with @asidx 0 is the one used for the 120 * convenience pointer cpu->as. 121 * The target-specific code which registers ASes is responsible 122 * for defining what semantics address space 0, 1, 2, etc have. 123 * 124 * Before the first call to this function, the caller must set 125 * cpu->num_ases to the total number of address spaces it needs 126 * to support. 127 * 128 * Note that with KVM only one address space is supported. 129 */ 130 void cpu_address_space_init(CPUState *cpu, int asidx, 131 const char *prefix, MemoryRegion *mr); 132 133 void cpu_physical_memory_rw(hwaddr addr, void *buf, 134 hwaddr len, bool is_write); 135 static inline void cpu_physical_memory_read(hwaddr addr, 136 void *buf, hwaddr len) 137 { 138 cpu_physical_memory_rw(addr, buf, len, false); 139 } 140 static inline void cpu_physical_memory_write(hwaddr addr, 141 const void *buf, hwaddr len) 142 { 143 cpu_physical_memory_rw(addr, (void *)buf, len, true); 144 } 145 void *cpu_physical_memory_map(hwaddr addr, 146 hwaddr *plen, 147 bool is_write); 148 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 149 bool is_write, hwaddr access_len); 150 void cpu_register_map_client(QEMUBH *bh); 151 void cpu_unregister_map_client(QEMUBH *bh); 152 153 bool cpu_physical_memory_is_io(hwaddr phys_addr); 154 155 /* Coalesced MMIO regions are areas where write operations can be reordered. 156 * This usually implies that write operations are side-effect free. This allows 157 * batching which can make a major impact on performance when using 158 * virtualization. 159 */ 160 void qemu_flush_coalesced_mmio_buffer(void); 161 162 void cpu_flush_icache_range(hwaddr start, hwaddr len); 163 164 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 165 166 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 167 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 168 int ram_block_discard_guest_memfd_range(RAMBlock *rb, uint64_t start, 169 size_t length); 170 171 #endif 172 173 /* Returns: 0 on success, -1 on error */ 174 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 175 void *ptr, size_t len, bool is_write); 176 177 /* vl.c */ 178 void list_cpus(void); 179 180 #ifdef CONFIG_TCG 181 182 bool tcg_cflags_has(CPUState *cpu, uint32_t flags); 183 void tcg_cflags_set(CPUState *cpu, uint32_t flags); 184 185 /* current cflags for hashing/comparison */ 186 uint32_t curr_cflags(CPUState *cpu); 187 188 /** 189 * cpu_unwind_state_data: 190 * @cpu: the cpu context 191 * @host_pc: the host pc within the translation 192 * @data: output data 193 * 194 * Attempt to load the the unwind state for a host pc occurring in 195 * translated code. If @host_pc is not in translated code, the 196 * function returns false; otherwise @data is loaded. 197 * This is the same unwind info as given to restore_state_to_opc. 198 */ 199 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); 200 201 /** 202 * cpu_restore_state: 203 * @cpu: the cpu context 204 * @host_pc: the host pc within the translation 205 * @return: true if state was restored, false otherwise 206 * 207 * Attempt to restore the state for a fault occurring in translated 208 * code. If @host_pc is not in translated code no state is 209 * restored and the function returns false. 210 */ 211 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); 212 213 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); 214 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 215 #endif /* CONFIG_TCG */ 216 G_NORETURN void cpu_loop_exit(CPUState *cpu); 217 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 218 219 /* accel/tcg/cpu-exec.c */ 220 int cpu_exec(CPUState *cpu); 221 222 /** 223 * env_archcpu(env) 224 * @env: The architecture environment 225 * 226 * Return the ArchCPU associated with the environment. 227 */ 228 static inline ArchCPU *env_archcpu(CPUArchState *env) 229 { 230 return (void *)env - sizeof(CPUState); 231 } 232 233 /** 234 * env_cpu(env) 235 * @env: The architecture environment 236 * 237 * Return the CPUState associated with the environment. 238 */ 239 static inline CPUState *env_cpu(CPUArchState *env) 240 { 241 return (void *)env - sizeof(CPUState); 242 } 243 244 #ifndef CONFIG_USER_ONLY 245 /** 246 * cpu_mmu_index: 247 * @env: The cpu environment 248 * @ifetch: True for code access, false for data access. 249 * 250 * Return the core mmu index for the current translation regime. 251 * This function is used by generic TCG code paths. 252 * 253 * The user-only version of this function is inline in cpu-all.h, 254 * where it always returns MMU_USER_IDX. 255 */ 256 static inline int cpu_mmu_index(CPUState *cs, bool ifetch) 257 { 258 int ret = cs->cc->mmu_index(cs, ifetch); 259 tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); 260 return ret; 261 } 262 #endif /* !CONFIG_USER_ONLY */ 263 264 #endif /* CPU_COMMON_H */ 265