1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 3 4 /* CPU interfaces that are target independent. */ 5 6 #include "exec/vaddr.h" 7 #ifndef CONFIG_USER_ONLY 8 #include "exec/hwaddr.h" 9 #endif 10 #include "hw/core/cpu.h" 11 #include "tcg/debug-assert.h" 12 13 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 14 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 15 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 16 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 17 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 18 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 19 20 void cpu_exec_init_all(void); 21 void cpu_exec_step_atomic(CPUState *cpu); 22 23 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size()) 24 25 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 26 extern QemuMutex qemu_cpu_list_lock; 27 void qemu_init_cpu_list(void); 28 void cpu_list_lock(void); 29 void cpu_list_unlock(void); 30 unsigned int cpu_list_generation_id_get(void); 31 32 void tcg_iommu_init_notifier_list(CPUState *cpu); 33 void tcg_iommu_free_notifier_list(CPUState *cpu); 34 35 #if !defined(CONFIG_USER_ONLY) 36 37 enum device_endian { 38 DEVICE_NATIVE_ENDIAN, 39 DEVICE_BIG_ENDIAN, 40 DEVICE_LITTLE_ENDIAN, 41 }; 42 43 #if HOST_BIG_ENDIAN 44 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 45 #else 46 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 47 #endif 48 49 /* address in the RAM (different from a physical address) */ 50 #if defined(CONFIG_XEN_BACKEND) 51 typedef uint64_t ram_addr_t; 52 # define RAM_ADDR_MAX UINT64_MAX 53 # define RAM_ADDR_FMT "%" PRIx64 54 #else 55 typedef uintptr_t ram_addr_t; 56 # define RAM_ADDR_MAX UINTPTR_MAX 57 # define RAM_ADDR_FMT "%" PRIxPTR 58 #endif 59 60 /* memory API */ 61 62 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 63 /* This should not be used by devices. */ 64 ram_addr_t qemu_ram_addr_from_host(void *ptr); 65 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 66 RAMBlock *qemu_ram_block_by_name(const char *name); 67 68 /* 69 * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock. 70 * 71 * @ptr: The host pointer to translate. 72 * @round_offset: Whether to round the result offset down to a target page 73 * @offset: Will be set to the offset within the returned RAMBlock. 74 * 75 * Returns: RAMBlock (or NULL if not found) 76 * 77 * By the time this function returns, the returned pointer is not protected 78 * by RCU anymore. If the caller is not within an RCU critical section and 79 * does not hold the BQL, it must have other means of protecting the 80 * pointer, such as a reference to the memory region that owns the RAMBlock. 81 */ 82 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 83 ram_addr_t *offset); 84 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 85 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 86 void qemu_ram_unset_idstr(RAMBlock *block); 87 const char *qemu_ram_get_idstr(RAMBlock *rb); 88 void *qemu_ram_get_host_addr(RAMBlock *rb); 89 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 90 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 91 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 92 bool qemu_ram_is_shared(RAMBlock *rb); 93 bool qemu_ram_is_noreserve(RAMBlock *rb); 94 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 95 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 96 bool qemu_ram_is_migratable(RAMBlock *rb); 97 void qemu_ram_set_migratable(RAMBlock *rb); 98 void qemu_ram_unset_migratable(RAMBlock *rb); 99 bool qemu_ram_is_named_file(RAMBlock *rb); 100 int qemu_ram_get_fd(RAMBlock *rb); 101 102 size_t qemu_ram_pagesize(RAMBlock *block); 103 size_t qemu_ram_pagesize_largest(void); 104 105 /** 106 * cpu_address_space_init: 107 * @cpu: CPU to add this address space to 108 * @asidx: integer index of this address space 109 * @prefix: prefix to be used as name of address space 110 * @mr: the root memory region of address space 111 * 112 * Add the specified address space to the CPU's cpu_ases list. 113 * The address space added with @asidx 0 is the one used for the 114 * convenience pointer cpu->as. 115 * The target-specific code which registers ASes is responsible 116 * for defining what semantics address space 0, 1, 2, etc have. 117 * 118 * Before the first call to this function, the caller must set 119 * cpu->num_ases to the total number of address spaces it needs 120 * to support. 121 * 122 * Note that with KVM only one address space is supported. 123 */ 124 void cpu_address_space_init(CPUState *cpu, int asidx, 125 const char *prefix, MemoryRegion *mr); 126 127 void cpu_physical_memory_rw(hwaddr addr, void *buf, 128 hwaddr len, bool is_write); 129 static inline void cpu_physical_memory_read(hwaddr addr, 130 void *buf, hwaddr len) 131 { 132 cpu_physical_memory_rw(addr, buf, len, false); 133 } 134 static inline void cpu_physical_memory_write(hwaddr addr, 135 const void *buf, hwaddr len) 136 { 137 cpu_physical_memory_rw(addr, (void *)buf, len, true); 138 } 139 void *cpu_physical_memory_map(hwaddr addr, 140 hwaddr *plen, 141 bool is_write); 142 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 143 bool is_write, hwaddr access_len); 144 void cpu_register_map_client(QEMUBH *bh); 145 void cpu_unregister_map_client(QEMUBH *bh); 146 147 bool cpu_physical_memory_is_io(hwaddr phys_addr); 148 149 /* Coalesced MMIO regions are areas where write operations can be reordered. 150 * This usually implies that write operations are side-effect free. This allows 151 * batching which can make a major impact on performance when using 152 * virtualization. 153 */ 154 void qemu_flush_coalesced_mmio_buffer(void); 155 156 void cpu_flush_icache_range(hwaddr start, hwaddr len); 157 158 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 159 160 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 161 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 162 163 #endif 164 165 /* Returns: 0 on success, -1 on error */ 166 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 167 void *ptr, size_t len, bool is_write); 168 169 /* vl.c */ 170 void list_cpus(void); 171 172 #ifdef CONFIG_TCG 173 /** 174 * cpu_unwind_state_data: 175 * @cpu: the cpu context 176 * @host_pc: the host pc within the translation 177 * @data: output data 178 * 179 * Attempt to load the the unwind state for a host pc occurring in 180 * translated code. If @host_pc is not in translated code, the 181 * function returns false; otherwise @data is loaded. 182 * This is the same unwind info as given to restore_state_to_opc. 183 */ 184 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); 185 186 /** 187 * cpu_restore_state: 188 * @cpu: the cpu context 189 * @host_pc: the host pc within the translation 190 * @return: true if state was restored, false otherwise 191 * 192 * Attempt to restore the state for a fault occurring in translated 193 * code. If @host_pc is not in translated code no state is 194 * restored and the function returns false. 195 */ 196 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); 197 198 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); 199 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 200 #endif /* CONFIG_TCG */ 201 G_NORETURN void cpu_loop_exit(CPUState *cpu); 202 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 203 204 /* same as PROT_xxx */ 205 #define PAGE_READ 0x0001 206 #define PAGE_WRITE 0x0002 207 #define PAGE_EXEC 0x0004 208 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 209 #define PAGE_VALID 0x0008 210 /* 211 * Original state of the write flag (used when tracking self-modifying code) 212 */ 213 #define PAGE_WRITE_ORG 0x0010 214 /* 215 * Invalidate the TLB entry immediately, helpful for s390x 216 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() 217 */ 218 #define PAGE_WRITE_INV 0x0020 219 /* For use with page_set_flags: page is being replaced; target_data cleared. */ 220 #define PAGE_RESET 0x0040 221 /* For linux-user, indicates that the page is MAP_ANON. */ 222 #define PAGE_ANON 0x0080 223 224 /* Target-specific bits that will be used via page_get_flags(). */ 225 #define PAGE_TARGET_1 0x0200 226 #define PAGE_TARGET_2 0x0400 227 228 /* 229 * For linux-user, indicates that the page is mapped with the same semantics 230 * in both guest and host. 231 */ 232 #define PAGE_PASSTHROUGH 0x0800 233 234 /* accel/tcg/cpu-exec.c */ 235 int cpu_exec(CPUState *cpu); 236 237 /** 238 * env_archcpu(env) 239 * @env: The architecture environment 240 * 241 * Return the ArchCPU associated with the environment. 242 */ 243 static inline ArchCPU *env_archcpu(CPUArchState *env) 244 { 245 return (void *)env - sizeof(CPUState); 246 } 247 248 /** 249 * env_cpu(env) 250 * @env: The architecture environment 251 * 252 * Return the CPUState associated with the environment. 253 */ 254 static inline CPUState *env_cpu(CPUArchState *env) 255 { 256 return (void *)env - sizeof(CPUState); 257 } 258 259 #ifndef CONFIG_USER_ONLY 260 /** 261 * cpu_mmu_index: 262 * @env: The cpu environment 263 * @ifetch: True for code access, false for data access. 264 * 265 * Return the core mmu index for the current translation regime. 266 * This function is used by generic TCG code paths. 267 * 268 * The user-only version of this function is inline in cpu-all.h, 269 * where it always returns MMU_USER_IDX. 270 */ 271 static inline int cpu_mmu_index(CPUState *cs, bool ifetch) 272 { 273 int ret = cs->cc->mmu_index(cs, ifetch); 274 tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); 275 return ret; 276 } 277 #endif /* !CONFIG_USER_ONLY */ 278 279 #endif /* CPU_COMMON_H */ 280