1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 1 3 4 /* CPU interfaces that are target independent. */ 5 6 #ifndef CONFIG_USER_ONLY 7 #include "exec/hwaddr.h" 8 #endif 9 10 #include "qemu/bswap.h" 11 #include "qemu/queue.h" 12 #include "qemu/fprintf-fn.h" 13 14 /** 15 * CPUListState: 16 * @cpu_fprintf: Print function. 17 * @file: File to print to using @cpu_fprint. 18 * 19 * State commonly used for iterating over CPU models. 20 */ 21 typedef struct CPUListState { 22 fprintf_function cpu_fprintf; 23 FILE *file; 24 } CPUListState; 25 26 #if !defined(CONFIG_USER_ONLY) 27 28 enum device_endian { 29 DEVICE_NATIVE_ENDIAN, 30 DEVICE_BIG_ENDIAN, 31 DEVICE_LITTLE_ENDIAN, 32 }; 33 34 /* address in the RAM (different from a physical address) */ 35 #if defined(CONFIG_XEN_BACKEND) 36 typedef uint64_t ram_addr_t; 37 # define RAM_ADDR_MAX UINT64_MAX 38 # define RAM_ADDR_FMT "%" PRIx64 39 #else 40 typedef uintptr_t ram_addr_t; 41 # define RAM_ADDR_MAX UINTPTR_MAX 42 # define RAM_ADDR_FMT "%" PRIxPTR 43 #endif 44 45 extern ram_addr_t ram_size; 46 47 /* memory API */ 48 49 typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value); 50 typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); 51 52 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 53 /* This should not be used by devices. */ 54 ram_addr_t qemu_ram_addr_from_host(void *ptr); 55 RAMBlock *qemu_ram_block_by_name(const char *name); 56 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 57 ram_addr_t *offset); 58 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 59 void qemu_ram_unset_idstr(RAMBlock *block); 60 const char *qemu_ram_get_idstr(RAMBlock *rb); 61 62 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, 63 int len, int is_write); 64 static inline void cpu_physical_memory_read(hwaddr addr, 65 void *buf, int len) 66 { 67 cpu_physical_memory_rw(addr, buf, len, 0); 68 } 69 static inline void cpu_physical_memory_write(hwaddr addr, 70 const void *buf, int len) 71 { 72 cpu_physical_memory_rw(addr, (void *)buf, len, 1); 73 } 74 void *cpu_physical_memory_map(hwaddr addr, 75 hwaddr *plen, 76 int is_write); 77 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 78 int is_write, hwaddr access_len); 79 void cpu_register_map_client(QEMUBH *bh); 80 void cpu_unregister_map_client(QEMUBH *bh); 81 82 bool cpu_physical_memory_is_io(hwaddr phys_addr); 83 84 /* Coalesced MMIO regions are areas where write operations can be reordered. 85 * This usually implies that write operations are side-effect free. This allows 86 * batching which can make a major impact on performance when using 87 * virtualization. 88 */ 89 void qemu_flush_coalesced_mmio_buffer(void); 90 91 uint32_t ldub_phys(AddressSpace *as, hwaddr addr); 92 uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr); 93 uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr); 94 uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr); 95 uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr); 96 uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr); 97 uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr); 98 void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val); 99 void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val); 100 void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val); 101 void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val); 102 void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val); 103 void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val); 104 void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val); 105 106 void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, 107 const uint8_t *buf, int len); 108 void cpu_flush_icache_range(hwaddr start, int len); 109 110 extern struct MemoryRegion io_mem_rom; 111 extern struct MemoryRegion io_mem_notdirty; 112 113 typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr, 114 ram_addr_t offset, ram_addr_t length, void *opaque); 115 116 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 117 118 #endif 119 120 #endif /* !CPU_COMMON_H */ 121