1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 3 4 /* CPU interfaces that are target independent. */ 5 6 #ifndef CONFIG_USER_ONLY 7 #include "exec/hwaddr.h" 8 #endif 9 10 /** 11 * vaddr: 12 * Type wide enough to contain any #target_ulong virtual address. 13 */ 14 typedef uint64_t vaddr; 15 #define VADDR_PRId PRId64 16 #define VADDR_PRIu PRIu64 17 #define VADDR_PRIo PRIo64 18 #define VADDR_PRIx PRIx64 19 #define VADDR_PRIX PRIX64 20 #define VADDR_MAX UINT64_MAX 21 22 void cpu_exec_init_all(void); 23 void cpu_exec_step_atomic(CPUState *cpu); 24 25 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 26 * when intptr_t is 32-bit and we are aligning a long long. 27 */ 28 extern uintptr_t qemu_host_page_size; 29 extern intptr_t qemu_host_page_mask; 30 31 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) 32 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size()) 33 34 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 35 extern QemuMutex qemu_cpu_list_lock; 36 void qemu_init_cpu_list(void); 37 void cpu_list_lock(void); 38 void cpu_list_unlock(void); 39 unsigned int cpu_list_generation_id_get(void); 40 41 void tcg_flush_softmmu_tlb(CPUState *cs); 42 void tcg_flush_jmp_cache(CPUState *cs); 43 44 void tcg_iommu_init_notifier_list(CPUState *cpu); 45 void tcg_iommu_free_notifier_list(CPUState *cpu); 46 47 #if !defined(CONFIG_USER_ONLY) 48 49 enum device_endian { 50 DEVICE_NATIVE_ENDIAN, 51 DEVICE_BIG_ENDIAN, 52 DEVICE_LITTLE_ENDIAN, 53 }; 54 55 #if HOST_BIG_ENDIAN 56 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 57 #else 58 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 59 #endif 60 61 /* address in the RAM (different from a physical address) */ 62 #if defined(CONFIG_XEN_BACKEND) 63 typedef uint64_t ram_addr_t; 64 # define RAM_ADDR_MAX UINT64_MAX 65 # define RAM_ADDR_FMT "%" PRIx64 66 #else 67 typedef uintptr_t ram_addr_t; 68 # define RAM_ADDR_MAX UINTPTR_MAX 69 # define RAM_ADDR_FMT "%" PRIxPTR 70 #endif 71 72 /* memory API */ 73 74 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 75 /* This should not be used by devices. */ 76 ram_addr_t qemu_ram_addr_from_host(void *ptr); 77 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 78 RAMBlock *qemu_ram_block_by_name(const char *name); 79 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 80 ram_addr_t *offset); 81 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 82 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 83 void qemu_ram_unset_idstr(RAMBlock *block); 84 const char *qemu_ram_get_idstr(RAMBlock *rb); 85 void *qemu_ram_get_host_addr(RAMBlock *rb); 86 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 87 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 88 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 89 bool qemu_ram_is_shared(RAMBlock *rb); 90 bool qemu_ram_is_noreserve(RAMBlock *rb); 91 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 92 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 93 bool qemu_ram_is_migratable(RAMBlock *rb); 94 void qemu_ram_set_migratable(RAMBlock *rb); 95 void qemu_ram_unset_migratable(RAMBlock *rb); 96 bool qemu_ram_is_named_file(RAMBlock *rb); 97 int qemu_ram_get_fd(RAMBlock *rb); 98 99 size_t qemu_ram_pagesize(RAMBlock *block); 100 size_t qemu_ram_pagesize_largest(void); 101 102 /** 103 * cpu_address_space_init: 104 * @cpu: CPU to add this address space to 105 * @asidx: integer index of this address space 106 * @prefix: prefix to be used as name of address space 107 * @mr: the root memory region of address space 108 * 109 * Add the specified address space to the CPU's cpu_ases list. 110 * The address space added with @asidx 0 is the one used for the 111 * convenience pointer cpu->as. 112 * The target-specific code which registers ASes is responsible 113 * for defining what semantics address space 0, 1, 2, etc have. 114 * 115 * Before the first call to this function, the caller must set 116 * cpu->num_ases to the total number of address spaces it needs 117 * to support. 118 * 119 * Note that with KVM only one address space is supported. 120 */ 121 void cpu_address_space_init(CPUState *cpu, int asidx, 122 const char *prefix, MemoryRegion *mr); 123 124 void cpu_physical_memory_rw(hwaddr addr, void *buf, 125 hwaddr len, bool is_write); 126 static inline void cpu_physical_memory_read(hwaddr addr, 127 void *buf, hwaddr len) 128 { 129 cpu_physical_memory_rw(addr, buf, len, false); 130 } 131 static inline void cpu_physical_memory_write(hwaddr addr, 132 const void *buf, hwaddr len) 133 { 134 cpu_physical_memory_rw(addr, (void *)buf, len, true); 135 } 136 void *cpu_physical_memory_map(hwaddr addr, 137 hwaddr *plen, 138 bool is_write); 139 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 140 bool is_write, hwaddr access_len); 141 void cpu_register_map_client(QEMUBH *bh); 142 void cpu_unregister_map_client(QEMUBH *bh); 143 144 bool cpu_physical_memory_is_io(hwaddr phys_addr); 145 146 /* Coalesced MMIO regions are areas where write operations can be reordered. 147 * This usually implies that write operations are side-effect free. This allows 148 * batching which can make a major impact on performance when using 149 * virtualization. 150 */ 151 void qemu_flush_coalesced_mmio_buffer(void); 152 153 void cpu_flush_icache_range(hwaddr start, hwaddr len); 154 155 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 156 157 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 158 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 159 160 #endif 161 162 /* Returns: 0 on success, -1 on error */ 163 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 164 void *ptr, size_t len, bool is_write); 165 166 /* vl.c */ 167 void list_cpus(void); 168 169 #endif /* CPU_COMMON_H */ 170