1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "qemu-common.h" 23 #include "exec/cpu-common.h" 24 #include "exec/memory.h" 25 #include "qemu/thread.h" 26 #include "qom/cpu.h" 27 #include "qemu/rcu.h" 28 29 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 30 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 31 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 32 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 33 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 34 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 35 36 /* some important defines: 37 * 38 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and 39 * otherwise little endian. 40 * 41 * TARGET_WORDS_BIGENDIAN : same for target cpu 42 */ 43 44 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) 45 #define BSWAP_NEEDED 46 #endif 47 48 #ifdef BSWAP_NEEDED 49 50 static inline uint16_t tswap16(uint16_t s) 51 { 52 return bswap16(s); 53 } 54 55 static inline uint32_t tswap32(uint32_t s) 56 { 57 return bswap32(s); 58 } 59 60 static inline uint64_t tswap64(uint64_t s) 61 { 62 return bswap64(s); 63 } 64 65 static inline void tswap16s(uint16_t *s) 66 { 67 *s = bswap16(*s); 68 } 69 70 static inline void tswap32s(uint32_t *s) 71 { 72 *s = bswap32(*s); 73 } 74 75 static inline void tswap64s(uint64_t *s) 76 { 77 *s = bswap64(*s); 78 } 79 80 #else 81 82 static inline uint16_t tswap16(uint16_t s) 83 { 84 return s; 85 } 86 87 static inline uint32_t tswap32(uint32_t s) 88 { 89 return s; 90 } 91 92 static inline uint64_t tswap64(uint64_t s) 93 { 94 return s; 95 } 96 97 static inline void tswap16s(uint16_t *s) 98 { 99 } 100 101 static inline void tswap32s(uint32_t *s) 102 { 103 } 104 105 static inline void tswap64s(uint64_t *s) 106 { 107 } 108 109 #endif 110 111 #if TARGET_LONG_SIZE == 4 112 #define tswapl(s) tswap32(s) 113 #define tswapls(s) tswap32s((uint32_t *)(s)) 114 #define bswaptls(s) bswap32s(s) 115 #else 116 #define tswapl(s) tswap64(s) 117 #define tswapls(s) tswap64s((uint64_t *)(s)) 118 #define bswaptls(s) bswap64s(s) 119 #endif 120 121 /* Target-endianness CPU memory access functions. These fit into the 122 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. 123 */ 124 #if defined(TARGET_WORDS_BIGENDIAN) 125 #define lduw_p(p) lduw_be_p(p) 126 #define ldsw_p(p) ldsw_be_p(p) 127 #define ldl_p(p) ldl_be_p(p) 128 #define ldq_p(p) ldq_be_p(p) 129 #define ldfl_p(p) ldfl_be_p(p) 130 #define ldfq_p(p) ldfq_be_p(p) 131 #define stw_p(p, v) stw_be_p(p, v) 132 #define stl_p(p, v) stl_be_p(p, v) 133 #define stq_p(p, v) stq_be_p(p, v) 134 #define stfl_p(p, v) stfl_be_p(p, v) 135 #define stfq_p(p, v) stfq_be_p(p, v) 136 #else 137 #define lduw_p(p) lduw_le_p(p) 138 #define ldsw_p(p) ldsw_le_p(p) 139 #define ldl_p(p) ldl_le_p(p) 140 #define ldq_p(p) ldq_le_p(p) 141 #define ldfl_p(p) ldfl_le_p(p) 142 #define ldfq_p(p) ldfq_le_p(p) 143 #define stw_p(p, v) stw_le_p(p, v) 144 #define stl_p(p, v) stl_le_p(p, v) 145 #define stq_p(p, v) stq_le_p(p, v) 146 #define stfl_p(p, v) stfl_le_p(p, v) 147 #define stfq_p(p, v) stfq_le_p(p, v) 148 #endif 149 150 /* MMU memory access macros */ 151 152 #if defined(CONFIG_USER_ONLY) 153 #include "exec/user/abitypes.h" 154 155 /* On some host systems the guest address space is reserved on the host. 156 * This allows the guest address space to be offset to a convenient location. 157 */ 158 extern unsigned long guest_base; 159 extern int have_guest_base; 160 extern unsigned long reserved_va; 161 162 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS 163 #define GUEST_ADDR_MAX (~0ul) 164 #else 165 #define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : \ 166 (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1) 167 #endif 168 #else 169 170 #include "exec/hwaddr.h" 171 172 #define SUFFIX 173 #define ARG1 as 174 #define ARG1_DECL AddressSpace *as 175 #define TARGET_ENDIANNESS 176 #include "exec/memory_ldst.inc.h" 177 178 #define SUFFIX _cached_slow 179 #define ARG1 cache 180 #define ARG1_DECL MemoryRegionCache *cache 181 #define TARGET_ENDIANNESS 182 #include "exec/memory_ldst.inc.h" 183 184 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) 185 { 186 address_space_stl_notdirty(as, addr, val, 187 MEMTXATTRS_UNSPECIFIED, NULL); 188 } 189 190 #define SUFFIX 191 #define ARG1 as 192 #define ARG1_DECL AddressSpace *as 193 #define TARGET_ENDIANNESS 194 #include "exec/memory_ldst_phys.inc.h" 195 196 /* Inline fast path for direct RAM access. */ 197 #define ENDIANNESS 198 #include "exec/memory_ldst_cached.inc.h" 199 200 #define SUFFIX _cached 201 #define ARG1 cache 202 #define ARG1_DECL MemoryRegionCache *cache 203 #define TARGET_ENDIANNESS 204 #include "exec/memory_ldst_phys.inc.h" 205 #endif 206 207 /* page related stuff */ 208 209 #ifdef TARGET_PAGE_BITS_VARY 210 extern bool target_page_bits_decided; 211 extern int target_page_bits; 212 #define TARGET_PAGE_BITS ({ assert(target_page_bits_decided); \ 213 target_page_bits; }) 214 #else 215 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS 216 #endif 217 218 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 219 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) 220 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) 221 222 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 223 * when intptr_t is 32-bit and we are aligning a long long. 224 */ 225 extern uintptr_t qemu_host_page_size; 226 extern intptr_t qemu_host_page_mask; 227 228 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) 229 #define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \ 230 qemu_real_host_page_mask) 231 232 /* same as PROT_xxx */ 233 #define PAGE_READ 0x0001 234 #define PAGE_WRITE 0x0002 235 #define PAGE_EXEC 0x0004 236 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 237 #define PAGE_VALID 0x0008 238 /* original state of the write flag (used when tracking self-modifying 239 code */ 240 #define PAGE_WRITE_ORG 0x0010 241 /* Invalidate the TLB entry immediately, helpful for s390x 242 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ 243 #define PAGE_WRITE_INV 0x0040 244 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 245 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 246 #define PAGE_RESERVED 0x0020 247 #endif 248 249 #if defined(CONFIG_USER_ONLY) 250 void page_dump(FILE *f); 251 252 typedef int (*walk_memory_regions_fn)(void *, target_ulong, 253 target_ulong, unsigned long); 254 int walk_memory_regions(void *, walk_memory_regions_fn); 255 256 int page_get_flags(target_ulong address); 257 void page_set_flags(target_ulong start, target_ulong end, int flags); 258 int page_check_range(target_ulong start, target_ulong len, int flags); 259 #endif 260 261 CPUArchState *cpu_copy(CPUArchState *env); 262 263 /* Flags for use in ENV->INTERRUPT_PENDING. 264 265 The numbers assigned here are non-sequential in order to preserve 266 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 267 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 268 the vmstate dump. */ 269 270 /* External hardware interrupt pending. This is typically used for 271 interrupts from devices. */ 272 #define CPU_INTERRUPT_HARD 0x0002 273 274 /* Exit the current TB. This is typically used when some system-level device 275 makes some change to the memory mapping. E.g. the a20 line change. */ 276 #define CPU_INTERRUPT_EXITTB 0x0004 277 278 /* Halt the CPU. */ 279 #define CPU_INTERRUPT_HALT 0x0020 280 281 /* Debug event pending. */ 282 #define CPU_INTERRUPT_DEBUG 0x0080 283 284 /* Reset signal. */ 285 #define CPU_INTERRUPT_RESET 0x0400 286 287 /* Several target-specific external hardware interrupts. Each target/cpu.h 288 should define proper names based on these defines. */ 289 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 290 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 291 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 292 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 293 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 294 295 /* Several target-specific internal interrupts. These differ from the 296 preceding target-specific interrupts in that they are intended to 297 originate from within the cpu itself, typically in response to some 298 instruction being executed. These, therefore, are not masked while 299 single-stepping within the debugger. */ 300 #define CPU_INTERRUPT_TGT_INT_0 0x0100 301 #define CPU_INTERRUPT_TGT_INT_1 0x0800 302 #define CPU_INTERRUPT_TGT_INT_2 0x2000 303 304 /* First unused bit: 0x4000. */ 305 306 /* The set of all bits that should be masked when single-stepping. */ 307 #define CPU_INTERRUPT_SSTEP_MASK \ 308 (CPU_INTERRUPT_HARD \ 309 | CPU_INTERRUPT_TGT_EXT_0 \ 310 | CPU_INTERRUPT_TGT_EXT_1 \ 311 | CPU_INTERRUPT_TGT_EXT_2 \ 312 | CPU_INTERRUPT_TGT_EXT_3 \ 313 | CPU_INTERRUPT_TGT_EXT_4) 314 315 #if !defined(CONFIG_USER_ONLY) 316 317 /* Flags stored in the low bits of the TLB virtual address. These are 318 * defined so that fast path ram access is all zeros. 319 * The flags all must be between TARGET_PAGE_BITS and 320 * maximum address alignment bit. 321 */ 322 /* Zero if TLB entry is valid. */ 323 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS - 1)) 324 /* Set if TLB entry references a clean RAM page. The iotlb entry will 325 contain the page physical address. */ 326 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) 327 /* Set if TLB entry is an IO callback. */ 328 #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) 329 330 /* Use this mask to check interception with an alignment mask 331 * in a TCG backend. 332 */ 333 #define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO) 334 335 void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); 336 void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf); 337 #endif /* !CONFIG_USER_ONLY */ 338 339 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 340 uint8_t *buf, int len, int is_write); 341 342 int cpu_exec(CPUState *cpu); 343 344 #endif /* CPU_ALL_H */ 345