1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "exec/cpu-common.h" 23 #include "exec/memory.h" 24 #include "exec/tswap.h" 25 #include "qemu/thread.h" 26 #include "hw/core/cpu.h" 27 #include "qemu/rcu.h" 28 29 /* some important defines: 30 * 31 * HOST_BIG_ENDIAN : whether the host cpu is big endian and 32 * otherwise little endian. 33 * 34 * TARGET_BIG_ENDIAN : same for the target cpu 35 */ 36 37 #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN 38 #define BSWAP_NEEDED 39 #endif 40 41 #if TARGET_LONG_SIZE == 4 42 #define tswapl(s) tswap32(s) 43 #define tswapls(s) tswap32s((uint32_t *)(s)) 44 #define bswaptls(s) bswap32s(s) 45 #else 46 #define tswapl(s) tswap64(s) 47 #define tswapls(s) tswap64s((uint64_t *)(s)) 48 #define bswaptls(s) bswap64s(s) 49 #endif 50 51 /* Target-endianness CPU memory access functions. These fit into the 52 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. 53 */ 54 #if TARGET_BIG_ENDIAN 55 #define lduw_p(p) lduw_be_p(p) 56 #define ldsw_p(p) ldsw_be_p(p) 57 #define ldl_p(p) ldl_be_p(p) 58 #define ldq_p(p) ldq_be_p(p) 59 #define stw_p(p, v) stw_be_p(p, v) 60 #define stl_p(p, v) stl_be_p(p, v) 61 #define stq_p(p, v) stq_be_p(p, v) 62 #define ldn_p(p, sz) ldn_be_p(p, sz) 63 #define stn_p(p, sz, v) stn_be_p(p, sz, v) 64 #else 65 #define lduw_p(p) lduw_le_p(p) 66 #define ldsw_p(p) ldsw_le_p(p) 67 #define ldl_p(p) ldl_le_p(p) 68 #define ldq_p(p) ldq_le_p(p) 69 #define stw_p(p, v) stw_le_p(p, v) 70 #define stl_p(p, v) stl_le_p(p, v) 71 #define stq_p(p, v) stq_le_p(p, v) 72 #define ldn_p(p, sz) ldn_le_p(p, sz) 73 #define stn_p(p, sz, v) stn_le_p(p, sz, v) 74 #endif 75 76 /* MMU memory access macros */ 77 78 #if defined(CONFIG_USER_ONLY) 79 #include "exec/user/abitypes.h" 80 #include "exec/user/guest-base.h" 81 82 extern bool have_guest_base; 83 84 /* 85 * If non-zero, the guest virtual address space is a contiguous subset 86 * of the host virtual address space, i.e. '-R reserved_va' is in effect 87 * either from the command-line or by default. The value is the last 88 * byte of the guest address space e.g. UINT32_MAX. 89 * 90 * If zero, the host and guest virtual address spaces are intermingled. 91 */ 92 extern unsigned long reserved_va; 93 94 /* 95 * Limit the guest addresses as best we can. 96 * 97 * When not using -R reserved_va, we cannot really limit the guest 98 * to less address space than the host. For 32-bit guests, this 99 * acts as a sanity check that we're not giving the guest an address 100 * that it cannot even represent. For 64-bit guests... the address 101 * might not be what the real kernel would give, but it is at least 102 * representable in the guest. 103 * 104 * TODO: Improve address allocation to avoid this problem, and to 105 * avoid setting bits at the top of guest addresses that might need 106 * to be used for tags. 107 */ 108 #define GUEST_ADDR_MAX_ \ 109 ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \ 110 UINT32_MAX : ~0ul) 111 #define GUEST_ADDR_MAX (reserved_va ? : GUEST_ADDR_MAX_) 112 113 #else 114 115 #include "exec/hwaddr.h" 116 117 #define SUFFIX 118 #define ARG1 as 119 #define ARG1_DECL AddressSpace *as 120 #define TARGET_ENDIANNESS 121 #include "exec/memory_ldst.h.inc" 122 123 #define SUFFIX _cached_slow 124 #define ARG1 cache 125 #define ARG1_DECL MemoryRegionCache *cache 126 #define TARGET_ENDIANNESS 127 #include "exec/memory_ldst.h.inc" 128 129 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) 130 { 131 address_space_stl_notdirty(as, addr, val, 132 MEMTXATTRS_UNSPECIFIED, NULL); 133 } 134 135 #define SUFFIX 136 #define ARG1 as 137 #define ARG1_DECL AddressSpace *as 138 #define TARGET_ENDIANNESS 139 #include "exec/memory_ldst_phys.h.inc" 140 141 /* Inline fast path for direct RAM access. */ 142 #define ENDIANNESS 143 #include "exec/memory_ldst_cached.h.inc" 144 145 #define SUFFIX _cached 146 #define ARG1 cache 147 #define ARG1_DECL MemoryRegionCache *cache 148 #define TARGET_ENDIANNESS 149 #include "exec/memory_ldst_phys.h.inc" 150 #endif 151 152 /* page related stuff */ 153 154 #ifdef TARGET_PAGE_BITS_VARY 155 # include "exec/page-vary.h" 156 extern const TargetPageBits target_page; 157 #ifdef CONFIG_DEBUG_TCG 158 #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; }) 159 #define TARGET_PAGE_MASK ({ assert(target_page.decided); \ 160 (target_long)target_page.mask; }) 161 #else 162 #define TARGET_PAGE_BITS target_page.bits 163 #define TARGET_PAGE_MASK ((target_long)target_page.mask) 164 #endif 165 #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) 166 #else 167 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS 168 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 169 #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) 170 #endif 171 172 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) 173 174 /* same as PROT_xxx */ 175 #define PAGE_READ 0x0001 176 #define PAGE_WRITE 0x0002 177 #define PAGE_EXEC 0x0004 178 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 179 #define PAGE_VALID 0x0008 180 /* 181 * Original state of the write flag (used when tracking self-modifying code) 182 */ 183 #define PAGE_WRITE_ORG 0x0010 184 /* 185 * Invalidate the TLB entry immediately, helpful for s390x 186 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() 187 */ 188 #define PAGE_WRITE_INV 0x0020 189 /* For use with page_set_flags: page is being replaced; target_data cleared. */ 190 #define PAGE_RESET 0x0040 191 /* For linux-user, indicates that the page is MAP_ANON. */ 192 #define PAGE_ANON 0x0080 193 194 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 195 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 196 #define PAGE_RESERVED 0x0100 197 #endif 198 /* Target-specific bits that will be used via page_get_flags(). */ 199 #define PAGE_TARGET_1 0x0200 200 #define PAGE_TARGET_2 0x0400 201 202 /* 203 * For linux-user, indicates that the page is mapped with the same semantics 204 * in both guest and host. 205 */ 206 #define PAGE_PASSTHROUGH 0x0800 207 208 #if defined(CONFIG_USER_ONLY) 209 void page_dump(FILE *f); 210 211 typedef int (*walk_memory_regions_fn)(void *, target_ulong, 212 target_ulong, unsigned long); 213 int walk_memory_regions(void *, walk_memory_regions_fn); 214 215 int page_get_flags(target_ulong address); 216 void page_set_flags(target_ulong start, target_ulong last, int flags); 217 void page_reset_target_data(target_ulong start, target_ulong last); 218 219 /** 220 * page_check_range 221 * @start: first byte of range 222 * @len: length of range 223 * @flags: flags required for each page 224 * 225 * Return true if every page in [@start, @start+@len) has @flags set. 226 * Return false if any page is unmapped. Thus testing flags == 0 is 227 * equivalent to testing for flags == PAGE_VALID. 228 */ 229 bool page_check_range(target_ulong start, target_ulong last, int flags); 230 231 /** 232 * page_check_range_empty: 233 * @start: first byte of range 234 * @last: last byte of range 235 * Context: holding mmap lock 236 * 237 * Return true if the entire range [@start, @last] is unmapped. 238 * The memory lock must be held so that the caller will can ensure 239 * the result stays true until a new mapping can be installed. 240 */ 241 bool page_check_range_empty(target_ulong start, target_ulong last); 242 243 /** 244 * page_find_range_empty 245 * @min: first byte of search range 246 * @max: last byte of search range 247 * @len: size of the hole required 248 * @align: alignment of the hole required (power of 2) 249 * 250 * If there is a range [x, x+@len) within [@min, @max] such that 251 * x % @align == 0, then return x. Otherwise return -1. 252 * The memory lock must be held, as the caller will want to ensure 253 * the returned range stays empty until a new mapping can be installed. 254 */ 255 target_ulong page_find_range_empty(target_ulong min, target_ulong max, 256 target_ulong len, target_ulong align); 257 258 /** 259 * page_get_target_data(address) 260 * @address: guest virtual address 261 * 262 * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate 263 * with the guest page at @address, allocating it if necessary. The 264 * caller should already have verified that the address is valid. 265 * 266 * The memory will be freed when the guest page is deallocated, 267 * e.g. with the munmap system call. 268 */ 269 void *page_get_target_data(target_ulong address) 270 __attribute__((returns_nonnull)); 271 #endif 272 273 CPUArchState *cpu_copy(CPUArchState *env); 274 275 /* Flags for use in ENV->INTERRUPT_PENDING. 276 277 The numbers assigned here are non-sequential in order to preserve 278 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 279 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 280 the vmstate dump. */ 281 282 /* External hardware interrupt pending. This is typically used for 283 interrupts from devices. */ 284 #define CPU_INTERRUPT_HARD 0x0002 285 286 /* Exit the current TB. This is typically used when some system-level device 287 makes some change to the memory mapping. E.g. the a20 line change. */ 288 #define CPU_INTERRUPT_EXITTB 0x0004 289 290 /* Halt the CPU. */ 291 #define CPU_INTERRUPT_HALT 0x0020 292 293 /* Debug event pending. */ 294 #define CPU_INTERRUPT_DEBUG 0x0080 295 296 /* Reset signal. */ 297 #define CPU_INTERRUPT_RESET 0x0400 298 299 /* Several target-specific external hardware interrupts. Each target/cpu.h 300 should define proper names based on these defines. */ 301 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 302 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 303 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 304 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 305 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 306 307 /* Several target-specific internal interrupts. These differ from the 308 preceding target-specific interrupts in that they are intended to 309 originate from within the cpu itself, typically in response to some 310 instruction being executed. These, therefore, are not masked while 311 single-stepping within the debugger. */ 312 #define CPU_INTERRUPT_TGT_INT_0 0x0100 313 #define CPU_INTERRUPT_TGT_INT_1 0x0800 314 #define CPU_INTERRUPT_TGT_INT_2 0x2000 315 316 /* First unused bit: 0x4000. */ 317 318 /* The set of all bits that should be masked when single-stepping. */ 319 #define CPU_INTERRUPT_SSTEP_MASK \ 320 (CPU_INTERRUPT_HARD \ 321 | CPU_INTERRUPT_TGT_EXT_0 \ 322 | CPU_INTERRUPT_TGT_EXT_1 \ 323 | CPU_INTERRUPT_TGT_EXT_2 \ 324 | CPU_INTERRUPT_TGT_EXT_3 \ 325 | CPU_INTERRUPT_TGT_EXT_4) 326 327 #ifdef CONFIG_USER_ONLY 328 329 /* 330 * Allow some level of source compatibility with softmmu. We do not 331 * support any of the more exotic features, so only invalid pages may 332 * be signaled by probe_access_flags(). 333 */ 334 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 335 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) 336 #define TLB_WATCHPOINT 0 337 338 #else 339 340 /* 341 * Flags stored in the low bits of the TLB virtual address. 342 * These are defined so that fast path ram access is all zeros. 343 * The flags all must be between TARGET_PAGE_BITS and 344 * maximum address alignment bit. 345 * 346 * Use TARGET_PAGE_BITS_MIN so that these bits are constant 347 * when TARGET_PAGE_BITS_VARY is in effect. 348 * 349 * The count, if not the placement of these bits is known 350 * to tcg/tcg-op-ldst.c, check_max_alignment(). 351 */ 352 /* Zero if TLB entry is valid. */ 353 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 354 /* Set if TLB entry references a clean RAM page. The iotlb entry will 355 contain the page physical address. */ 356 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) 357 /* Set if TLB entry is an IO callback. */ 358 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) 359 /* Set if TLB entry writes ignored. */ 360 #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) 361 /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ 362 #define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) 363 364 /* 365 * Use this mask to check interception with an alignment mask 366 * in a TCG backend. 367 */ 368 #define TLB_FLAGS_MASK \ 369 (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ 370 | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) 371 372 /* 373 * Flags stored in CPUTLBEntryFull.slow_flags[x]. 374 * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. 375 */ 376 /* Set if TLB entry requires byte swap. */ 377 #define TLB_BSWAP (1 << 0) 378 /* Set if TLB entry contains a watchpoint. */ 379 #define TLB_WATCHPOINT (1 << 1) 380 381 #define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) 382 383 /* The two sets of flags must not overlap. */ 384 QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); 385 386 /** 387 * tlb_hit_page: return true if page aligned @addr is a hit against the 388 * TLB entry @tlb_addr 389 * 390 * @addr: virtual address to test (must be page aligned) 391 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 392 */ 393 static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) 394 { 395 return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); 396 } 397 398 /** 399 * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr 400 * 401 * @addr: virtual address to test (need not be page aligned) 402 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 403 */ 404 static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) 405 { 406 return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); 407 } 408 409 #endif /* !CONFIG_USER_ONLY */ 410 411 /* accel/tcg/cpu-exec.c */ 412 int cpu_exec(CPUState *cpu); 413 414 /* Validate correct placement of CPUArchState. */ 415 QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0); 416 QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState)); 417 418 /** 419 * env_archcpu(env) 420 * @env: The architecture environment 421 * 422 * Return the ArchCPU associated with the environment. 423 */ 424 static inline ArchCPU *env_archcpu(CPUArchState *env) 425 { 426 return (void *)env - sizeof(CPUState); 427 } 428 429 /** 430 * env_cpu(env) 431 * @env: The architecture environment 432 * 433 * Return the CPUState associated with the environment. 434 */ 435 static inline CPUState *env_cpu(CPUArchState *env) 436 { 437 return (void *)env - sizeof(CPUState); 438 } 439 440 #endif /* CPU_ALL_H */ 441