xref: /openbmc/qemu/include/exec/cpu-all.h (revision e9206163)
1 /*
2  * defines common to all virtual CPUs
3  *
4  *  Copyright (c) 2003 Fabrice Bellard
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 #ifndef CPU_ALL_H
20 #define CPU_ALL_H
21 
22 #include "exec/cpu-common.h"
23 #include "exec/memory.h"
24 #include "exec/tswap.h"
25 #include "qemu/thread.h"
26 #include "hw/core/cpu.h"
27 #include "qemu/rcu.h"
28 
29 /* some important defines:
30  *
31  * HOST_BIG_ENDIAN : whether the host cpu is big endian and
32  * otherwise little endian.
33  *
34  * TARGET_BIG_ENDIAN : same for the target cpu
35  */
36 
37 #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
38 #define BSWAP_NEEDED
39 #endif
40 
41 #if TARGET_LONG_SIZE == 4
42 #define tswapl(s) tswap32(s)
43 #define tswapls(s) tswap32s((uint32_t *)(s))
44 #define bswaptls(s) bswap32s(s)
45 #else
46 #define tswapl(s) tswap64(s)
47 #define tswapls(s) tswap64s((uint64_t *)(s))
48 #define bswaptls(s) bswap64s(s)
49 #endif
50 
51 /* Target-endianness CPU memory access functions. These fit into the
52  * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
53  */
54 #if TARGET_BIG_ENDIAN
55 #define lduw_p(p) lduw_be_p(p)
56 #define ldsw_p(p) ldsw_be_p(p)
57 #define ldl_p(p) ldl_be_p(p)
58 #define ldq_p(p) ldq_be_p(p)
59 #define stw_p(p, v) stw_be_p(p, v)
60 #define stl_p(p, v) stl_be_p(p, v)
61 #define stq_p(p, v) stq_be_p(p, v)
62 #define ldn_p(p, sz) ldn_be_p(p, sz)
63 #define stn_p(p, sz, v) stn_be_p(p, sz, v)
64 #else
65 #define lduw_p(p) lduw_le_p(p)
66 #define ldsw_p(p) ldsw_le_p(p)
67 #define ldl_p(p) ldl_le_p(p)
68 #define ldq_p(p) ldq_le_p(p)
69 #define stw_p(p, v) stw_le_p(p, v)
70 #define stl_p(p, v) stl_le_p(p, v)
71 #define stq_p(p, v) stq_le_p(p, v)
72 #define ldn_p(p, sz) ldn_le_p(p, sz)
73 #define stn_p(p, sz, v) stn_le_p(p, sz, v)
74 #endif
75 
76 /* MMU memory access macros */
77 
78 #if defined(CONFIG_USER_ONLY)
79 #include "exec/user/abitypes.h"
80 #include "exec/user/guest-base.h"
81 
82 extern bool have_guest_base;
83 
84 /*
85  * If non-zero, the guest virtual address space is a contiguous subset
86  * of the host virtual address space, i.e. '-R reserved_va' is in effect
87  * either from the command-line or by default.  The value is the last
88  * byte of the guest address space e.g. UINT32_MAX.
89  *
90  * If zero, the host and guest virtual address spaces are intermingled.
91  */
92 extern unsigned long reserved_va;
93 
94 /*
95  * Limit the guest addresses as best we can.
96  *
97  * When not using -R reserved_va, we cannot really limit the guest
98  * to less address space than the host.  For 32-bit guests, this
99  * acts as a sanity check that we're not giving the guest an address
100  * that it cannot even represent.  For 64-bit guests... the address
101  * might not be what the real kernel would give, but it is at least
102  * representable in the guest.
103  *
104  * TODO: Improve address allocation to avoid this problem, and to
105  * avoid setting bits at the top of guest addresses that might need
106  * to be used for tags.
107  */
108 #define GUEST_ADDR_MAX_                                                 \
109     ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ?  \
110      UINT32_MAX : ~0ul)
111 #define GUEST_ADDR_MAX    (reserved_va ? : GUEST_ADDR_MAX_)
112 
113 #else
114 
115 #include "exec/hwaddr.h"
116 
117 #define SUFFIX
118 #define ARG1         as
119 #define ARG1_DECL    AddressSpace *as
120 #define TARGET_ENDIANNESS
121 #include "exec/memory_ldst.h.inc"
122 
123 #define SUFFIX       _cached_slow
124 #define ARG1         cache
125 #define ARG1_DECL    MemoryRegionCache *cache
126 #define TARGET_ENDIANNESS
127 #include "exec/memory_ldst.h.inc"
128 
129 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
130 {
131     address_space_stl_notdirty(as, addr, val,
132                                MEMTXATTRS_UNSPECIFIED, NULL);
133 }
134 
135 #define SUFFIX
136 #define ARG1         as
137 #define ARG1_DECL    AddressSpace *as
138 #define TARGET_ENDIANNESS
139 #include "exec/memory_ldst_phys.h.inc"
140 
141 /* Inline fast path for direct RAM access.  */
142 #define ENDIANNESS
143 #include "exec/memory_ldst_cached.h.inc"
144 
145 #define SUFFIX       _cached
146 #define ARG1         cache
147 #define ARG1_DECL    MemoryRegionCache *cache
148 #define TARGET_ENDIANNESS
149 #include "exec/memory_ldst_phys.h.inc"
150 #endif
151 
152 /* page related stuff */
153 
154 #ifdef TARGET_PAGE_BITS_VARY
155 # include "exec/page-vary.h"
156 extern const TargetPageBits target_page;
157 #ifdef CONFIG_DEBUG_TCG
158 #define TARGET_PAGE_BITS   ({ assert(target_page.decided); target_page.bits; })
159 #define TARGET_PAGE_MASK   ({ assert(target_page.decided); \
160                               (target_long)target_page.mask; })
161 #else
162 #define TARGET_PAGE_BITS   target_page.bits
163 #define TARGET_PAGE_MASK   ((target_long)target_page.mask)
164 #endif
165 #define TARGET_PAGE_SIZE   (-(int)TARGET_PAGE_MASK)
166 #else
167 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
168 #define TARGET_PAGE_SIZE   (1 << TARGET_PAGE_BITS)
169 #define TARGET_PAGE_MASK   ((target_long)-1 << TARGET_PAGE_BITS)
170 #endif
171 
172 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
173 
174 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
175 /* FIXME: Code that sets/uses this is broken and needs to go away.  */
176 #define PAGE_RESERVED  0x0100
177 #endif
178 /*
179  * For linux-user, indicates that the page is mapped with the same semantics
180  * in both guest and host.
181  */
182 #define PAGE_PASSTHROUGH 0x0800
183 
184 #if defined(CONFIG_USER_ONLY)
185 void page_dump(FILE *f);
186 
187 typedef int (*walk_memory_regions_fn)(void *, target_ulong,
188                                       target_ulong, unsigned long);
189 int walk_memory_regions(void *, walk_memory_regions_fn);
190 
191 int page_get_flags(target_ulong address);
192 void page_set_flags(target_ulong start, target_ulong last, int flags);
193 void page_reset_target_data(target_ulong start, target_ulong last);
194 
195 /**
196  * page_check_range
197  * @start: first byte of range
198  * @len: length of range
199  * @flags: flags required for each page
200  *
201  * Return true if every page in [@start, @start+@len) has @flags set.
202  * Return false if any page is unmapped.  Thus testing flags == 0 is
203  * equivalent to testing for flags == PAGE_VALID.
204  */
205 bool page_check_range(target_ulong start, target_ulong last, int flags);
206 
207 /**
208  * page_check_range_empty:
209  * @start: first byte of range
210  * @last: last byte of range
211  * Context: holding mmap lock
212  *
213  * Return true if the entire range [@start, @last] is unmapped.
214  * The memory lock must be held so that the caller will can ensure
215  * the result stays true until a new mapping can be installed.
216  */
217 bool page_check_range_empty(target_ulong start, target_ulong last);
218 
219 /**
220  * page_find_range_empty
221  * @min: first byte of search range
222  * @max: last byte of search range
223  * @len: size of the hole required
224  * @align: alignment of the hole required (power of 2)
225  *
226  * If there is a range [x, x+@len) within [@min, @max] such that
227  * x % @align == 0, then return x.  Otherwise return -1.
228  * The memory lock must be held, as the caller will want to ensure
229  * the returned range stays empty until a new mapping can be installed.
230  */
231 target_ulong page_find_range_empty(target_ulong min, target_ulong max,
232                                    target_ulong len, target_ulong align);
233 
234 /**
235  * page_get_target_data(address)
236  * @address: guest virtual address
237  *
238  * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate
239  * with the guest page at @address, allocating it if necessary.  The
240  * caller should already have verified that the address is valid.
241  *
242  * The memory will be freed when the guest page is deallocated,
243  * e.g. with the munmap system call.
244  */
245 void *page_get_target_data(target_ulong address)
246     __attribute__((returns_nonnull));
247 #endif
248 
249 CPUArchState *cpu_copy(CPUArchState *env);
250 
251 /* Flags for use in ENV->INTERRUPT_PENDING.
252 
253    The numbers assigned here are non-sequential in order to preserve
254    binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
255    previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
256    the vmstate dump.  */
257 
258 /* External hardware interrupt pending.  This is typically used for
259    interrupts from devices.  */
260 #define CPU_INTERRUPT_HARD        0x0002
261 
262 /* Exit the current TB.  This is typically used when some system-level device
263    makes some change to the memory mapping.  E.g. the a20 line change.  */
264 #define CPU_INTERRUPT_EXITTB      0x0004
265 
266 /* Halt the CPU.  */
267 #define CPU_INTERRUPT_HALT        0x0020
268 
269 /* Debug event pending.  */
270 #define CPU_INTERRUPT_DEBUG       0x0080
271 
272 /* Reset signal.  */
273 #define CPU_INTERRUPT_RESET       0x0400
274 
275 /* Several target-specific external hardware interrupts.  Each target/cpu.h
276    should define proper names based on these defines.  */
277 #define CPU_INTERRUPT_TGT_EXT_0   0x0008
278 #define CPU_INTERRUPT_TGT_EXT_1   0x0010
279 #define CPU_INTERRUPT_TGT_EXT_2   0x0040
280 #define CPU_INTERRUPT_TGT_EXT_3   0x0200
281 #define CPU_INTERRUPT_TGT_EXT_4   0x1000
282 
283 /* Several target-specific internal interrupts.  These differ from the
284    preceding target-specific interrupts in that they are intended to
285    originate from within the cpu itself, typically in response to some
286    instruction being executed.  These, therefore, are not masked while
287    single-stepping within the debugger.  */
288 #define CPU_INTERRUPT_TGT_INT_0   0x0100
289 #define CPU_INTERRUPT_TGT_INT_1   0x0800
290 #define CPU_INTERRUPT_TGT_INT_2   0x2000
291 
292 /* First unused bit: 0x4000.  */
293 
294 /* The set of all bits that should be masked when single-stepping.  */
295 #define CPU_INTERRUPT_SSTEP_MASK \
296     (CPU_INTERRUPT_HARD          \
297      | CPU_INTERRUPT_TGT_EXT_0   \
298      | CPU_INTERRUPT_TGT_EXT_1   \
299      | CPU_INTERRUPT_TGT_EXT_2   \
300      | CPU_INTERRUPT_TGT_EXT_3   \
301      | CPU_INTERRUPT_TGT_EXT_4)
302 
303 #ifdef CONFIG_USER_ONLY
304 
305 /*
306  * Allow some level of source compatibility with softmmu.  We do not
307  * support any of the more exotic features, so only invalid pages may
308  * be signaled by probe_access_flags().
309  */
310 #define TLB_INVALID_MASK    (1 << (TARGET_PAGE_BITS_MIN - 1))
311 #define TLB_MMIO            (1 << (TARGET_PAGE_BITS_MIN - 2))
312 #define TLB_WATCHPOINT      0
313 
314 static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
315 {
316     return MMU_USER_IDX;
317 }
318 #else
319 
320 /*
321  * Flags stored in the low bits of the TLB virtual address.
322  * These are defined so that fast path ram access is all zeros.
323  * The flags all must be between TARGET_PAGE_BITS and
324  * maximum address alignment bit.
325  *
326  * Use TARGET_PAGE_BITS_MIN so that these bits are constant
327  * when TARGET_PAGE_BITS_VARY is in effect.
328  *
329  * The count, if not the placement of these bits is known
330  * to tcg/tcg-op-ldst.c, check_max_alignment().
331  */
332 /* Zero if TLB entry is valid.  */
333 #define TLB_INVALID_MASK    (1 << (TARGET_PAGE_BITS_MIN - 1))
334 /* Set if TLB entry references a clean RAM page.  The iotlb entry will
335    contain the page physical address.  */
336 #define TLB_NOTDIRTY        (1 << (TARGET_PAGE_BITS_MIN - 2))
337 /* Set if TLB entry is an IO callback.  */
338 #define TLB_MMIO            (1 << (TARGET_PAGE_BITS_MIN - 3))
339 /* Set if TLB entry writes ignored.  */
340 #define TLB_DISCARD_WRITE   (1 << (TARGET_PAGE_BITS_MIN - 4))
341 /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
342 #define TLB_FORCE_SLOW      (1 << (TARGET_PAGE_BITS_MIN - 5))
343 
344 /*
345  * Use this mask to check interception with an alignment mask
346  * in a TCG backend.
347  */
348 #define TLB_FLAGS_MASK \
349     (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
350     | TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
351 
352 /*
353  * Flags stored in CPUTLBEntryFull.slow_flags[x].
354  * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
355  */
356 /* Set if TLB entry requires byte swap.  */
357 #define TLB_BSWAP            (1 << 0)
358 /* Set if TLB entry contains a watchpoint.  */
359 #define TLB_WATCHPOINT       (1 << 1)
360 
361 #define TLB_SLOW_FLAGS_MASK  (TLB_BSWAP | TLB_WATCHPOINT)
362 
363 /* The two sets of flags must not overlap. */
364 QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
365 
366 /**
367  * tlb_hit_page: return true if page aligned @addr is a hit against the
368  * TLB entry @tlb_addr
369  *
370  * @addr: virtual address to test (must be page aligned)
371  * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
372  */
373 static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
374 {
375     return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
376 }
377 
378 /**
379  * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
380  *
381  * @addr: virtual address to test (need not be page aligned)
382  * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
383  */
384 static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
385 {
386     return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
387 }
388 
389 #endif /* !CONFIG_USER_ONLY */
390 
391 /* Validate correct placement of CPUArchState. */
392 QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
393 QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
394 
395 #endif /* CPU_ALL_H */
396