1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "exec/cpu-common.h" 23 #include "exec/memory.h" 24 #include "qemu/thread.h" 25 #include "hw/core/cpu.h" 26 #include "qemu/rcu.h" 27 28 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 29 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 30 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 31 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 32 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 33 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 34 35 /* some important defines: 36 * 37 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and 38 * otherwise little endian. 39 * 40 * TARGET_WORDS_BIGENDIAN : same for target cpu 41 */ 42 43 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) 44 #define BSWAP_NEEDED 45 #endif 46 47 #ifdef BSWAP_NEEDED 48 49 static inline uint16_t tswap16(uint16_t s) 50 { 51 return bswap16(s); 52 } 53 54 static inline uint32_t tswap32(uint32_t s) 55 { 56 return bswap32(s); 57 } 58 59 static inline uint64_t tswap64(uint64_t s) 60 { 61 return bswap64(s); 62 } 63 64 static inline void tswap16s(uint16_t *s) 65 { 66 *s = bswap16(*s); 67 } 68 69 static inline void tswap32s(uint32_t *s) 70 { 71 *s = bswap32(*s); 72 } 73 74 static inline void tswap64s(uint64_t *s) 75 { 76 *s = bswap64(*s); 77 } 78 79 #else 80 81 static inline uint16_t tswap16(uint16_t s) 82 { 83 return s; 84 } 85 86 static inline uint32_t tswap32(uint32_t s) 87 { 88 return s; 89 } 90 91 static inline uint64_t tswap64(uint64_t s) 92 { 93 return s; 94 } 95 96 static inline void tswap16s(uint16_t *s) 97 { 98 } 99 100 static inline void tswap32s(uint32_t *s) 101 { 102 } 103 104 static inline void tswap64s(uint64_t *s) 105 { 106 } 107 108 #endif 109 110 #if TARGET_LONG_SIZE == 4 111 #define tswapl(s) tswap32(s) 112 #define tswapls(s) tswap32s((uint32_t *)(s)) 113 #define bswaptls(s) bswap32s(s) 114 #else 115 #define tswapl(s) tswap64(s) 116 #define tswapls(s) tswap64s((uint64_t *)(s)) 117 #define bswaptls(s) bswap64s(s) 118 #endif 119 120 /* Target-endianness CPU memory access functions. These fit into the 121 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. 122 */ 123 #if defined(TARGET_WORDS_BIGENDIAN) 124 #define lduw_p(p) lduw_be_p(p) 125 #define ldsw_p(p) ldsw_be_p(p) 126 #define ldl_p(p) ldl_be_p(p) 127 #define ldq_p(p) ldq_be_p(p) 128 #define stw_p(p, v) stw_be_p(p, v) 129 #define stl_p(p, v) stl_be_p(p, v) 130 #define stq_p(p, v) stq_be_p(p, v) 131 #define ldn_p(p, sz) ldn_be_p(p, sz) 132 #define stn_p(p, sz, v) stn_be_p(p, sz, v) 133 #else 134 #define lduw_p(p) lduw_le_p(p) 135 #define ldsw_p(p) ldsw_le_p(p) 136 #define ldl_p(p) ldl_le_p(p) 137 #define ldq_p(p) ldq_le_p(p) 138 #define stw_p(p, v) stw_le_p(p, v) 139 #define stl_p(p, v) stl_le_p(p, v) 140 #define stq_p(p, v) stq_le_p(p, v) 141 #define ldn_p(p, sz) ldn_le_p(p, sz) 142 #define stn_p(p, sz, v) stn_le_p(p, sz, v) 143 #endif 144 145 /* MMU memory access macros */ 146 147 #if defined(CONFIG_USER_ONLY) 148 #include "exec/user/abitypes.h" 149 150 /* On some host systems the guest address space is reserved on the host. 151 * This allows the guest address space to be offset to a convenient location. 152 */ 153 extern uintptr_t guest_base; 154 extern bool have_guest_base; 155 extern unsigned long reserved_va; 156 157 /* 158 * Limit the guest addresses as best we can. 159 * 160 * When not using -R reserved_va, we cannot really limit the guest 161 * to less address space than the host. For 32-bit guests, this 162 * acts as a sanity check that we're not giving the guest an address 163 * that it cannot even represent. For 64-bit guests... the address 164 * might not be what the real kernel would give, but it is at least 165 * representable in the guest. 166 * 167 * TODO: Improve address allocation to avoid this problem, and to 168 * avoid setting bits at the top of guest addresses that might need 169 * to be used for tags. 170 */ 171 #define GUEST_ADDR_MAX_ \ 172 ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \ 173 UINT32_MAX : ~0ul) 174 #define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : GUEST_ADDR_MAX_) 175 176 #else 177 178 #include "exec/hwaddr.h" 179 180 #define SUFFIX 181 #define ARG1 as 182 #define ARG1_DECL AddressSpace *as 183 #define TARGET_ENDIANNESS 184 #include "exec/memory_ldst.h.inc" 185 186 #define SUFFIX _cached_slow 187 #define ARG1 cache 188 #define ARG1_DECL MemoryRegionCache *cache 189 #define TARGET_ENDIANNESS 190 #include "exec/memory_ldst.h.inc" 191 192 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) 193 { 194 address_space_stl_notdirty(as, addr, val, 195 MEMTXATTRS_UNSPECIFIED, NULL); 196 } 197 198 #define SUFFIX 199 #define ARG1 as 200 #define ARG1_DECL AddressSpace *as 201 #define TARGET_ENDIANNESS 202 #include "exec/memory_ldst_phys.h.inc" 203 204 /* Inline fast path for direct RAM access. */ 205 #define ENDIANNESS 206 #include "exec/memory_ldst_cached.h.inc" 207 208 #define SUFFIX _cached 209 #define ARG1 cache 210 #define ARG1_DECL MemoryRegionCache *cache 211 #define TARGET_ENDIANNESS 212 #include "exec/memory_ldst_phys.h.inc" 213 #endif 214 215 /* page related stuff */ 216 217 #ifdef TARGET_PAGE_BITS_VARY 218 # include "exec/page-vary.h" 219 extern const TargetPageBits target_page; 220 #ifdef CONFIG_DEBUG_TCG 221 #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; }) 222 #define TARGET_PAGE_MASK ({ assert(target_page.decided); \ 223 (target_long)target_page.mask; }) 224 #else 225 #define TARGET_PAGE_BITS target_page.bits 226 #define TARGET_PAGE_MASK ((target_long)target_page.mask) 227 #endif 228 #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) 229 #else 230 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS 231 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 232 #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) 233 #endif 234 235 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) 236 237 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 238 * when intptr_t is 32-bit and we are aligning a long long. 239 */ 240 extern uintptr_t qemu_host_page_size; 241 extern intptr_t qemu_host_page_mask; 242 243 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) 244 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size) 245 246 /* same as PROT_xxx */ 247 #define PAGE_READ 0x0001 248 #define PAGE_WRITE 0x0002 249 #define PAGE_EXEC 0x0004 250 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 251 #define PAGE_VALID 0x0008 252 /* 253 * Original state of the write flag (used when tracking self-modifying code) 254 */ 255 #define PAGE_WRITE_ORG 0x0010 256 /* 257 * Invalidate the TLB entry immediately, helpful for s390x 258 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() 259 */ 260 #define PAGE_WRITE_INV 0x0020 261 /* For use with page_set_flags: page is being replaced; target_data cleared. */ 262 #define PAGE_RESET 0x0040 263 /* For linux-user, indicates that the page is MAP_ANON. */ 264 #define PAGE_ANON 0x0080 265 266 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 267 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 268 #define PAGE_RESERVED 0x0100 269 #endif 270 /* Target-specific bits that will be used via page_get_flags(). */ 271 #define PAGE_TARGET_1 0x0200 272 #define PAGE_TARGET_2 0x0400 273 274 #if defined(CONFIG_USER_ONLY) 275 void page_dump(FILE *f); 276 277 typedef int (*walk_memory_regions_fn)(void *, target_ulong, 278 target_ulong, unsigned long); 279 int walk_memory_regions(void *, walk_memory_regions_fn); 280 281 int page_get_flags(target_ulong address); 282 void page_set_flags(target_ulong start, target_ulong end, int flags); 283 int page_check_range(target_ulong start, target_ulong len, int flags); 284 285 /** 286 * page_alloc_target_data(address, size) 287 * @address: guest virtual address 288 * @size: size of data to allocate 289 * 290 * Allocate @size bytes of out-of-band data to associate with the 291 * guest page at @address. If the page is not mapped, NULL will 292 * be returned. If there is existing data associated with @address, 293 * no new memory will be allocated. 294 * 295 * The memory will be freed when the guest page is deallocated, 296 * e.g. with the munmap system call. 297 */ 298 void *page_alloc_target_data(target_ulong address, size_t size); 299 300 /** 301 * page_get_target_data(address) 302 * @address: guest virtual address 303 * 304 * Return any out-of-bound memory assocated with the guest page 305 * at @address, as per page_alloc_target_data. 306 */ 307 void *page_get_target_data(target_ulong address); 308 #endif 309 310 CPUArchState *cpu_copy(CPUArchState *env); 311 312 /* Flags for use in ENV->INTERRUPT_PENDING. 313 314 The numbers assigned here are non-sequential in order to preserve 315 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 316 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 317 the vmstate dump. */ 318 319 /* External hardware interrupt pending. This is typically used for 320 interrupts from devices. */ 321 #define CPU_INTERRUPT_HARD 0x0002 322 323 /* Exit the current TB. This is typically used when some system-level device 324 makes some change to the memory mapping. E.g. the a20 line change. */ 325 #define CPU_INTERRUPT_EXITTB 0x0004 326 327 /* Halt the CPU. */ 328 #define CPU_INTERRUPT_HALT 0x0020 329 330 /* Debug event pending. */ 331 #define CPU_INTERRUPT_DEBUG 0x0080 332 333 /* Reset signal. */ 334 #define CPU_INTERRUPT_RESET 0x0400 335 336 /* Several target-specific external hardware interrupts. Each target/cpu.h 337 should define proper names based on these defines. */ 338 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 339 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 340 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 341 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 342 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 343 344 /* Several target-specific internal interrupts. These differ from the 345 preceding target-specific interrupts in that they are intended to 346 originate from within the cpu itself, typically in response to some 347 instruction being executed. These, therefore, are not masked while 348 single-stepping within the debugger. */ 349 #define CPU_INTERRUPT_TGT_INT_0 0x0100 350 #define CPU_INTERRUPT_TGT_INT_1 0x0800 351 #define CPU_INTERRUPT_TGT_INT_2 0x2000 352 353 /* First unused bit: 0x4000. */ 354 355 /* The set of all bits that should be masked when single-stepping. */ 356 #define CPU_INTERRUPT_SSTEP_MASK \ 357 (CPU_INTERRUPT_HARD \ 358 | CPU_INTERRUPT_TGT_EXT_0 \ 359 | CPU_INTERRUPT_TGT_EXT_1 \ 360 | CPU_INTERRUPT_TGT_EXT_2 \ 361 | CPU_INTERRUPT_TGT_EXT_3 \ 362 | CPU_INTERRUPT_TGT_EXT_4) 363 364 #ifdef CONFIG_USER_ONLY 365 366 /* 367 * Allow some level of source compatibility with softmmu. We do not 368 * support any of the more exotic features, so only invalid pages may 369 * be signaled by probe_access_flags(). 370 */ 371 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 372 #define TLB_MMIO 0 373 #define TLB_WATCHPOINT 0 374 375 #else 376 377 /* 378 * Flags stored in the low bits of the TLB virtual address. 379 * These are defined so that fast path ram access is all zeros. 380 * The flags all must be between TARGET_PAGE_BITS and 381 * maximum address alignment bit. 382 * 383 * Use TARGET_PAGE_BITS_MIN so that these bits are constant 384 * when TARGET_PAGE_BITS_VARY is in effect. 385 */ 386 /* Zero if TLB entry is valid. */ 387 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 388 /* Set if TLB entry references a clean RAM page. The iotlb entry will 389 contain the page physical address. */ 390 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) 391 /* Set if TLB entry is an IO callback. */ 392 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) 393 /* Set if TLB entry contains a watchpoint. */ 394 #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) 395 /* Set if TLB entry requires byte swap. */ 396 #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) 397 /* Set if TLB entry writes ignored. */ 398 #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) 399 400 /* Use this mask to check interception with an alignment mask 401 * in a TCG backend. 402 */ 403 #define TLB_FLAGS_MASK \ 404 (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ 405 | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) 406 407 /** 408 * tlb_hit_page: return true if page aligned @addr is a hit against the 409 * TLB entry @tlb_addr 410 * 411 * @addr: virtual address to test (must be page aligned) 412 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 413 */ 414 static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr) 415 { 416 return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); 417 } 418 419 /** 420 * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr 421 * 422 * @addr: virtual address to test (need not be page aligned) 423 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 424 */ 425 static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr) 426 { 427 return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); 428 } 429 430 #ifdef CONFIG_TCG 431 /* accel/tcg/cpu-exec.c */ 432 void dump_drift_info(void); 433 /* accel/tcg/translate-all.c */ 434 void dump_exec_info(void); 435 void dump_opcount_info(void); 436 #endif /* CONFIG_TCG */ 437 438 #endif /* !CONFIG_USER_ONLY */ 439 440 #ifdef CONFIG_TCG 441 /* accel/tcg/cpu-exec.c */ 442 int cpu_exec(CPUState *cpu); 443 void tcg_exec_realizefn(CPUState *cpu, Error **errp); 444 void tcg_exec_unrealizefn(CPUState *cpu); 445 #endif /* CONFIG_TCG */ 446 447 /* Returns: 0 on success, -1 on error */ 448 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 449 void *ptr, target_ulong len, bool is_write); 450 451 /** 452 * cpu_set_cpustate_pointers(cpu) 453 * @cpu: The cpu object 454 * 455 * Set the generic pointers in CPUState into the outer object. 456 */ 457 static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) 458 { 459 cpu->parent_obj.env_ptr = &cpu->env; 460 cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr; 461 } 462 463 /** 464 * env_archcpu(env) 465 * @env: The architecture environment 466 * 467 * Return the ArchCPU associated with the environment. 468 */ 469 static inline ArchCPU *env_archcpu(CPUArchState *env) 470 { 471 return container_of(env, ArchCPU, env); 472 } 473 474 /** 475 * env_cpu(env) 476 * @env: The architecture environment 477 * 478 * Return the CPUState associated with the environment. 479 */ 480 static inline CPUState *env_cpu(CPUArchState *env) 481 { 482 return &env_archcpu(env)->parent_obj; 483 } 484 485 /** 486 * env_neg(env) 487 * @env: The architecture environment 488 * 489 * Return the CPUNegativeOffsetState associated with the environment. 490 */ 491 static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) 492 { 493 ArchCPU *arch_cpu = container_of(env, ArchCPU, env); 494 return &arch_cpu->neg; 495 } 496 497 /** 498 * cpu_neg(cpu) 499 * @cpu: The generic CPUState 500 * 501 * Return the CPUNegativeOffsetState associated with the cpu. 502 */ 503 static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) 504 { 505 ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj); 506 return &arch_cpu->neg; 507 } 508 509 /** 510 * env_tlb(env) 511 * @env: The architecture environment 512 * 513 * Return the CPUTLB state associated with the environment. 514 */ 515 static inline CPUTLB *env_tlb(CPUArchState *env) 516 { 517 return &env_neg(env)->tlb; 518 } 519 520 #endif /* CPU_ALL_H */ 521