1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "qemu-common.h" 23 #include "exec/cpu-common.h" 24 #include "exec/memory.h" 25 #include "qemu/thread.h" 26 #include "qom/cpu.h" 27 #include "qemu/rcu.h" 28 29 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 30 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 31 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 32 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 33 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 34 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 35 36 /* some important defines: 37 * 38 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and 39 * otherwise little endian. 40 * 41 * TARGET_WORDS_BIGENDIAN : same for target cpu 42 */ 43 44 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) 45 #define BSWAP_NEEDED 46 #endif 47 48 #ifdef BSWAP_NEEDED 49 50 static inline uint16_t tswap16(uint16_t s) 51 { 52 return bswap16(s); 53 } 54 55 static inline uint32_t tswap32(uint32_t s) 56 { 57 return bswap32(s); 58 } 59 60 static inline uint64_t tswap64(uint64_t s) 61 { 62 return bswap64(s); 63 } 64 65 static inline void tswap16s(uint16_t *s) 66 { 67 *s = bswap16(*s); 68 } 69 70 static inline void tswap32s(uint32_t *s) 71 { 72 *s = bswap32(*s); 73 } 74 75 static inline void tswap64s(uint64_t *s) 76 { 77 *s = bswap64(*s); 78 } 79 80 #else 81 82 static inline uint16_t tswap16(uint16_t s) 83 { 84 return s; 85 } 86 87 static inline uint32_t tswap32(uint32_t s) 88 { 89 return s; 90 } 91 92 static inline uint64_t tswap64(uint64_t s) 93 { 94 return s; 95 } 96 97 static inline void tswap16s(uint16_t *s) 98 { 99 } 100 101 static inline void tswap32s(uint32_t *s) 102 { 103 } 104 105 static inline void tswap64s(uint64_t *s) 106 { 107 } 108 109 #endif 110 111 #if TARGET_LONG_SIZE == 4 112 #define tswapl(s) tswap32(s) 113 #define tswapls(s) tswap32s((uint32_t *)(s)) 114 #define bswaptls(s) bswap32s(s) 115 #else 116 #define tswapl(s) tswap64(s) 117 #define tswapls(s) tswap64s((uint64_t *)(s)) 118 #define bswaptls(s) bswap64s(s) 119 #endif 120 121 /* Target-endianness CPU memory access functions. These fit into the 122 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. 123 */ 124 #if defined(TARGET_WORDS_BIGENDIAN) 125 #define lduw_p(p) lduw_be_p(p) 126 #define ldsw_p(p) ldsw_be_p(p) 127 #define ldl_p(p) ldl_be_p(p) 128 #define ldq_p(p) ldq_be_p(p) 129 #define ldfl_p(p) ldfl_be_p(p) 130 #define ldfq_p(p) ldfq_be_p(p) 131 #define stw_p(p, v) stw_be_p(p, v) 132 #define stl_p(p, v) stl_be_p(p, v) 133 #define stq_p(p, v) stq_be_p(p, v) 134 #define stfl_p(p, v) stfl_be_p(p, v) 135 #define stfq_p(p, v) stfq_be_p(p, v) 136 #define ldn_p(p, sz) ldn_be_p(p, sz) 137 #define stn_p(p, sz, v) stn_be_p(p, sz, v) 138 #else 139 #define lduw_p(p) lduw_le_p(p) 140 #define ldsw_p(p) ldsw_le_p(p) 141 #define ldl_p(p) ldl_le_p(p) 142 #define ldq_p(p) ldq_le_p(p) 143 #define ldfl_p(p) ldfl_le_p(p) 144 #define ldfq_p(p) ldfq_le_p(p) 145 #define stw_p(p, v) stw_le_p(p, v) 146 #define stl_p(p, v) stl_le_p(p, v) 147 #define stq_p(p, v) stq_le_p(p, v) 148 #define stfl_p(p, v) stfl_le_p(p, v) 149 #define stfq_p(p, v) stfq_le_p(p, v) 150 #define ldn_p(p, sz) ldn_le_p(p, sz) 151 #define stn_p(p, sz, v) stn_le_p(p, sz, v) 152 #endif 153 154 /* MMU memory access macros */ 155 156 #if defined(CONFIG_USER_ONLY) 157 #include "exec/user/abitypes.h" 158 159 /* On some host systems the guest address space is reserved on the host. 160 * This allows the guest address space to be offset to a convenient location. 161 */ 162 extern unsigned long guest_base; 163 extern int have_guest_base; 164 extern unsigned long reserved_va; 165 166 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS 167 #define GUEST_ADDR_MAX (~0ul) 168 #else 169 #define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : \ 170 (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1) 171 #endif 172 #else 173 174 #include "exec/hwaddr.h" 175 176 #define SUFFIX 177 #define ARG1 as 178 #define ARG1_DECL AddressSpace *as 179 #define TARGET_ENDIANNESS 180 #include "exec/memory_ldst.inc.h" 181 182 #define SUFFIX _cached_slow 183 #define ARG1 cache 184 #define ARG1_DECL MemoryRegionCache *cache 185 #define TARGET_ENDIANNESS 186 #include "exec/memory_ldst.inc.h" 187 188 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) 189 { 190 address_space_stl_notdirty(as, addr, val, 191 MEMTXATTRS_UNSPECIFIED, NULL); 192 } 193 194 #define SUFFIX 195 #define ARG1 as 196 #define ARG1_DECL AddressSpace *as 197 #define TARGET_ENDIANNESS 198 #include "exec/memory_ldst_phys.inc.h" 199 200 /* Inline fast path for direct RAM access. */ 201 #define ENDIANNESS 202 #include "exec/memory_ldst_cached.inc.h" 203 204 #define SUFFIX _cached 205 #define ARG1 cache 206 #define ARG1_DECL MemoryRegionCache *cache 207 #define TARGET_ENDIANNESS 208 #include "exec/memory_ldst_phys.inc.h" 209 #endif 210 211 /* page related stuff */ 212 213 #ifdef TARGET_PAGE_BITS_VARY 214 extern bool target_page_bits_decided; 215 extern int target_page_bits; 216 #define TARGET_PAGE_BITS ({ assert(target_page_bits_decided); \ 217 target_page_bits; }) 218 #else 219 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS 220 #endif 221 222 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 223 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) 224 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) 225 226 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 227 * when intptr_t is 32-bit and we are aligning a long long. 228 */ 229 extern uintptr_t qemu_host_page_size; 230 extern intptr_t qemu_host_page_mask; 231 232 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) 233 #define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \ 234 qemu_real_host_page_mask) 235 236 /* same as PROT_xxx */ 237 #define PAGE_READ 0x0001 238 #define PAGE_WRITE 0x0002 239 #define PAGE_EXEC 0x0004 240 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 241 #define PAGE_VALID 0x0008 242 /* original state of the write flag (used when tracking self-modifying 243 code */ 244 #define PAGE_WRITE_ORG 0x0010 245 /* Invalidate the TLB entry immediately, helpful for s390x 246 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ 247 #define PAGE_WRITE_INV 0x0040 248 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 249 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 250 #define PAGE_RESERVED 0x0020 251 #endif 252 253 #if defined(CONFIG_USER_ONLY) 254 void page_dump(FILE *f); 255 256 typedef int (*walk_memory_regions_fn)(void *, target_ulong, 257 target_ulong, unsigned long); 258 int walk_memory_regions(void *, walk_memory_regions_fn); 259 260 int page_get_flags(target_ulong address); 261 void page_set_flags(target_ulong start, target_ulong end, int flags); 262 int page_check_range(target_ulong start, target_ulong len, int flags); 263 #endif 264 265 CPUArchState *cpu_copy(CPUArchState *env); 266 267 /* Flags for use in ENV->INTERRUPT_PENDING. 268 269 The numbers assigned here are non-sequential in order to preserve 270 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 271 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 272 the vmstate dump. */ 273 274 /* External hardware interrupt pending. This is typically used for 275 interrupts from devices. */ 276 #define CPU_INTERRUPT_HARD 0x0002 277 278 /* Exit the current TB. This is typically used when some system-level device 279 makes some change to the memory mapping. E.g. the a20 line change. */ 280 #define CPU_INTERRUPT_EXITTB 0x0004 281 282 /* Halt the CPU. */ 283 #define CPU_INTERRUPT_HALT 0x0020 284 285 /* Debug event pending. */ 286 #define CPU_INTERRUPT_DEBUG 0x0080 287 288 /* Reset signal. */ 289 #define CPU_INTERRUPT_RESET 0x0400 290 291 /* Several target-specific external hardware interrupts. Each target/cpu.h 292 should define proper names based on these defines. */ 293 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 294 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 295 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 296 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 297 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 298 299 /* Several target-specific internal interrupts. These differ from the 300 preceding target-specific interrupts in that they are intended to 301 originate from within the cpu itself, typically in response to some 302 instruction being executed. These, therefore, are not masked while 303 single-stepping within the debugger. */ 304 #define CPU_INTERRUPT_TGT_INT_0 0x0100 305 #define CPU_INTERRUPT_TGT_INT_1 0x0800 306 #define CPU_INTERRUPT_TGT_INT_2 0x2000 307 308 /* First unused bit: 0x4000. */ 309 310 /* The set of all bits that should be masked when single-stepping. */ 311 #define CPU_INTERRUPT_SSTEP_MASK \ 312 (CPU_INTERRUPT_HARD \ 313 | CPU_INTERRUPT_TGT_EXT_0 \ 314 | CPU_INTERRUPT_TGT_EXT_1 \ 315 | CPU_INTERRUPT_TGT_EXT_2 \ 316 | CPU_INTERRUPT_TGT_EXT_3 \ 317 | CPU_INTERRUPT_TGT_EXT_4) 318 319 #if !defined(CONFIG_USER_ONLY) 320 321 /* Flags stored in the low bits of the TLB virtual address. These are 322 * defined so that fast path ram access is all zeros. 323 * The flags all must be between TARGET_PAGE_BITS and 324 * maximum address alignment bit. 325 */ 326 /* Zero if TLB entry is valid. */ 327 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS - 1)) 328 /* Set if TLB entry references a clean RAM page. The iotlb entry will 329 contain the page physical address. */ 330 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) 331 /* Set if TLB entry is an IO callback. */ 332 #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) 333 /* Set if TLB entry must have MMU lookup repeated for every access */ 334 #define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4)) 335 336 /* Use this mask to check interception with an alignment mask 337 * in a TCG backend. 338 */ 339 #define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ 340 | TLB_RECHECK) 341 342 /** 343 * tlb_hit_page: return true if page aligned @addr is a hit against the 344 * TLB entry @tlb_addr 345 * 346 * @addr: virtual address to test (must be page aligned) 347 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 348 */ 349 static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr) 350 { 351 return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); 352 } 353 354 /** 355 * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr 356 * 357 * @addr: virtual address to test (need not be page aligned) 358 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 359 */ 360 static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr) 361 { 362 return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); 363 } 364 365 void dump_exec_info(void); 366 void dump_opcount_info(void); 367 #endif /* !CONFIG_USER_ONLY */ 368 369 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 370 uint8_t *buf, target_ulong len, int is_write); 371 372 int cpu_exec(CPUState *cpu); 373 374 #endif /* CPU_ALL_H */ 375