1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "exec/cpu-common.h" 23 #include "exec/memory.h" 24 #include "exec/tswap.h" 25 #include "qemu/thread.h" 26 #include "hw/core/cpu.h" 27 #include "qemu/rcu.h" 28 29 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 30 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 31 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 32 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 33 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 34 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 35 36 /* some important defines: 37 * 38 * HOST_BIG_ENDIAN : whether the host cpu is big endian and 39 * otherwise little endian. 40 * 41 * TARGET_BIG_ENDIAN : same for the target cpu 42 */ 43 44 #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN 45 #define BSWAP_NEEDED 46 #endif 47 48 #if TARGET_LONG_SIZE == 4 49 #define tswapl(s) tswap32(s) 50 #define tswapls(s) tswap32s((uint32_t *)(s)) 51 #define bswaptls(s) bswap32s(s) 52 #else 53 #define tswapl(s) tswap64(s) 54 #define tswapls(s) tswap64s((uint64_t *)(s)) 55 #define bswaptls(s) bswap64s(s) 56 #endif 57 58 /* Target-endianness CPU memory access functions. These fit into the 59 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. 60 */ 61 #if TARGET_BIG_ENDIAN 62 #define lduw_p(p) lduw_be_p(p) 63 #define ldsw_p(p) ldsw_be_p(p) 64 #define ldl_p(p) ldl_be_p(p) 65 #define ldq_p(p) ldq_be_p(p) 66 #define stw_p(p, v) stw_be_p(p, v) 67 #define stl_p(p, v) stl_be_p(p, v) 68 #define stq_p(p, v) stq_be_p(p, v) 69 #define ldn_p(p, sz) ldn_be_p(p, sz) 70 #define stn_p(p, sz, v) stn_be_p(p, sz, v) 71 #else 72 #define lduw_p(p) lduw_le_p(p) 73 #define ldsw_p(p) ldsw_le_p(p) 74 #define ldl_p(p) ldl_le_p(p) 75 #define ldq_p(p) ldq_le_p(p) 76 #define stw_p(p, v) stw_le_p(p, v) 77 #define stl_p(p, v) stl_le_p(p, v) 78 #define stq_p(p, v) stq_le_p(p, v) 79 #define ldn_p(p, sz) ldn_le_p(p, sz) 80 #define stn_p(p, sz, v) stn_le_p(p, sz, v) 81 #endif 82 83 /* MMU memory access macros */ 84 85 #if defined(CONFIG_USER_ONLY) 86 #include "exec/user/abitypes.h" 87 #include "exec/user/guest-base.h" 88 89 extern bool have_guest_base; 90 91 /* 92 * If non-zero, the guest virtual address space is a contiguous subset 93 * of the host virtual address space, i.e. '-R reserved_va' is in effect 94 * either from the command-line or by default. The value is the last 95 * byte of the guest address space e.g. UINT32_MAX. 96 * 97 * If zero, the host and guest virtual address spaces are intermingled. 98 */ 99 extern unsigned long reserved_va; 100 101 /* 102 * Limit the guest addresses as best we can. 103 * 104 * When not using -R reserved_va, we cannot really limit the guest 105 * to less address space than the host. For 32-bit guests, this 106 * acts as a sanity check that we're not giving the guest an address 107 * that it cannot even represent. For 64-bit guests... the address 108 * might not be what the real kernel would give, but it is at least 109 * representable in the guest. 110 * 111 * TODO: Improve address allocation to avoid this problem, and to 112 * avoid setting bits at the top of guest addresses that might need 113 * to be used for tags. 114 */ 115 #define GUEST_ADDR_MAX_ \ 116 ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \ 117 UINT32_MAX : ~0ul) 118 #define GUEST_ADDR_MAX (reserved_va ? : GUEST_ADDR_MAX_) 119 120 #else 121 122 #include "exec/hwaddr.h" 123 124 #define SUFFIX 125 #define ARG1 as 126 #define ARG1_DECL AddressSpace *as 127 #define TARGET_ENDIANNESS 128 #include "exec/memory_ldst.h.inc" 129 130 #define SUFFIX _cached_slow 131 #define ARG1 cache 132 #define ARG1_DECL MemoryRegionCache *cache 133 #define TARGET_ENDIANNESS 134 #include "exec/memory_ldst.h.inc" 135 136 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) 137 { 138 address_space_stl_notdirty(as, addr, val, 139 MEMTXATTRS_UNSPECIFIED, NULL); 140 } 141 142 #define SUFFIX 143 #define ARG1 as 144 #define ARG1_DECL AddressSpace *as 145 #define TARGET_ENDIANNESS 146 #include "exec/memory_ldst_phys.h.inc" 147 148 /* Inline fast path for direct RAM access. */ 149 #define ENDIANNESS 150 #include "exec/memory_ldst_cached.h.inc" 151 152 #define SUFFIX _cached 153 #define ARG1 cache 154 #define ARG1_DECL MemoryRegionCache *cache 155 #define TARGET_ENDIANNESS 156 #include "exec/memory_ldst_phys.h.inc" 157 #endif 158 159 /* page related stuff */ 160 161 #ifdef TARGET_PAGE_BITS_VARY 162 # include "exec/page-vary.h" 163 extern const TargetPageBits target_page; 164 #ifdef CONFIG_DEBUG_TCG 165 #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; }) 166 #define TARGET_PAGE_MASK ({ assert(target_page.decided); \ 167 (target_long)target_page.mask; }) 168 #else 169 #define TARGET_PAGE_BITS target_page.bits 170 #define TARGET_PAGE_MASK ((target_long)target_page.mask) 171 #endif 172 #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) 173 #else 174 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS 175 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 176 #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) 177 #endif 178 179 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) 180 181 /* same as PROT_xxx */ 182 #define PAGE_READ 0x0001 183 #define PAGE_WRITE 0x0002 184 #define PAGE_EXEC 0x0004 185 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 186 #define PAGE_VALID 0x0008 187 /* 188 * Original state of the write flag (used when tracking self-modifying code) 189 */ 190 #define PAGE_WRITE_ORG 0x0010 191 /* 192 * Invalidate the TLB entry immediately, helpful for s390x 193 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() 194 */ 195 #define PAGE_WRITE_INV 0x0020 196 /* For use with page_set_flags: page is being replaced; target_data cleared. */ 197 #define PAGE_RESET 0x0040 198 /* For linux-user, indicates that the page is MAP_ANON. */ 199 #define PAGE_ANON 0x0080 200 201 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 202 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 203 #define PAGE_RESERVED 0x0100 204 #endif 205 /* Target-specific bits that will be used via page_get_flags(). */ 206 #define PAGE_TARGET_1 0x0200 207 #define PAGE_TARGET_2 0x0400 208 209 /* 210 * For linux-user, indicates that the page is mapped with the same semantics 211 * in both guest and host. 212 */ 213 #define PAGE_PASSTHROUGH 0x0800 214 215 #if defined(CONFIG_USER_ONLY) 216 void page_dump(FILE *f); 217 218 typedef int (*walk_memory_regions_fn)(void *, target_ulong, 219 target_ulong, unsigned long); 220 int walk_memory_regions(void *, walk_memory_regions_fn); 221 222 int page_get_flags(target_ulong address); 223 void page_set_flags(target_ulong start, target_ulong last, int flags); 224 void page_reset_target_data(target_ulong start, target_ulong last); 225 int page_check_range(target_ulong start, target_ulong len, int flags); 226 227 /** 228 * page_get_target_data(address) 229 * @address: guest virtual address 230 * 231 * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate 232 * with the guest page at @address, allocating it if necessary. The 233 * caller should already have verified that the address is valid. 234 * 235 * The memory will be freed when the guest page is deallocated, 236 * e.g. with the munmap system call. 237 */ 238 void *page_get_target_data(target_ulong address) 239 __attribute__((returns_nonnull)); 240 #endif 241 242 CPUArchState *cpu_copy(CPUArchState *env); 243 244 /* Flags for use in ENV->INTERRUPT_PENDING. 245 246 The numbers assigned here are non-sequential in order to preserve 247 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 248 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 249 the vmstate dump. */ 250 251 /* External hardware interrupt pending. This is typically used for 252 interrupts from devices. */ 253 #define CPU_INTERRUPT_HARD 0x0002 254 255 /* Exit the current TB. This is typically used when some system-level device 256 makes some change to the memory mapping. E.g. the a20 line change. */ 257 #define CPU_INTERRUPT_EXITTB 0x0004 258 259 /* Halt the CPU. */ 260 #define CPU_INTERRUPT_HALT 0x0020 261 262 /* Debug event pending. */ 263 #define CPU_INTERRUPT_DEBUG 0x0080 264 265 /* Reset signal. */ 266 #define CPU_INTERRUPT_RESET 0x0400 267 268 /* Several target-specific external hardware interrupts. Each target/cpu.h 269 should define proper names based on these defines. */ 270 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 271 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 272 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 273 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 274 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 275 276 /* Several target-specific internal interrupts. These differ from the 277 preceding target-specific interrupts in that they are intended to 278 originate from within the cpu itself, typically in response to some 279 instruction being executed. These, therefore, are not masked while 280 single-stepping within the debugger. */ 281 #define CPU_INTERRUPT_TGT_INT_0 0x0100 282 #define CPU_INTERRUPT_TGT_INT_1 0x0800 283 #define CPU_INTERRUPT_TGT_INT_2 0x2000 284 285 /* First unused bit: 0x4000. */ 286 287 /* The set of all bits that should be masked when single-stepping. */ 288 #define CPU_INTERRUPT_SSTEP_MASK \ 289 (CPU_INTERRUPT_HARD \ 290 | CPU_INTERRUPT_TGT_EXT_0 \ 291 | CPU_INTERRUPT_TGT_EXT_1 \ 292 | CPU_INTERRUPT_TGT_EXT_2 \ 293 | CPU_INTERRUPT_TGT_EXT_3 \ 294 | CPU_INTERRUPT_TGT_EXT_4) 295 296 #ifdef CONFIG_USER_ONLY 297 298 /* 299 * Allow some level of source compatibility with softmmu. We do not 300 * support any of the more exotic features, so only invalid pages may 301 * be signaled by probe_access_flags(). 302 */ 303 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 304 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) 305 #define TLB_WATCHPOINT 0 306 307 #else 308 309 /* 310 * Flags stored in the low bits of the TLB virtual address. 311 * These are defined so that fast path ram access is all zeros. 312 * The flags all must be between TARGET_PAGE_BITS and 313 * maximum address alignment bit. 314 * 315 * Use TARGET_PAGE_BITS_MIN so that these bits are constant 316 * when TARGET_PAGE_BITS_VARY is in effect. 317 * 318 * The count, if not the placement of these bits is known 319 * to tcg/tcg-op-ldst.c, check_max_alignment(). 320 */ 321 /* Zero if TLB entry is valid. */ 322 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 323 /* Set if TLB entry references a clean RAM page. The iotlb entry will 324 contain the page physical address. */ 325 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) 326 /* Set if TLB entry is an IO callback. */ 327 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) 328 /* Set if TLB entry writes ignored. */ 329 #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) 330 /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ 331 #define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) 332 333 /* 334 * Use this mask to check interception with an alignment mask 335 * in a TCG backend. 336 */ 337 #define TLB_FLAGS_MASK \ 338 (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ 339 | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) 340 341 /* 342 * Flags stored in CPUTLBEntryFull.slow_flags[x]. 343 * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. 344 */ 345 /* Set if TLB entry requires byte swap. */ 346 #define TLB_BSWAP (1 << 0) 347 /* Set if TLB entry contains a watchpoint. */ 348 #define TLB_WATCHPOINT (1 << 1) 349 350 #define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) 351 352 /* The two sets of flags must not overlap. */ 353 QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); 354 355 /** 356 * tlb_hit_page: return true if page aligned @addr is a hit against the 357 * TLB entry @tlb_addr 358 * 359 * @addr: virtual address to test (must be page aligned) 360 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 361 */ 362 static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr) 363 { 364 return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); 365 } 366 367 /** 368 * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr 369 * 370 * @addr: virtual address to test (need not be page aligned) 371 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 372 */ 373 static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr) 374 { 375 return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); 376 } 377 378 #ifdef CONFIG_TCG 379 /* accel/tcg/translate-all.c */ 380 void dump_exec_info(GString *buf); 381 #endif /* CONFIG_TCG */ 382 383 #endif /* !CONFIG_USER_ONLY */ 384 385 /* accel/tcg/cpu-exec.c */ 386 int cpu_exec(CPUState *cpu); 387 void tcg_exec_realizefn(CPUState *cpu, Error **errp); 388 void tcg_exec_unrealizefn(CPUState *cpu); 389 390 /** 391 * cpu_set_cpustate_pointers(cpu) 392 * @cpu: The cpu object 393 * 394 * Set the generic pointers in CPUState into the outer object. 395 */ 396 static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) 397 { 398 cpu->parent_obj.env_ptr = &cpu->env; 399 cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr; 400 } 401 402 /** 403 * env_archcpu(env) 404 * @env: The architecture environment 405 * 406 * Return the ArchCPU associated with the environment. 407 */ 408 static inline ArchCPU *env_archcpu(CPUArchState *env) 409 { 410 return container_of(env, ArchCPU, env); 411 } 412 413 /** 414 * env_cpu(env) 415 * @env: The architecture environment 416 * 417 * Return the CPUState associated with the environment. 418 */ 419 static inline CPUState *env_cpu(CPUArchState *env) 420 { 421 return &env_archcpu(env)->parent_obj; 422 } 423 424 /** 425 * env_neg(env) 426 * @env: The architecture environment 427 * 428 * Return the CPUNegativeOffsetState associated with the environment. 429 */ 430 static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) 431 { 432 ArchCPU *arch_cpu = container_of(env, ArchCPU, env); 433 return &arch_cpu->neg; 434 } 435 436 /** 437 * cpu_neg(cpu) 438 * @cpu: The generic CPUState 439 * 440 * Return the CPUNegativeOffsetState associated with the cpu. 441 */ 442 static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) 443 { 444 ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj); 445 return &arch_cpu->neg; 446 } 447 448 /** 449 * env_tlb(env) 450 * @env: The architecture environment 451 * 452 * Return the CPUTLB state associated with the environment. 453 */ 454 static inline CPUTLB *env_tlb(CPUArchState *env) 455 { 456 return &env_neg(env)->tlb; 457 } 458 459 #endif /* CPU_ALL_H */ 460