1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "qemu-common.h" 23 #include "exec/cpu-common.h" 24 #include "exec/memory.h" 25 #include "qemu/thread.h" 26 #include "qom/cpu.h" 27 #include "qemu/rcu.h" 28 29 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 30 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 31 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 32 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 33 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 34 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 35 36 /* some important defines: 37 * 38 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and 39 * otherwise little endian. 40 * 41 * TARGET_WORDS_BIGENDIAN : same for target cpu 42 */ 43 44 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) 45 #define BSWAP_NEEDED 46 #endif 47 48 #ifdef BSWAP_NEEDED 49 50 static inline uint16_t tswap16(uint16_t s) 51 { 52 return bswap16(s); 53 } 54 55 static inline uint32_t tswap32(uint32_t s) 56 { 57 return bswap32(s); 58 } 59 60 static inline uint64_t tswap64(uint64_t s) 61 { 62 return bswap64(s); 63 } 64 65 static inline void tswap16s(uint16_t *s) 66 { 67 *s = bswap16(*s); 68 } 69 70 static inline void tswap32s(uint32_t *s) 71 { 72 *s = bswap32(*s); 73 } 74 75 static inline void tswap64s(uint64_t *s) 76 { 77 *s = bswap64(*s); 78 } 79 80 #else 81 82 static inline uint16_t tswap16(uint16_t s) 83 { 84 return s; 85 } 86 87 static inline uint32_t tswap32(uint32_t s) 88 { 89 return s; 90 } 91 92 static inline uint64_t tswap64(uint64_t s) 93 { 94 return s; 95 } 96 97 static inline void tswap16s(uint16_t *s) 98 { 99 } 100 101 static inline void tswap32s(uint32_t *s) 102 { 103 } 104 105 static inline void tswap64s(uint64_t *s) 106 { 107 } 108 109 #endif 110 111 #if TARGET_LONG_SIZE == 4 112 #define tswapl(s) tswap32(s) 113 #define tswapls(s) tswap32s((uint32_t *)(s)) 114 #define bswaptls(s) bswap32s(s) 115 #else 116 #define tswapl(s) tswap64(s) 117 #define tswapls(s) tswap64s((uint64_t *)(s)) 118 #define bswaptls(s) bswap64s(s) 119 #endif 120 121 /* Target-endianness CPU memory access functions. These fit into the 122 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. 123 */ 124 #if defined(TARGET_WORDS_BIGENDIAN) 125 #define lduw_p(p) lduw_be_p(p) 126 #define ldsw_p(p) ldsw_be_p(p) 127 #define ldl_p(p) ldl_be_p(p) 128 #define ldq_p(p) ldq_be_p(p) 129 #define ldfl_p(p) ldfl_be_p(p) 130 #define ldfq_p(p) ldfq_be_p(p) 131 #define stw_p(p, v) stw_be_p(p, v) 132 #define stl_p(p, v) stl_be_p(p, v) 133 #define stq_p(p, v) stq_be_p(p, v) 134 #define stfl_p(p, v) stfl_be_p(p, v) 135 #define stfq_p(p, v) stfq_be_p(p, v) 136 #else 137 #define lduw_p(p) lduw_le_p(p) 138 #define ldsw_p(p) ldsw_le_p(p) 139 #define ldl_p(p) ldl_le_p(p) 140 #define ldq_p(p) ldq_le_p(p) 141 #define ldfl_p(p) ldfl_le_p(p) 142 #define ldfq_p(p) ldfq_le_p(p) 143 #define stw_p(p, v) stw_le_p(p, v) 144 #define stl_p(p, v) stl_le_p(p, v) 145 #define stq_p(p, v) stq_le_p(p, v) 146 #define stfl_p(p, v) stfl_le_p(p, v) 147 #define stfq_p(p, v) stfq_le_p(p, v) 148 #endif 149 150 /* MMU memory access macros */ 151 152 #if defined(CONFIG_USER_ONLY) 153 #include "exec/user/abitypes.h" 154 155 /* On some host systems the guest address space is reserved on the host. 156 * This allows the guest address space to be offset to a convenient location. 157 */ 158 extern unsigned long guest_base; 159 extern int have_guest_base; 160 extern unsigned long reserved_va; 161 162 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS 163 #define GUEST_ADDR_MAX (~0ul) 164 #else 165 #define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : \ 166 (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1) 167 #endif 168 #else 169 170 #include "exec/hwaddr.h" 171 uint32_t lduw_phys(AddressSpace *as, hwaddr addr); 172 uint32_t ldl_phys(AddressSpace *as, hwaddr addr); 173 uint64_t ldq_phys(AddressSpace *as, hwaddr addr); 174 void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val); 175 void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val); 176 void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val); 177 void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val); 178 179 uint32_t address_space_lduw(AddressSpace *as, hwaddr addr, 180 MemTxAttrs attrs, MemTxResult *result); 181 uint32_t address_space_ldl(AddressSpace *as, hwaddr addr, 182 MemTxAttrs attrs, MemTxResult *result); 183 uint64_t address_space_ldq(AddressSpace *as, hwaddr addr, 184 MemTxAttrs attrs, MemTxResult *result); 185 void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val, 186 MemTxAttrs attrs, MemTxResult *result); 187 void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val, 188 MemTxAttrs attrs, MemTxResult *result); 189 void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val, 190 MemTxAttrs attrs, MemTxResult *result); 191 void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val, 192 MemTxAttrs attrs, MemTxResult *result); 193 194 uint32_t lduw_phys_cached(MemoryRegionCache *cache, hwaddr addr); 195 uint32_t ldl_phys_cached(MemoryRegionCache *cache, hwaddr addr); 196 uint64_t ldq_phys_cached(MemoryRegionCache *cache, hwaddr addr); 197 void stl_phys_notdirty_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val); 198 void stw_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val); 199 void stl_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val); 200 void stq_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint64_t val); 201 202 uint32_t address_space_lduw_cached(MemoryRegionCache *cache, hwaddr addr, 203 MemTxAttrs attrs, MemTxResult *result); 204 uint32_t address_space_ldl_cached(MemoryRegionCache *cache, hwaddr addr, 205 MemTxAttrs attrs, MemTxResult *result); 206 uint64_t address_space_ldq_cached(MemoryRegionCache *cache, hwaddr addr, 207 MemTxAttrs attrs, MemTxResult *result); 208 void address_space_stl_notdirty_cached(MemoryRegionCache *cache, hwaddr addr, 209 uint32_t val, MemTxAttrs attrs, MemTxResult *result); 210 void address_space_stw_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val, 211 MemTxAttrs attrs, MemTxResult *result); 212 void address_space_stl_cached(MemoryRegionCache *cache, hwaddr addr, uint32_t val, 213 MemTxAttrs attrs, MemTxResult *result); 214 void address_space_stq_cached(MemoryRegionCache *cache, hwaddr addr, uint64_t val, 215 MemTxAttrs attrs, MemTxResult *result); 216 #endif 217 218 /* page related stuff */ 219 220 #ifdef TARGET_PAGE_BITS_VARY 221 extern bool target_page_bits_decided; 222 extern int target_page_bits; 223 #define TARGET_PAGE_BITS ({ assert(target_page_bits_decided); \ 224 target_page_bits; }) 225 #else 226 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS 227 #endif 228 229 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 230 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) 231 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) 232 233 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 234 * when intptr_t is 32-bit and we are aligning a long long. 235 */ 236 extern uintptr_t qemu_host_page_size; 237 extern intptr_t qemu_host_page_mask; 238 239 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) 240 #define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \ 241 qemu_real_host_page_mask) 242 243 /* same as PROT_xxx */ 244 #define PAGE_READ 0x0001 245 #define PAGE_WRITE 0x0002 246 #define PAGE_EXEC 0x0004 247 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 248 #define PAGE_VALID 0x0008 249 /* original state of the write flag (used when tracking self-modifying 250 code */ 251 #define PAGE_WRITE_ORG 0x0010 252 /* Invalidate the TLB entry immediately, helpful for s390x 253 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ 254 #define PAGE_WRITE_INV 0x0040 255 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 256 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 257 #define PAGE_RESERVED 0x0020 258 #endif 259 260 #if defined(CONFIG_USER_ONLY) 261 void page_dump(FILE *f); 262 263 typedef int (*walk_memory_regions_fn)(void *, target_ulong, 264 target_ulong, unsigned long); 265 int walk_memory_regions(void *, walk_memory_regions_fn); 266 267 int page_get_flags(target_ulong address); 268 void page_set_flags(target_ulong start, target_ulong end, int flags); 269 int page_check_range(target_ulong start, target_ulong len, int flags); 270 #endif 271 272 CPUArchState *cpu_copy(CPUArchState *env); 273 274 /* Flags for use in ENV->INTERRUPT_PENDING. 275 276 The numbers assigned here are non-sequential in order to preserve 277 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 278 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 279 the vmstate dump. */ 280 281 /* External hardware interrupt pending. This is typically used for 282 interrupts from devices. */ 283 #define CPU_INTERRUPT_HARD 0x0002 284 285 /* Exit the current TB. This is typically used when some system-level device 286 makes some change to the memory mapping. E.g. the a20 line change. */ 287 #define CPU_INTERRUPT_EXITTB 0x0004 288 289 /* Halt the CPU. */ 290 #define CPU_INTERRUPT_HALT 0x0020 291 292 /* Debug event pending. */ 293 #define CPU_INTERRUPT_DEBUG 0x0080 294 295 /* Reset signal. */ 296 #define CPU_INTERRUPT_RESET 0x0400 297 298 /* Several target-specific external hardware interrupts. Each target/cpu.h 299 should define proper names based on these defines. */ 300 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 301 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 302 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 303 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 304 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 305 306 /* Several target-specific internal interrupts. These differ from the 307 preceding target-specific interrupts in that they are intended to 308 originate from within the cpu itself, typically in response to some 309 instruction being executed. These, therefore, are not masked while 310 single-stepping within the debugger. */ 311 #define CPU_INTERRUPT_TGT_INT_0 0x0100 312 #define CPU_INTERRUPT_TGT_INT_1 0x0800 313 #define CPU_INTERRUPT_TGT_INT_2 0x2000 314 315 /* First unused bit: 0x4000. */ 316 317 /* The set of all bits that should be masked when single-stepping. */ 318 #define CPU_INTERRUPT_SSTEP_MASK \ 319 (CPU_INTERRUPT_HARD \ 320 | CPU_INTERRUPT_TGT_EXT_0 \ 321 | CPU_INTERRUPT_TGT_EXT_1 \ 322 | CPU_INTERRUPT_TGT_EXT_2 \ 323 | CPU_INTERRUPT_TGT_EXT_3 \ 324 | CPU_INTERRUPT_TGT_EXT_4) 325 326 #if !defined(CONFIG_USER_ONLY) 327 328 /* Flags stored in the low bits of the TLB virtual address. These are 329 * defined so that fast path ram access is all zeros. 330 * The flags all must be between TARGET_PAGE_BITS and 331 * maximum address alignment bit. 332 */ 333 /* Zero if TLB entry is valid. */ 334 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS - 1)) 335 /* Set if TLB entry references a clean RAM page. The iotlb entry will 336 contain the page physical address. */ 337 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS - 2)) 338 /* Set if TLB entry is an IO callback. */ 339 #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) 340 341 /* Use this mask to check interception with an alignment mask 342 * in a TCG backend. 343 */ 344 #define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO) 345 346 void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); 347 void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf); 348 #endif /* !CONFIG_USER_ONLY */ 349 350 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 351 uint8_t *buf, int len, int is_write); 352 353 int cpu_exec(CPUState *cpu); 354 355 #endif /* CPU_ALL_H */ 356