1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "exec/cpu-common.h" 23 #include "exec/memory.h" 24 #include "qemu/thread.h" 25 #include "hw/core/cpu.h" 26 #include "qemu/rcu.h" 27 28 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 29 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 30 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 31 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 32 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 33 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 34 35 /* some important defines: 36 * 37 * HOST_BIG_ENDIAN : whether the host cpu is big endian and 38 * otherwise little endian. 39 * 40 * TARGET_BIG_ENDIAN : same for the target cpu 41 */ 42 43 #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN 44 #define BSWAP_NEEDED 45 #endif 46 47 #ifdef BSWAP_NEEDED 48 49 static inline uint16_t tswap16(uint16_t s) 50 { 51 return bswap16(s); 52 } 53 54 static inline uint32_t tswap32(uint32_t s) 55 { 56 return bswap32(s); 57 } 58 59 static inline uint64_t tswap64(uint64_t s) 60 { 61 return bswap64(s); 62 } 63 64 static inline void tswap16s(uint16_t *s) 65 { 66 *s = bswap16(*s); 67 } 68 69 static inline void tswap32s(uint32_t *s) 70 { 71 *s = bswap32(*s); 72 } 73 74 static inline void tswap64s(uint64_t *s) 75 { 76 *s = bswap64(*s); 77 } 78 79 #else 80 81 static inline uint16_t tswap16(uint16_t s) 82 { 83 return s; 84 } 85 86 static inline uint32_t tswap32(uint32_t s) 87 { 88 return s; 89 } 90 91 static inline uint64_t tswap64(uint64_t s) 92 { 93 return s; 94 } 95 96 static inline void tswap16s(uint16_t *s) 97 { 98 } 99 100 static inline void tswap32s(uint32_t *s) 101 { 102 } 103 104 static inline void tswap64s(uint64_t *s) 105 { 106 } 107 108 #endif 109 110 #if TARGET_LONG_SIZE == 4 111 #define tswapl(s) tswap32(s) 112 #define tswapls(s) tswap32s((uint32_t *)(s)) 113 #define bswaptls(s) bswap32s(s) 114 #else 115 #define tswapl(s) tswap64(s) 116 #define tswapls(s) tswap64s((uint64_t *)(s)) 117 #define bswaptls(s) bswap64s(s) 118 #endif 119 120 /* Target-endianness CPU memory access functions. These fit into the 121 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. 122 */ 123 #if TARGET_BIG_ENDIAN 124 #define lduw_p(p) lduw_be_p(p) 125 #define ldsw_p(p) ldsw_be_p(p) 126 #define ldl_p(p) ldl_be_p(p) 127 #define ldq_p(p) ldq_be_p(p) 128 #define stw_p(p, v) stw_be_p(p, v) 129 #define stl_p(p, v) stl_be_p(p, v) 130 #define stq_p(p, v) stq_be_p(p, v) 131 #define ldn_p(p, sz) ldn_be_p(p, sz) 132 #define stn_p(p, sz, v) stn_be_p(p, sz, v) 133 #else 134 #define lduw_p(p) lduw_le_p(p) 135 #define ldsw_p(p) ldsw_le_p(p) 136 #define ldl_p(p) ldl_le_p(p) 137 #define ldq_p(p) ldq_le_p(p) 138 #define stw_p(p, v) stw_le_p(p, v) 139 #define stl_p(p, v) stl_le_p(p, v) 140 #define stq_p(p, v) stq_le_p(p, v) 141 #define ldn_p(p, sz) ldn_le_p(p, sz) 142 #define stn_p(p, sz, v) stn_le_p(p, sz, v) 143 #endif 144 145 /* MMU memory access macros */ 146 147 #if defined(CONFIG_USER_ONLY) 148 #include "exec/user/abitypes.h" 149 150 /* On some host systems the guest address space is reserved on the host. 151 * This allows the guest address space to be offset to a convenient location. 152 */ 153 extern uintptr_t guest_base; 154 extern bool have_guest_base; 155 156 /* 157 * If non-zero, the guest virtual address space is a contiguous subset 158 * of the host virtual address space, i.e. '-R reserved_va' is in effect 159 * either from the command-line or by default. The value is the last 160 * byte of the guest address space e.g. UINT32_MAX. 161 * 162 * If zero, the host and guest virtual address spaces are intermingled. 163 */ 164 extern unsigned long reserved_va; 165 166 /* 167 * Limit the guest addresses as best we can. 168 * 169 * When not using -R reserved_va, we cannot really limit the guest 170 * to less address space than the host. For 32-bit guests, this 171 * acts as a sanity check that we're not giving the guest an address 172 * that it cannot even represent. For 64-bit guests... the address 173 * might not be what the real kernel would give, but it is at least 174 * representable in the guest. 175 * 176 * TODO: Improve address allocation to avoid this problem, and to 177 * avoid setting bits at the top of guest addresses that might need 178 * to be used for tags. 179 */ 180 #define GUEST_ADDR_MAX_ \ 181 ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \ 182 UINT32_MAX : ~0ul) 183 #define GUEST_ADDR_MAX (reserved_va ? : GUEST_ADDR_MAX_) 184 185 #else 186 187 #include "exec/hwaddr.h" 188 189 #define SUFFIX 190 #define ARG1 as 191 #define ARG1_DECL AddressSpace *as 192 #define TARGET_ENDIANNESS 193 #include "exec/memory_ldst.h.inc" 194 195 #define SUFFIX _cached_slow 196 #define ARG1 cache 197 #define ARG1_DECL MemoryRegionCache *cache 198 #define TARGET_ENDIANNESS 199 #include "exec/memory_ldst.h.inc" 200 201 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) 202 { 203 address_space_stl_notdirty(as, addr, val, 204 MEMTXATTRS_UNSPECIFIED, NULL); 205 } 206 207 #define SUFFIX 208 #define ARG1 as 209 #define ARG1_DECL AddressSpace *as 210 #define TARGET_ENDIANNESS 211 #include "exec/memory_ldst_phys.h.inc" 212 213 /* Inline fast path for direct RAM access. */ 214 #define ENDIANNESS 215 #include "exec/memory_ldst_cached.h.inc" 216 217 #define SUFFIX _cached 218 #define ARG1 cache 219 #define ARG1_DECL MemoryRegionCache *cache 220 #define TARGET_ENDIANNESS 221 #include "exec/memory_ldst_phys.h.inc" 222 #endif 223 224 /* page related stuff */ 225 226 #ifdef TARGET_PAGE_BITS_VARY 227 # include "exec/page-vary.h" 228 extern const TargetPageBits target_page; 229 #ifdef CONFIG_DEBUG_TCG 230 #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; }) 231 #define TARGET_PAGE_MASK ({ assert(target_page.decided); \ 232 (target_long)target_page.mask; }) 233 #else 234 #define TARGET_PAGE_BITS target_page.bits 235 #define TARGET_PAGE_MASK ((target_long)target_page.mask) 236 #endif 237 #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) 238 #else 239 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS 240 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 241 #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) 242 #endif 243 244 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) 245 246 /* same as PROT_xxx */ 247 #define PAGE_READ 0x0001 248 #define PAGE_WRITE 0x0002 249 #define PAGE_EXEC 0x0004 250 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 251 #define PAGE_VALID 0x0008 252 /* 253 * Original state of the write flag (used when tracking self-modifying code) 254 */ 255 #define PAGE_WRITE_ORG 0x0010 256 /* 257 * Invalidate the TLB entry immediately, helpful for s390x 258 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() 259 */ 260 #define PAGE_WRITE_INV 0x0020 261 /* For use with page_set_flags: page is being replaced; target_data cleared. */ 262 #define PAGE_RESET 0x0040 263 /* For linux-user, indicates that the page is MAP_ANON. */ 264 #define PAGE_ANON 0x0080 265 266 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 267 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 268 #define PAGE_RESERVED 0x0100 269 #endif 270 /* Target-specific bits that will be used via page_get_flags(). */ 271 #define PAGE_TARGET_1 0x0200 272 #define PAGE_TARGET_2 0x0400 273 274 /* 275 * For linux-user, indicates that the page is mapped with the same semantics 276 * in both guest and host. 277 */ 278 #define PAGE_PASSTHROUGH 0x0800 279 280 #if defined(CONFIG_USER_ONLY) 281 void page_dump(FILE *f); 282 283 typedef int (*walk_memory_regions_fn)(void *, target_ulong, 284 target_ulong, unsigned long); 285 int walk_memory_regions(void *, walk_memory_regions_fn); 286 287 int page_get_flags(target_ulong address); 288 void page_set_flags(target_ulong start, target_ulong last, int flags); 289 void page_reset_target_data(target_ulong start, target_ulong last); 290 int page_check_range(target_ulong start, target_ulong len, int flags); 291 292 /** 293 * page_get_target_data(address) 294 * @address: guest virtual address 295 * 296 * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate 297 * with the guest page at @address, allocating it if necessary. The 298 * caller should already have verified that the address is valid. 299 * 300 * The memory will be freed when the guest page is deallocated, 301 * e.g. with the munmap system call. 302 */ 303 void *page_get_target_data(target_ulong address) 304 __attribute__((returns_nonnull)); 305 #endif 306 307 CPUArchState *cpu_copy(CPUArchState *env); 308 309 /* Flags for use in ENV->INTERRUPT_PENDING. 310 311 The numbers assigned here are non-sequential in order to preserve 312 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 313 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 314 the vmstate dump. */ 315 316 /* External hardware interrupt pending. This is typically used for 317 interrupts from devices. */ 318 #define CPU_INTERRUPT_HARD 0x0002 319 320 /* Exit the current TB. This is typically used when some system-level device 321 makes some change to the memory mapping. E.g. the a20 line change. */ 322 #define CPU_INTERRUPT_EXITTB 0x0004 323 324 /* Halt the CPU. */ 325 #define CPU_INTERRUPT_HALT 0x0020 326 327 /* Debug event pending. */ 328 #define CPU_INTERRUPT_DEBUG 0x0080 329 330 /* Reset signal. */ 331 #define CPU_INTERRUPT_RESET 0x0400 332 333 /* Several target-specific external hardware interrupts. Each target/cpu.h 334 should define proper names based on these defines. */ 335 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 336 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 337 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 338 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 339 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 340 341 /* Several target-specific internal interrupts. These differ from the 342 preceding target-specific interrupts in that they are intended to 343 originate from within the cpu itself, typically in response to some 344 instruction being executed. These, therefore, are not masked while 345 single-stepping within the debugger. */ 346 #define CPU_INTERRUPT_TGT_INT_0 0x0100 347 #define CPU_INTERRUPT_TGT_INT_1 0x0800 348 #define CPU_INTERRUPT_TGT_INT_2 0x2000 349 350 /* First unused bit: 0x4000. */ 351 352 /* The set of all bits that should be masked when single-stepping. */ 353 #define CPU_INTERRUPT_SSTEP_MASK \ 354 (CPU_INTERRUPT_HARD \ 355 | CPU_INTERRUPT_TGT_EXT_0 \ 356 | CPU_INTERRUPT_TGT_EXT_1 \ 357 | CPU_INTERRUPT_TGT_EXT_2 \ 358 | CPU_INTERRUPT_TGT_EXT_3 \ 359 | CPU_INTERRUPT_TGT_EXT_4) 360 361 #ifdef CONFIG_USER_ONLY 362 363 /* 364 * Allow some level of source compatibility with softmmu. We do not 365 * support any of the more exotic features, so only invalid pages may 366 * be signaled by probe_access_flags(). 367 */ 368 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 369 #define TLB_MMIO 0 370 #define TLB_WATCHPOINT 0 371 372 #else 373 374 /* 375 * Flags stored in the low bits of the TLB virtual address. 376 * These are defined so that fast path ram access is all zeros. 377 * The flags all must be between TARGET_PAGE_BITS and 378 * maximum address alignment bit. 379 * 380 * Use TARGET_PAGE_BITS_MIN so that these bits are constant 381 * when TARGET_PAGE_BITS_VARY is in effect. 382 */ 383 /* Zero if TLB entry is valid. */ 384 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 385 /* Set if TLB entry references a clean RAM page. The iotlb entry will 386 contain the page physical address. */ 387 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) 388 /* Set if TLB entry is an IO callback. */ 389 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) 390 /* Set if TLB entry contains a watchpoint. */ 391 #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) 392 /* Set if TLB entry requires byte swap. */ 393 #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) 394 /* Set if TLB entry writes ignored. */ 395 #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) 396 397 /* Use this mask to check interception with an alignment mask 398 * in a TCG backend. 399 */ 400 #define TLB_FLAGS_MASK \ 401 (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ 402 | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) 403 404 /** 405 * tlb_hit_page: return true if page aligned @addr is a hit against the 406 * TLB entry @tlb_addr 407 * 408 * @addr: virtual address to test (must be page aligned) 409 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 410 */ 411 static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr) 412 { 413 return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); 414 } 415 416 /** 417 * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr 418 * 419 * @addr: virtual address to test (need not be page aligned) 420 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 421 */ 422 static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr) 423 { 424 return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); 425 } 426 427 #ifdef CONFIG_TCG 428 /* accel/tcg/translate-all.c */ 429 void dump_exec_info(GString *buf); 430 #endif /* CONFIG_TCG */ 431 432 #endif /* !CONFIG_USER_ONLY */ 433 434 /* accel/tcg/cpu-exec.c */ 435 int cpu_exec(CPUState *cpu); 436 void tcg_exec_realizefn(CPUState *cpu, Error **errp); 437 void tcg_exec_unrealizefn(CPUState *cpu); 438 439 /** 440 * cpu_set_cpustate_pointers(cpu) 441 * @cpu: The cpu object 442 * 443 * Set the generic pointers in CPUState into the outer object. 444 */ 445 static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) 446 { 447 cpu->parent_obj.env_ptr = &cpu->env; 448 cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr; 449 } 450 451 /** 452 * env_archcpu(env) 453 * @env: The architecture environment 454 * 455 * Return the ArchCPU associated with the environment. 456 */ 457 static inline ArchCPU *env_archcpu(CPUArchState *env) 458 { 459 return container_of(env, ArchCPU, env); 460 } 461 462 /** 463 * env_cpu(env) 464 * @env: The architecture environment 465 * 466 * Return the CPUState associated with the environment. 467 */ 468 static inline CPUState *env_cpu(CPUArchState *env) 469 { 470 return &env_archcpu(env)->parent_obj; 471 } 472 473 /** 474 * env_neg(env) 475 * @env: The architecture environment 476 * 477 * Return the CPUNegativeOffsetState associated with the environment. 478 */ 479 static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) 480 { 481 ArchCPU *arch_cpu = container_of(env, ArchCPU, env); 482 return &arch_cpu->neg; 483 } 484 485 /** 486 * cpu_neg(cpu) 487 * @cpu: The generic CPUState 488 * 489 * Return the CPUNegativeOffsetState associated with the cpu. 490 */ 491 static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) 492 { 493 ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj); 494 return &arch_cpu->neg; 495 } 496 497 /** 498 * env_tlb(env) 499 * @env: The architecture environment 500 * 501 * Return the CPUTLB state associated with the environment. 502 */ 503 static inline CPUTLB *env_tlb(CPUArchState *env) 504 { 505 return &env_neg(env)->tlb; 506 } 507 508 #endif /* CPU_ALL_H */ 509