1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "qemu-common.h" 23 #include "exec/cpu-common.h" 24 #include "qemu/thread.h" 25 26 /* some important defines: 27 * 28 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned 29 * memory accesses. 30 * 31 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and 32 * otherwise little endian. 33 * 34 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet)) 35 * 36 * TARGET_WORDS_BIGENDIAN : same for target cpu 37 */ 38 39 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) 40 #define BSWAP_NEEDED 41 #endif 42 43 #ifdef BSWAP_NEEDED 44 45 static inline uint16_t tswap16(uint16_t s) 46 { 47 return bswap16(s); 48 } 49 50 static inline uint32_t tswap32(uint32_t s) 51 { 52 return bswap32(s); 53 } 54 55 static inline uint64_t tswap64(uint64_t s) 56 { 57 return bswap64(s); 58 } 59 60 static inline void tswap16s(uint16_t *s) 61 { 62 *s = bswap16(*s); 63 } 64 65 static inline void tswap32s(uint32_t *s) 66 { 67 *s = bswap32(*s); 68 } 69 70 static inline void tswap64s(uint64_t *s) 71 { 72 *s = bswap64(*s); 73 } 74 75 #else 76 77 static inline uint16_t tswap16(uint16_t s) 78 { 79 return s; 80 } 81 82 static inline uint32_t tswap32(uint32_t s) 83 { 84 return s; 85 } 86 87 static inline uint64_t tswap64(uint64_t s) 88 { 89 return s; 90 } 91 92 static inline void tswap16s(uint16_t *s) 93 { 94 } 95 96 static inline void tswap32s(uint32_t *s) 97 { 98 } 99 100 static inline void tswap64s(uint64_t *s) 101 { 102 } 103 104 #endif 105 106 #if TARGET_LONG_SIZE == 4 107 #define tswapl(s) tswap32(s) 108 #define tswapls(s) tswap32s((uint32_t *)(s)) 109 #define bswaptls(s) bswap32s(s) 110 #else 111 #define tswapl(s) tswap64(s) 112 #define tswapls(s) tswap64s((uint64_t *)(s)) 113 #define bswaptls(s) bswap64s(s) 114 #endif 115 116 /* CPU memory access without any memory or io remapping */ 117 118 /* 119 * the generic syntax for the memory accesses is: 120 * 121 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr) 122 * 123 * store: st{type}{size}{endian}_{access_type}(ptr, val) 124 * 125 * type is: 126 * (empty): integer access 127 * f : float access 128 * 129 * sign is: 130 * (empty): for floats or 32 bit size 131 * u : unsigned 132 * s : signed 133 * 134 * size is: 135 * b: 8 bits 136 * w: 16 bits 137 * l: 32 bits 138 * q: 64 bits 139 * 140 * endian is: 141 * (empty): target cpu endianness or 8 bit access 142 * r : reversed target cpu endianness (not implemented yet) 143 * be : big endian (not implemented yet) 144 * le : little endian (not implemented yet) 145 * 146 * access_type is: 147 * raw : host memory access 148 * user : user mode access using soft MMU 149 * kernel : kernel mode access using soft MMU 150 */ 151 152 /* target-endianness CPU memory access functions */ 153 #if defined(TARGET_WORDS_BIGENDIAN) 154 #define lduw_p(p) lduw_be_p(p) 155 #define ldsw_p(p) ldsw_be_p(p) 156 #define ldl_p(p) ldl_be_p(p) 157 #define ldq_p(p) ldq_be_p(p) 158 #define ldfl_p(p) ldfl_be_p(p) 159 #define ldfq_p(p) ldfq_be_p(p) 160 #define stw_p(p, v) stw_be_p(p, v) 161 #define stl_p(p, v) stl_be_p(p, v) 162 #define stq_p(p, v) stq_be_p(p, v) 163 #define stfl_p(p, v) stfl_be_p(p, v) 164 #define stfq_p(p, v) stfq_be_p(p, v) 165 #else 166 #define lduw_p(p) lduw_le_p(p) 167 #define ldsw_p(p) ldsw_le_p(p) 168 #define ldl_p(p) ldl_le_p(p) 169 #define ldq_p(p) ldq_le_p(p) 170 #define ldfl_p(p) ldfl_le_p(p) 171 #define ldfq_p(p) ldfq_le_p(p) 172 #define stw_p(p, v) stw_le_p(p, v) 173 #define stl_p(p, v) stl_le_p(p, v) 174 #define stq_p(p, v) stq_le_p(p, v) 175 #define stfl_p(p, v) stfl_le_p(p, v) 176 #define stfq_p(p, v) stfq_le_p(p, v) 177 #endif 178 179 /* MMU memory access macros */ 180 181 #if defined(CONFIG_USER_ONLY) 182 #include <assert.h> 183 #include "exec/user/abitypes.h" 184 185 /* On some host systems the guest address space is reserved on the host. 186 * This allows the guest address space to be offset to a convenient location. 187 */ 188 #if defined(CONFIG_USE_GUEST_BASE) 189 extern unsigned long guest_base; 190 extern int have_guest_base; 191 extern unsigned long reserved_va; 192 #define GUEST_BASE guest_base 193 #define RESERVED_VA reserved_va 194 #else 195 #define GUEST_BASE 0ul 196 #define RESERVED_VA 0ul 197 #endif 198 199 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ 200 #define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE)) 201 202 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS 203 #define h2g_valid(x) 1 204 #else 205 #define h2g_valid(x) ({ \ 206 unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ 207 (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \ 208 (!RESERVED_VA || (__guest < RESERVED_VA)); \ 209 }) 210 #endif 211 212 #define h2g(x) ({ \ 213 unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ 214 /* Check if given address fits target address space */ \ 215 assert(h2g_valid(x)); \ 216 (abi_ulong)__ret; \ 217 }) 218 219 #define saddr(x) g2h(x) 220 #define laddr(x) g2h(x) 221 222 #else /* !CONFIG_USER_ONLY */ 223 /* NOTE: we use double casts if pointers and target_ulong have 224 different sizes */ 225 #define saddr(x) (uint8_t *)(intptr_t)(x) 226 #define laddr(x) (uint8_t *)(intptr_t)(x) 227 #endif 228 229 #define ldub_raw(p) ldub_p(laddr((p))) 230 #define ldsb_raw(p) ldsb_p(laddr((p))) 231 #define lduw_raw(p) lduw_p(laddr((p))) 232 #define ldsw_raw(p) ldsw_p(laddr((p))) 233 #define ldl_raw(p) ldl_p(laddr((p))) 234 #define ldq_raw(p) ldq_p(laddr((p))) 235 #define ldfl_raw(p) ldfl_p(laddr((p))) 236 #define ldfq_raw(p) ldfq_p(laddr((p))) 237 #define stb_raw(p, v) stb_p(saddr((p)), v) 238 #define stw_raw(p, v) stw_p(saddr((p)), v) 239 #define stl_raw(p, v) stl_p(saddr((p)), v) 240 #define stq_raw(p, v) stq_p(saddr((p)), v) 241 #define stfl_raw(p, v) stfl_p(saddr((p)), v) 242 #define stfq_raw(p, v) stfq_p(saddr((p)), v) 243 244 245 #if defined(CONFIG_USER_ONLY) 246 247 /* if user mode, no other memory access functions */ 248 #define ldub(p) ldub_raw(p) 249 #define ldsb(p) ldsb_raw(p) 250 #define lduw(p) lduw_raw(p) 251 #define ldsw(p) ldsw_raw(p) 252 #define ldl(p) ldl_raw(p) 253 #define ldq(p) ldq_raw(p) 254 #define ldfl(p) ldfl_raw(p) 255 #define ldfq(p) ldfq_raw(p) 256 #define stb(p, v) stb_raw(p, v) 257 #define stw(p, v) stw_raw(p, v) 258 #define stl(p, v) stl_raw(p, v) 259 #define stq(p, v) stq_raw(p, v) 260 #define stfl(p, v) stfl_raw(p, v) 261 #define stfq(p, v) stfq_raw(p, v) 262 263 #define cpu_ldub_code(env1, p) ldub_raw(p) 264 #define cpu_ldsb_code(env1, p) ldsb_raw(p) 265 #define cpu_lduw_code(env1, p) lduw_raw(p) 266 #define cpu_ldsw_code(env1, p) ldsw_raw(p) 267 #define cpu_ldl_code(env1, p) ldl_raw(p) 268 #define cpu_ldq_code(env1, p) ldq_raw(p) 269 270 #define cpu_ldub_data(env, addr) ldub_raw(addr) 271 #define cpu_lduw_data(env, addr) lduw_raw(addr) 272 #define cpu_ldsw_data(env, addr) ldsw_raw(addr) 273 #define cpu_ldl_data(env, addr) ldl_raw(addr) 274 #define cpu_ldq_data(env, addr) ldq_raw(addr) 275 276 #define cpu_stb_data(env, addr, data) stb_raw(addr, data) 277 #define cpu_stw_data(env, addr, data) stw_raw(addr, data) 278 #define cpu_stl_data(env, addr, data) stl_raw(addr, data) 279 #define cpu_stq_data(env, addr, data) stq_raw(addr, data) 280 281 #define cpu_ldub_kernel(env, addr) ldub_raw(addr) 282 #define cpu_lduw_kernel(env, addr) lduw_raw(addr) 283 #define cpu_ldsw_kernel(env, addr) ldsw_raw(addr) 284 #define cpu_ldl_kernel(env, addr) ldl_raw(addr) 285 #define cpu_ldq_kernel(env, addr) ldq_raw(addr) 286 287 #define cpu_stb_kernel(env, addr, data) stb_raw(addr, data) 288 #define cpu_stw_kernel(env, addr, data) stw_raw(addr, data) 289 #define cpu_stl_kernel(env, addr, data) stl_raw(addr, data) 290 #define cpu_stq_kernel(env, addr, data) stq_raw(addr, data) 291 292 #define ldub_kernel(p) ldub_raw(p) 293 #define ldsb_kernel(p) ldsb_raw(p) 294 #define lduw_kernel(p) lduw_raw(p) 295 #define ldsw_kernel(p) ldsw_raw(p) 296 #define ldl_kernel(p) ldl_raw(p) 297 #define ldq_kernel(p) ldq_raw(p) 298 #define ldfl_kernel(p) ldfl_raw(p) 299 #define ldfq_kernel(p) ldfq_raw(p) 300 #define stb_kernel(p, v) stb_raw(p, v) 301 #define stw_kernel(p, v) stw_raw(p, v) 302 #define stl_kernel(p, v) stl_raw(p, v) 303 #define stq_kernel(p, v) stq_raw(p, v) 304 #define stfl_kernel(p, v) stfl_raw(p, v) 305 #define stfq_kernel(p, vt) stfq_raw(p, v) 306 307 #define cpu_ldub_data(env, addr) ldub_raw(addr) 308 #define cpu_lduw_data(env, addr) lduw_raw(addr) 309 #define cpu_ldl_data(env, addr) ldl_raw(addr) 310 311 #define cpu_stb_data(env, addr, data) stb_raw(addr, data) 312 #define cpu_stw_data(env, addr, data) stw_raw(addr, data) 313 #define cpu_stl_data(env, addr, data) stl_raw(addr, data) 314 #endif /* defined(CONFIG_USER_ONLY) */ 315 316 /* page related stuff */ 317 318 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 319 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) 320 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) 321 322 /* ??? These should be the larger of uintptr_t and target_ulong. */ 323 extern uintptr_t qemu_real_host_page_size; 324 extern uintptr_t qemu_host_page_size; 325 extern uintptr_t qemu_host_page_mask; 326 327 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) 328 329 /* same as PROT_xxx */ 330 #define PAGE_READ 0x0001 331 #define PAGE_WRITE 0x0002 332 #define PAGE_EXEC 0x0004 333 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 334 #define PAGE_VALID 0x0008 335 /* original state of the write flag (used when tracking self-modifying 336 code */ 337 #define PAGE_WRITE_ORG 0x0010 338 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 339 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 340 #define PAGE_RESERVED 0x0020 341 #endif 342 343 #if defined(CONFIG_USER_ONLY) 344 void page_dump(FILE *f); 345 346 typedef int (*walk_memory_regions_fn)(void *, abi_ulong, 347 abi_ulong, unsigned long); 348 int walk_memory_regions(void *, walk_memory_regions_fn); 349 350 int page_get_flags(target_ulong address); 351 void page_set_flags(target_ulong start, target_ulong end, int flags); 352 int page_check_range(target_ulong start, target_ulong len, int flags); 353 #endif 354 355 CPUArchState *cpu_copy(CPUArchState *env); 356 357 void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) 358 GCC_FMT_ATTR(2, 3); 359 360 /* Flags for use in ENV->INTERRUPT_PENDING. 361 362 The numbers assigned here are non-sequential in order to preserve 363 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 364 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 365 the vmstate dump. */ 366 367 /* External hardware interrupt pending. This is typically used for 368 interrupts from devices. */ 369 #define CPU_INTERRUPT_HARD 0x0002 370 371 /* Exit the current TB. This is typically used when some system-level device 372 makes some change to the memory mapping. E.g. the a20 line change. */ 373 #define CPU_INTERRUPT_EXITTB 0x0004 374 375 /* Halt the CPU. */ 376 #define CPU_INTERRUPT_HALT 0x0020 377 378 /* Debug event pending. */ 379 #define CPU_INTERRUPT_DEBUG 0x0080 380 381 /* Several target-specific external hardware interrupts. Each target/cpu.h 382 should define proper names based on these defines. */ 383 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 384 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 385 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 386 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 387 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 388 389 /* Several target-specific internal interrupts. These differ from the 390 preceding target-specific interrupts in that they are intended to 391 originate from within the cpu itself, typically in response to some 392 instruction being executed. These, therefore, are not masked while 393 single-stepping within the debugger. */ 394 #define CPU_INTERRUPT_TGT_INT_0 0x0100 395 #define CPU_INTERRUPT_TGT_INT_1 0x0400 396 #define CPU_INTERRUPT_TGT_INT_2 0x0800 397 #define CPU_INTERRUPT_TGT_INT_3 0x2000 398 399 /* First unused bit: 0x4000. */ 400 401 /* The set of all bits that should be masked when single-stepping. */ 402 #define CPU_INTERRUPT_SSTEP_MASK \ 403 (CPU_INTERRUPT_HARD \ 404 | CPU_INTERRUPT_TGT_EXT_0 \ 405 | CPU_INTERRUPT_TGT_EXT_1 \ 406 | CPU_INTERRUPT_TGT_EXT_2 \ 407 | CPU_INTERRUPT_TGT_EXT_3 \ 408 | CPU_INTERRUPT_TGT_EXT_4) 409 410 /* Breakpoint/watchpoint flags */ 411 #define BP_MEM_READ 0x01 412 #define BP_MEM_WRITE 0x02 413 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) 414 #define BP_STOP_BEFORE_ACCESS 0x04 415 #define BP_WATCHPOINT_HIT 0x08 416 #define BP_GDB 0x10 417 #define BP_CPU 0x20 418 419 int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, 420 CPUBreakpoint **breakpoint); 421 int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); 422 void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint); 423 void cpu_breakpoint_remove_all(CPUArchState *env, int mask); 424 int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, 425 int flags, CPUWatchpoint **watchpoint); 426 int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, 427 target_ulong len, int flags); 428 void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint); 429 void cpu_watchpoint_remove_all(CPUArchState *env, int mask); 430 431 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ 432 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ 433 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ 434 435 void cpu_single_step(CPUArchState *env, int enabled); 436 437 #if !defined(CONFIG_USER_ONLY) 438 439 /* Return the physical page corresponding to a virtual one. Use it 440 only for debugging because no protection checks are done. Return -1 441 if no page found. */ 442 hwaddr cpu_get_phys_page_debug(CPUArchState *env, target_ulong addr); 443 444 /* memory API */ 445 446 extern ram_addr_t ram_size; 447 448 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ 449 #define RAM_PREALLOC_MASK (1 << 0) 450 451 typedef struct RAMBlock { 452 struct MemoryRegion *mr; 453 uint8_t *host; 454 ram_addr_t offset; 455 ram_addr_t length; 456 uint32_t flags; 457 char idstr[256]; 458 /* Reads can take either the iothread or the ramlist lock. 459 * Writes must take both locks. 460 */ 461 QTAILQ_ENTRY(RAMBlock) next; 462 #if defined(__linux__) && !defined(TARGET_S390X) 463 int fd; 464 #endif 465 } RAMBlock; 466 467 typedef struct RAMList { 468 QemuMutex mutex; 469 /* Protected by the iothread lock. */ 470 uint8_t *phys_dirty; 471 RAMBlock *mru_block; 472 /* Protected by the ramlist lock. */ 473 QTAILQ_HEAD(, RAMBlock) blocks; 474 uint32_t version; 475 } RAMList; 476 extern RAMList ram_list; 477 478 extern const char *mem_path; 479 extern int mem_prealloc; 480 481 /* Flags stored in the low bits of the TLB virtual address. These are 482 defined so that fast path ram access is all zeros. */ 483 /* Zero if TLB entry is valid. */ 484 #define TLB_INVALID_MASK (1 << 3) 485 /* Set if TLB entry references a clean RAM page. The iotlb entry will 486 contain the page physical address. */ 487 #define TLB_NOTDIRTY (1 << 4) 488 /* Set if TLB entry is an IO callback. */ 489 #define TLB_MMIO (1 << 5) 490 491 void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); 492 ram_addr_t last_ram_offset(void); 493 void qemu_mutex_lock_ramlist(void); 494 void qemu_mutex_unlock_ramlist(void); 495 #endif /* !CONFIG_USER_ONLY */ 496 497 int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr, 498 uint8_t *buf, int len, int is_write); 499 500 #endif /* CPU_ALL_H */ 501