1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "exec/cpu-common.h" 23 #include "exec/memory.h" 24 #include "exec/tswap.h" 25 #include "qemu/thread.h" 26 #include "hw/core/cpu.h" 27 #include "qemu/rcu.h" 28 29 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 30 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 31 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 32 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 33 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 34 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 35 36 /* some important defines: 37 * 38 * HOST_BIG_ENDIAN : whether the host cpu is big endian and 39 * otherwise little endian. 40 * 41 * TARGET_BIG_ENDIAN : same for the target cpu 42 */ 43 44 #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN 45 #define BSWAP_NEEDED 46 #endif 47 48 #if TARGET_LONG_SIZE == 4 49 #define tswapl(s) tswap32(s) 50 #define tswapls(s) tswap32s((uint32_t *)(s)) 51 #define bswaptls(s) bswap32s(s) 52 #else 53 #define tswapl(s) tswap64(s) 54 #define tswapls(s) tswap64s((uint64_t *)(s)) 55 #define bswaptls(s) bswap64s(s) 56 #endif 57 58 /* Target-endianness CPU memory access functions. These fit into the 59 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. 60 */ 61 #if TARGET_BIG_ENDIAN 62 #define lduw_p(p) lduw_be_p(p) 63 #define ldsw_p(p) ldsw_be_p(p) 64 #define ldl_p(p) ldl_be_p(p) 65 #define ldq_p(p) ldq_be_p(p) 66 #define stw_p(p, v) stw_be_p(p, v) 67 #define stl_p(p, v) stl_be_p(p, v) 68 #define stq_p(p, v) stq_be_p(p, v) 69 #define ldn_p(p, sz) ldn_be_p(p, sz) 70 #define stn_p(p, sz, v) stn_be_p(p, sz, v) 71 #else 72 #define lduw_p(p) lduw_le_p(p) 73 #define ldsw_p(p) ldsw_le_p(p) 74 #define ldl_p(p) ldl_le_p(p) 75 #define ldq_p(p) ldq_le_p(p) 76 #define stw_p(p, v) stw_le_p(p, v) 77 #define stl_p(p, v) stl_le_p(p, v) 78 #define stq_p(p, v) stq_le_p(p, v) 79 #define ldn_p(p, sz) ldn_le_p(p, sz) 80 #define stn_p(p, sz, v) stn_le_p(p, sz, v) 81 #endif 82 83 /* MMU memory access macros */ 84 85 #if defined(CONFIG_USER_ONLY) 86 #include "exec/user/abitypes.h" 87 88 /* On some host systems the guest address space is reserved on the host. 89 * This allows the guest address space to be offset to a convenient location. 90 */ 91 extern uintptr_t guest_base; 92 extern bool have_guest_base; 93 94 /* 95 * If non-zero, the guest virtual address space is a contiguous subset 96 * of the host virtual address space, i.e. '-R reserved_va' is in effect 97 * either from the command-line or by default. The value is the last 98 * byte of the guest address space e.g. UINT32_MAX. 99 * 100 * If zero, the host and guest virtual address spaces are intermingled. 101 */ 102 extern unsigned long reserved_va; 103 104 /* 105 * Limit the guest addresses as best we can. 106 * 107 * When not using -R reserved_va, we cannot really limit the guest 108 * to less address space than the host. For 32-bit guests, this 109 * acts as a sanity check that we're not giving the guest an address 110 * that it cannot even represent. For 64-bit guests... the address 111 * might not be what the real kernel would give, but it is at least 112 * representable in the guest. 113 * 114 * TODO: Improve address allocation to avoid this problem, and to 115 * avoid setting bits at the top of guest addresses that might need 116 * to be used for tags. 117 */ 118 #define GUEST_ADDR_MAX_ \ 119 ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \ 120 UINT32_MAX : ~0ul) 121 #define GUEST_ADDR_MAX (reserved_va ? : GUEST_ADDR_MAX_) 122 123 #else 124 125 #include "exec/hwaddr.h" 126 127 #define SUFFIX 128 #define ARG1 as 129 #define ARG1_DECL AddressSpace *as 130 #define TARGET_ENDIANNESS 131 #include "exec/memory_ldst.h.inc" 132 133 #define SUFFIX _cached_slow 134 #define ARG1 cache 135 #define ARG1_DECL MemoryRegionCache *cache 136 #define TARGET_ENDIANNESS 137 #include "exec/memory_ldst.h.inc" 138 139 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) 140 { 141 address_space_stl_notdirty(as, addr, val, 142 MEMTXATTRS_UNSPECIFIED, NULL); 143 } 144 145 #define SUFFIX 146 #define ARG1 as 147 #define ARG1_DECL AddressSpace *as 148 #define TARGET_ENDIANNESS 149 #include "exec/memory_ldst_phys.h.inc" 150 151 /* Inline fast path for direct RAM access. */ 152 #define ENDIANNESS 153 #include "exec/memory_ldst_cached.h.inc" 154 155 #define SUFFIX _cached 156 #define ARG1 cache 157 #define ARG1_DECL MemoryRegionCache *cache 158 #define TARGET_ENDIANNESS 159 #include "exec/memory_ldst_phys.h.inc" 160 #endif 161 162 /* page related stuff */ 163 164 #ifdef TARGET_PAGE_BITS_VARY 165 # include "exec/page-vary.h" 166 extern const TargetPageBits target_page; 167 #ifdef CONFIG_DEBUG_TCG 168 #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; }) 169 #define TARGET_PAGE_MASK ({ assert(target_page.decided); \ 170 (target_long)target_page.mask; }) 171 #else 172 #define TARGET_PAGE_BITS target_page.bits 173 #define TARGET_PAGE_MASK ((target_long)target_page.mask) 174 #endif 175 #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) 176 #else 177 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS 178 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 179 #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) 180 #endif 181 182 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) 183 184 /* same as PROT_xxx */ 185 #define PAGE_READ 0x0001 186 #define PAGE_WRITE 0x0002 187 #define PAGE_EXEC 0x0004 188 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 189 #define PAGE_VALID 0x0008 190 /* 191 * Original state of the write flag (used when tracking self-modifying code) 192 */ 193 #define PAGE_WRITE_ORG 0x0010 194 /* 195 * Invalidate the TLB entry immediately, helpful for s390x 196 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() 197 */ 198 #define PAGE_WRITE_INV 0x0020 199 /* For use with page_set_flags: page is being replaced; target_data cleared. */ 200 #define PAGE_RESET 0x0040 201 /* For linux-user, indicates that the page is MAP_ANON. */ 202 #define PAGE_ANON 0x0080 203 204 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 205 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 206 #define PAGE_RESERVED 0x0100 207 #endif 208 /* Target-specific bits that will be used via page_get_flags(). */ 209 #define PAGE_TARGET_1 0x0200 210 #define PAGE_TARGET_2 0x0400 211 212 /* 213 * For linux-user, indicates that the page is mapped with the same semantics 214 * in both guest and host. 215 */ 216 #define PAGE_PASSTHROUGH 0x0800 217 218 #if defined(CONFIG_USER_ONLY) 219 void page_dump(FILE *f); 220 221 typedef int (*walk_memory_regions_fn)(void *, target_ulong, 222 target_ulong, unsigned long); 223 int walk_memory_regions(void *, walk_memory_regions_fn); 224 225 int page_get_flags(target_ulong address); 226 void page_set_flags(target_ulong start, target_ulong last, int flags); 227 void page_reset_target_data(target_ulong start, target_ulong last); 228 int page_check_range(target_ulong start, target_ulong len, int flags); 229 230 /** 231 * page_get_target_data(address) 232 * @address: guest virtual address 233 * 234 * Return TARGET_PAGE_DATA_SIZE bytes of out-of-band data to associate 235 * with the guest page at @address, allocating it if necessary. The 236 * caller should already have verified that the address is valid. 237 * 238 * The memory will be freed when the guest page is deallocated, 239 * e.g. with the munmap system call. 240 */ 241 void *page_get_target_data(target_ulong address) 242 __attribute__((returns_nonnull)); 243 #endif 244 245 CPUArchState *cpu_copy(CPUArchState *env); 246 247 /* Flags for use in ENV->INTERRUPT_PENDING. 248 249 The numbers assigned here are non-sequential in order to preserve 250 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 251 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 252 the vmstate dump. */ 253 254 /* External hardware interrupt pending. This is typically used for 255 interrupts from devices. */ 256 #define CPU_INTERRUPT_HARD 0x0002 257 258 /* Exit the current TB. This is typically used when some system-level device 259 makes some change to the memory mapping. E.g. the a20 line change. */ 260 #define CPU_INTERRUPT_EXITTB 0x0004 261 262 /* Halt the CPU. */ 263 #define CPU_INTERRUPT_HALT 0x0020 264 265 /* Debug event pending. */ 266 #define CPU_INTERRUPT_DEBUG 0x0080 267 268 /* Reset signal. */ 269 #define CPU_INTERRUPT_RESET 0x0400 270 271 /* Several target-specific external hardware interrupts. Each target/cpu.h 272 should define proper names based on these defines. */ 273 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 274 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 275 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 276 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 277 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 278 279 /* Several target-specific internal interrupts. These differ from the 280 preceding target-specific interrupts in that they are intended to 281 originate from within the cpu itself, typically in response to some 282 instruction being executed. These, therefore, are not masked while 283 single-stepping within the debugger. */ 284 #define CPU_INTERRUPT_TGT_INT_0 0x0100 285 #define CPU_INTERRUPT_TGT_INT_1 0x0800 286 #define CPU_INTERRUPT_TGT_INT_2 0x2000 287 288 /* First unused bit: 0x4000. */ 289 290 /* The set of all bits that should be masked when single-stepping. */ 291 #define CPU_INTERRUPT_SSTEP_MASK \ 292 (CPU_INTERRUPT_HARD \ 293 | CPU_INTERRUPT_TGT_EXT_0 \ 294 | CPU_INTERRUPT_TGT_EXT_1 \ 295 | CPU_INTERRUPT_TGT_EXT_2 \ 296 | CPU_INTERRUPT_TGT_EXT_3 \ 297 | CPU_INTERRUPT_TGT_EXT_4) 298 299 #ifdef CONFIG_USER_ONLY 300 301 /* 302 * Allow some level of source compatibility with softmmu. We do not 303 * support any of the more exotic features, so only invalid pages may 304 * be signaled by probe_access_flags(). 305 */ 306 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 307 #define TLB_MMIO 0 308 #define TLB_WATCHPOINT 0 309 310 #else 311 312 /* 313 * Flags stored in the low bits of the TLB virtual address. 314 * These are defined so that fast path ram access is all zeros. 315 * The flags all must be between TARGET_PAGE_BITS and 316 * maximum address alignment bit. 317 * 318 * Use TARGET_PAGE_BITS_MIN so that these bits are constant 319 * when TARGET_PAGE_BITS_VARY is in effect. 320 */ 321 /* Zero if TLB entry is valid. */ 322 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 323 /* Set if TLB entry references a clean RAM page. The iotlb entry will 324 contain the page physical address. */ 325 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) 326 /* Set if TLB entry is an IO callback. */ 327 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) 328 /* Set if TLB entry contains a watchpoint. */ 329 #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) 330 /* Set if TLB entry requires byte swap. */ 331 #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) 332 /* Set if TLB entry writes ignored. */ 333 #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) 334 335 /* Use this mask to check interception with an alignment mask 336 * in a TCG backend. 337 */ 338 #define TLB_FLAGS_MASK \ 339 (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ 340 | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) 341 342 /** 343 * tlb_hit_page: return true if page aligned @addr is a hit against the 344 * TLB entry @tlb_addr 345 * 346 * @addr: virtual address to test (must be page aligned) 347 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 348 */ 349 static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr) 350 { 351 return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); 352 } 353 354 /** 355 * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr 356 * 357 * @addr: virtual address to test (need not be page aligned) 358 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 359 */ 360 static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr) 361 { 362 return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); 363 } 364 365 #ifdef CONFIG_TCG 366 /* accel/tcg/translate-all.c */ 367 void dump_exec_info(GString *buf); 368 #endif /* CONFIG_TCG */ 369 370 #endif /* !CONFIG_USER_ONLY */ 371 372 /* accel/tcg/cpu-exec.c */ 373 int cpu_exec(CPUState *cpu); 374 void tcg_exec_realizefn(CPUState *cpu, Error **errp); 375 void tcg_exec_unrealizefn(CPUState *cpu); 376 377 /** 378 * cpu_set_cpustate_pointers(cpu) 379 * @cpu: The cpu object 380 * 381 * Set the generic pointers in CPUState into the outer object. 382 */ 383 static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) 384 { 385 cpu->parent_obj.env_ptr = &cpu->env; 386 cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr; 387 } 388 389 /** 390 * env_archcpu(env) 391 * @env: The architecture environment 392 * 393 * Return the ArchCPU associated with the environment. 394 */ 395 static inline ArchCPU *env_archcpu(CPUArchState *env) 396 { 397 return container_of(env, ArchCPU, env); 398 } 399 400 /** 401 * env_cpu(env) 402 * @env: The architecture environment 403 * 404 * Return the CPUState associated with the environment. 405 */ 406 static inline CPUState *env_cpu(CPUArchState *env) 407 { 408 return &env_archcpu(env)->parent_obj; 409 } 410 411 /** 412 * env_neg(env) 413 * @env: The architecture environment 414 * 415 * Return the CPUNegativeOffsetState associated with the environment. 416 */ 417 static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) 418 { 419 ArchCPU *arch_cpu = container_of(env, ArchCPU, env); 420 return &arch_cpu->neg; 421 } 422 423 /** 424 * cpu_neg(cpu) 425 * @cpu: The generic CPUState 426 * 427 * Return the CPUNegativeOffsetState associated with the cpu. 428 */ 429 static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) 430 { 431 ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj); 432 return &arch_cpu->neg; 433 } 434 435 /** 436 * env_tlb(env) 437 * @env: The architecture environment 438 * 439 * Return the CPUTLB state associated with the environment. 440 */ 441 static inline CPUTLB *env_tlb(CPUArchState *env) 442 { 443 return &env_neg(env)->tlb; 444 } 445 446 #endif /* CPU_ALL_H */ 447