1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "qemu-common.h" 23 #include "exec/cpu-common.h" 24 #include "qemu/thread.h" 25 #include "qom/cpu.h" 26 27 /* some important defines: 28 * 29 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned 30 * memory accesses. 31 * 32 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and 33 * otherwise little endian. 34 * 35 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet)) 36 * 37 * TARGET_WORDS_BIGENDIAN : same for target cpu 38 */ 39 40 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) 41 #define BSWAP_NEEDED 42 #endif 43 44 #ifdef BSWAP_NEEDED 45 46 static inline uint16_t tswap16(uint16_t s) 47 { 48 return bswap16(s); 49 } 50 51 static inline uint32_t tswap32(uint32_t s) 52 { 53 return bswap32(s); 54 } 55 56 static inline uint64_t tswap64(uint64_t s) 57 { 58 return bswap64(s); 59 } 60 61 static inline void tswap16s(uint16_t *s) 62 { 63 *s = bswap16(*s); 64 } 65 66 static inline void tswap32s(uint32_t *s) 67 { 68 *s = bswap32(*s); 69 } 70 71 static inline void tswap64s(uint64_t *s) 72 { 73 *s = bswap64(*s); 74 } 75 76 #else 77 78 static inline uint16_t tswap16(uint16_t s) 79 { 80 return s; 81 } 82 83 static inline uint32_t tswap32(uint32_t s) 84 { 85 return s; 86 } 87 88 static inline uint64_t tswap64(uint64_t s) 89 { 90 return s; 91 } 92 93 static inline void tswap16s(uint16_t *s) 94 { 95 } 96 97 static inline void tswap32s(uint32_t *s) 98 { 99 } 100 101 static inline void tswap64s(uint64_t *s) 102 { 103 } 104 105 #endif 106 107 #if TARGET_LONG_SIZE == 4 108 #define tswapl(s) tswap32(s) 109 #define tswapls(s) tswap32s((uint32_t *)(s)) 110 #define bswaptls(s) bswap32s(s) 111 #else 112 #define tswapl(s) tswap64(s) 113 #define tswapls(s) tswap64s((uint64_t *)(s)) 114 #define bswaptls(s) bswap64s(s) 115 #endif 116 117 /* CPU memory access without any memory or io remapping */ 118 119 /* 120 * the generic syntax for the memory accesses is: 121 * 122 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr) 123 * 124 * store: st{type}{size}{endian}_{access_type}(ptr, val) 125 * 126 * type is: 127 * (empty): integer access 128 * f : float access 129 * 130 * sign is: 131 * (empty): for floats or 32 bit size 132 * u : unsigned 133 * s : signed 134 * 135 * size is: 136 * b: 8 bits 137 * w: 16 bits 138 * l: 32 bits 139 * q: 64 bits 140 * 141 * endian is: 142 * (empty): target cpu endianness or 8 bit access 143 * r : reversed target cpu endianness (not implemented yet) 144 * be : big endian (not implemented yet) 145 * le : little endian (not implemented yet) 146 * 147 * access_type is: 148 * raw : host memory access 149 * user : user mode access using soft MMU 150 * kernel : kernel mode access using soft MMU 151 */ 152 153 /* target-endianness CPU memory access functions */ 154 #if defined(TARGET_WORDS_BIGENDIAN) 155 #define lduw_p(p) lduw_be_p(p) 156 #define ldsw_p(p) ldsw_be_p(p) 157 #define ldl_p(p) ldl_be_p(p) 158 #define ldq_p(p) ldq_be_p(p) 159 #define ldfl_p(p) ldfl_be_p(p) 160 #define ldfq_p(p) ldfq_be_p(p) 161 #define stw_p(p, v) stw_be_p(p, v) 162 #define stl_p(p, v) stl_be_p(p, v) 163 #define stq_p(p, v) stq_be_p(p, v) 164 #define stfl_p(p, v) stfl_be_p(p, v) 165 #define stfq_p(p, v) stfq_be_p(p, v) 166 #else 167 #define lduw_p(p) lduw_le_p(p) 168 #define ldsw_p(p) ldsw_le_p(p) 169 #define ldl_p(p) ldl_le_p(p) 170 #define ldq_p(p) ldq_le_p(p) 171 #define ldfl_p(p) ldfl_le_p(p) 172 #define ldfq_p(p) ldfq_le_p(p) 173 #define stw_p(p, v) stw_le_p(p, v) 174 #define stl_p(p, v) stl_le_p(p, v) 175 #define stq_p(p, v) stq_le_p(p, v) 176 #define stfl_p(p, v) stfl_le_p(p, v) 177 #define stfq_p(p, v) stfq_le_p(p, v) 178 #endif 179 180 /* MMU memory access macros */ 181 182 #if defined(CONFIG_USER_ONLY) 183 #include <assert.h> 184 #include "exec/user/abitypes.h" 185 186 /* On some host systems the guest address space is reserved on the host. 187 * This allows the guest address space to be offset to a convenient location. 188 */ 189 #if defined(CONFIG_USE_GUEST_BASE) 190 extern unsigned long guest_base; 191 extern int have_guest_base; 192 extern unsigned long reserved_va; 193 #define GUEST_BASE guest_base 194 #define RESERVED_VA reserved_va 195 #else 196 #define GUEST_BASE 0ul 197 #define RESERVED_VA 0ul 198 #endif 199 200 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ 201 #define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE)) 202 203 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS 204 #define h2g_valid(x) 1 205 #else 206 #define h2g_valid(x) ({ \ 207 unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ 208 (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \ 209 (!RESERVED_VA || (__guest < RESERVED_VA)); \ 210 }) 211 #endif 212 213 #define h2g(x) ({ \ 214 unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ 215 /* Check if given address fits target address space */ \ 216 assert(h2g_valid(x)); \ 217 (abi_ulong)__ret; \ 218 }) 219 220 #define saddr(x) g2h(x) 221 #define laddr(x) g2h(x) 222 223 #else /* !CONFIG_USER_ONLY */ 224 /* NOTE: we use double casts if pointers and target_ulong have 225 different sizes */ 226 #define saddr(x) (uint8_t *)(intptr_t)(x) 227 #define laddr(x) (uint8_t *)(intptr_t)(x) 228 #endif 229 230 #define ldub_raw(p) ldub_p(laddr((p))) 231 #define ldsb_raw(p) ldsb_p(laddr((p))) 232 #define lduw_raw(p) lduw_p(laddr((p))) 233 #define ldsw_raw(p) ldsw_p(laddr((p))) 234 #define ldl_raw(p) ldl_p(laddr((p))) 235 #define ldq_raw(p) ldq_p(laddr((p))) 236 #define ldfl_raw(p) ldfl_p(laddr((p))) 237 #define ldfq_raw(p) ldfq_p(laddr((p))) 238 #define stb_raw(p, v) stb_p(saddr((p)), v) 239 #define stw_raw(p, v) stw_p(saddr((p)), v) 240 #define stl_raw(p, v) stl_p(saddr((p)), v) 241 #define stq_raw(p, v) stq_p(saddr((p)), v) 242 #define stfl_raw(p, v) stfl_p(saddr((p)), v) 243 #define stfq_raw(p, v) stfq_p(saddr((p)), v) 244 245 246 #if defined(CONFIG_USER_ONLY) 247 248 /* if user mode, no other memory access functions */ 249 #define ldub(p) ldub_raw(p) 250 #define ldsb(p) ldsb_raw(p) 251 #define lduw(p) lduw_raw(p) 252 #define ldsw(p) ldsw_raw(p) 253 #define ldl(p) ldl_raw(p) 254 #define ldq(p) ldq_raw(p) 255 #define ldfl(p) ldfl_raw(p) 256 #define ldfq(p) ldfq_raw(p) 257 #define stb(p, v) stb_raw(p, v) 258 #define stw(p, v) stw_raw(p, v) 259 #define stl(p, v) stl_raw(p, v) 260 #define stq(p, v) stq_raw(p, v) 261 #define stfl(p, v) stfl_raw(p, v) 262 #define stfq(p, v) stfq_raw(p, v) 263 264 #define cpu_ldub_code(env1, p) ldub_raw(p) 265 #define cpu_ldsb_code(env1, p) ldsb_raw(p) 266 #define cpu_lduw_code(env1, p) lduw_raw(p) 267 #define cpu_ldsw_code(env1, p) ldsw_raw(p) 268 #define cpu_ldl_code(env1, p) ldl_raw(p) 269 #define cpu_ldq_code(env1, p) ldq_raw(p) 270 271 #define cpu_ldub_data(env, addr) ldub_raw(addr) 272 #define cpu_lduw_data(env, addr) lduw_raw(addr) 273 #define cpu_ldsw_data(env, addr) ldsw_raw(addr) 274 #define cpu_ldl_data(env, addr) ldl_raw(addr) 275 #define cpu_ldq_data(env, addr) ldq_raw(addr) 276 277 #define cpu_stb_data(env, addr, data) stb_raw(addr, data) 278 #define cpu_stw_data(env, addr, data) stw_raw(addr, data) 279 #define cpu_stl_data(env, addr, data) stl_raw(addr, data) 280 #define cpu_stq_data(env, addr, data) stq_raw(addr, data) 281 282 #define cpu_ldub_kernel(env, addr) ldub_raw(addr) 283 #define cpu_lduw_kernel(env, addr) lduw_raw(addr) 284 #define cpu_ldsw_kernel(env, addr) ldsw_raw(addr) 285 #define cpu_ldl_kernel(env, addr) ldl_raw(addr) 286 #define cpu_ldq_kernel(env, addr) ldq_raw(addr) 287 288 #define cpu_stb_kernel(env, addr, data) stb_raw(addr, data) 289 #define cpu_stw_kernel(env, addr, data) stw_raw(addr, data) 290 #define cpu_stl_kernel(env, addr, data) stl_raw(addr, data) 291 #define cpu_stq_kernel(env, addr, data) stq_raw(addr, data) 292 293 #define ldub_kernel(p) ldub_raw(p) 294 #define ldsb_kernel(p) ldsb_raw(p) 295 #define lduw_kernel(p) lduw_raw(p) 296 #define ldsw_kernel(p) ldsw_raw(p) 297 #define ldl_kernel(p) ldl_raw(p) 298 #define ldq_kernel(p) ldq_raw(p) 299 #define ldfl_kernel(p) ldfl_raw(p) 300 #define ldfq_kernel(p) ldfq_raw(p) 301 #define stb_kernel(p, v) stb_raw(p, v) 302 #define stw_kernel(p, v) stw_raw(p, v) 303 #define stl_kernel(p, v) stl_raw(p, v) 304 #define stq_kernel(p, v) stq_raw(p, v) 305 #define stfl_kernel(p, v) stfl_raw(p, v) 306 #define stfq_kernel(p, vt) stfq_raw(p, v) 307 308 #define cpu_ldub_data(env, addr) ldub_raw(addr) 309 #define cpu_lduw_data(env, addr) lduw_raw(addr) 310 #define cpu_ldl_data(env, addr) ldl_raw(addr) 311 312 #define cpu_stb_data(env, addr, data) stb_raw(addr, data) 313 #define cpu_stw_data(env, addr, data) stw_raw(addr, data) 314 #define cpu_stl_data(env, addr, data) stl_raw(addr, data) 315 #endif /* defined(CONFIG_USER_ONLY) */ 316 317 /* page related stuff */ 318 319 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 320 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) 321 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) 322 323 /* ??? These should be the larger of uintptr_t and target_ulong. */ 324 extern uintptr_t qemu_real_host_page_size; 325 extern uintptr_t qemu_host_page_size; 326 extern uintptr_t qemu_host_page_mask; 327 328 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) 329 330 /* same as PROT_xxx */ 331 #define PAGE_READ 0x0001 332 #define PAGE_WRITE 0x0002 333 #define PAGE_EXEC 0x0004 334 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 335 #define PAGE_VALID 0x0008 336 /* original state of the write flag (used when tracking self-modifying 337 code */ 338 #define PAGE_WRITE_ORG 0x0010 339 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 340 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 341 #define PAGE_RESERVED 0x0020 342 #endif 343 344 #if defined(CONFIG_USER_ONLY) 345 void page_dump(FILE *f); 346 347 typedef int (*walk_memory_regions_fn)(void *, abi_ulong, 348 abi_ulong, unsigned long); 349 int walk_memory_regions(void *, walk_memory_regions_fn); 350 351 int page_get_flags(target_ulong address); 352 void page_set_flags(target_ulong start, target_ulong end, int flags); 353 int page_check_range(target_ulong start, target_ulong len, int flags); 354 #endif 355 356 CPUArchState *cpu_copy(CPUArchState *env); 357 358 void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) 359 GCC_FMT_ATTR(2, 3); 360 361 /* Flags for use in ENV->INTERRUPT_PENDING. 362 363 The numbers assigned here are non-sequential in order to preserve 364 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 365 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 366 the vmstate dump. */ 367 368 /* External hardware interrupt pending. This is typically used for 369 interrupts from devices. */ 370 #define CPU_INTERRUPT_HARD 0x0002 371 372 /* Exit the current TB. This is typically used when some system-level device 373 makes some change to the memory mapping. E.g. the a20 line change. */ 374 #define CPU_INTERRUPT_EXITTB 0x0004 375 376 /* Halt the CPU. */ 377 #define CPU_INTERRUPT_HALT 0x0020 378 379 /* Debug event pending. */ 380 #define CPU_INTERRUPT_DEBUG 0x0080 381 382 /* Several target-specific external hardware interrupts. Each target/cpu.h 383 should define proper names based on these defines. */ 384 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 385 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 386 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 387 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 388 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 389 390 /* Several target-specific internal interrupts. These differ from the 391 preceding target-specific interrupts in that they are intended to 392 originate from within the cpu itself, typically in response to some 393 instruction being executed. These, therefore, are not masked while 394 single-stepping within the debugger. */ 395 #define CPU_INTERRUPT_TGT_INT_0 0x0100 396 #define CPU_INTERRUPT_TGT_INT_1 0x0400 397 #define CPU_INTERRUPT_TGT_INT_2 0x0800 398 #define CPU_INTERRUPT_TGT_INT_3 0x2000 399 400 /* First unused bit: 0x4000. */ 401 402 /* The set of all bits that should be masked when single-stepping. */ 403 #define CPU_INTERRUPT_SSTEP_MASK \ 404 (CPU_INTERRUPT_HARD \ 405 | CPU_INTERRUPT_TGT_EXT_0 \ 406 | CPU_INTERRUPT_TGT_EXT_1 \ 407 | CPU_INTERRUPT_TGT_EXT_2 \ 408 | CPU_INTERRUPT_TGT_EXT_3 \ 409 | CPU_INTERRUPT_TGT_EXT_4) 410 411 /* Breakpoint/watchpoint flags */ 412 #define BP_MEM_READ 0x01 413 #define BP_MEM_WRITE 0x02 414 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) 415 #define BP_STOP_BEFORE_ACCESS 0x04 416 #define BP_WATCHPOINT_HIT 0x08 417 #define BP_GDB 0x10 418 #define BP_CPU 0x20 419 420 int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, 421 CPUBreakpoint **breakpoint); 422 int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); 423 void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint); 424 void cpu_breakpoint_remove_all(CPUArchState *env, int mask); 425 int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, 426 int flags, CPUWatchpoint **watchpoint); 427 int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, 428 target_ulong len, int flags); 429 void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint); 430 void cpu_watchpoint_remove_all(CPUArchState *env, int mask); 431 432 #if !defined(CONFIG_USER_ONLY) 433 434 /* memory API */ 435 436 extern ram_addr_t ram_size; 437 438 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ 439 #define RAM_PREALLOC_MASK (1 << 0) 440 441 typedef struct RAMBlock { 442 struct MemoryRegion *mr; 443 uint8_t *host; 444 ram_addr_t offset; 445 ram_addr_t length; 446 uint32_t flags; 447 char idstr[256]; 448 /* Reads can take either the iothread or the ramlist lock. 449 * Writes must take both locks. 450 */ 451 QTAILQ_ENTRY(RAMBlock) next; 452 #if defined(__linux__) && !defined(TARGET_S390X) 453 int fd; 454 #endif 455 } RAMBlock; 456 457 typedef struct RAMList { 458 QemuMutex mutex; 459 /* Protected by the iothread lock. */ 460 uint8_t *phys_dirty; 461 RAMBlock *mru_block; 462 /* Protected by the ramlist lock. */ 463 QTAILQ_HEAD(, RAMBlock) blocks; 464 uint32_t version; 465 } RAMList; 466 extern RAMList ram_list; 467 468 extern const char *mem_path; 469 extern int mem_prealloc; 470 471 /* Flags stored in the low bits of the TLB virtual address. These are 472 defined so that fast path ram access is all zeros. */ 473 /* Zero if TLB entry is valid. */ 474 #define TLB_INVALID_MASK (1 << 3) 475 /* Set if TLB entry references a clean RAM page. The iotlb entry will 476 contain the page physical address. */ 477 #define TLB_NOTDIRTY (1 << 4) 478 /* Set if TLB entry is an IO callback. */ 479 #define TLB_MMIO (1 << 5) 480 481 void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); 482 ram_addr_t last_ram_offset(void); 483 void qemu_mutex_lock_ramlist(void); 484 void qemu_mutex_unlock_ramlist(void); 485 #endif /* !CONFIG_USER_ONLY */ 486 487 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 488 uint8_t *buf, int len, int is_write); 489 490 #endif /* CPU_ALL_H */ 491