1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "qemu-common.h" 23 #include "exec/cpu-common.h" 24 #include "exec/memory.h" 25 #include "qemu/thread.h" 26 #include "qom/cpu.h" 27 #include "qemu/rcu.h" 28 29 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 30 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 31 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 32 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 33 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 34 35 /* some important defines: 36 * 37 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and 38 * otherwise little endian. 39 * 40 * TARGET_WORDS_BIGENDIAN : same for target cpu 41 */ 42 43 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) 44 #define BSWAP_NEEDED 45 #endif 46 47 #ifdef BSWAP_NEEDED 48 49 static inline uint16_t tswap16(uint16_t s) 50 { 51 return bswap16(s); 52 } 53 54 static inline uint32_t tswap32(uint32_t s) 55 { 56 return bswap32(s); 57 } 58 59 static inline uint64_t tswap64(uint64_t s) 60 { 61 return bswap64(s); 62 } 63 64 static inline void tswap16s(uint16_t *s) 65 { 66 *s = bswap16(*s); 67 } 68 69 static inline void tswap32s(uint32_t *s) 70 { 71 *s = bswap32(*s); 72 } 73 74 static inline void tswap64s(uint64_t *s) 75 { 76 *s = bswap64(*s); 77 } 78 79 #else 80 81 static inline uint16_t tswap16(uint16_t s) 82 { 83 return s; 84 } 85 86 static inline uint32_t tswap32(uint32_t s) 87 { 88 return s; 89 } 90 91 static inline uint64_t tswap64(uint64_t s) 92 { 93 return s; 94 } 95 96 static inline void tswap16s(uint16_t *s) 97 { 98 } 99 100 static inline void tswap32s(uint32_t *s) 101 { 102 } 103 104 static inline void tswap64s(uint64_t *s) 105 { 106 } 107 108 #endif 109 110 #if TARGET_LONG_SIZE == 4 111 #define tswapl(s) tswap32(s) 112 #define tswapls(s) tswap32s((uint32_t *)(s)) 113 #define bswaptls(s) bswap32s(s) 114 #else 115 #define tswapl(s) tswap64(s) 116 #define tswapls(s) tswap64s((uint64_t *)(s)) 117 #define bswaptls(s) bswap64s(s) 118 #endif 119 120 /* Target-endianness CPU memory access functions. These fit into the 121 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. 122 */ 123 #if defined(TARGET_WORDS_BIGENDIAN) 124 #define lduw_p(p) lduw_be_p(p) 125 #define ldsw_p(p) ldsw_be_p(p) 126 #define ldl_p(p) ldl_be_p(p) 127 #define ldq_p(p) ldq_be_p(p) 128 #define ldfl_p(p) ldfl_be_p(p) 129 #define ldfq_p(p) ldfq_be_p(p) 130 #define stw_p(p, v) stw_be_p(p, v) 131 #define stl_p(p, v) stl_be_p(p, v) 132 #define stq_p(p, v) stq_be_p(p, v) 133 #define stfl_p(p, v) stfl_be_p(p, v) 134 #define stfq_p(p, v) stfq_be_p(p, v) 135 #else 136 #define lduw_p(p) lduw_le_p(p) 137 #define ldsw_p(p) ldsw_le_p(p) 138 #define ldl_p(p) ldl_le_p(p) 139 #define ldq_p(p) ldq_le_p(p) 140 #define ldfl_p(p) ldfl_le_p(p) 141 #define ldfq_p(p) ldfq_le_p(p) 142 #define stw_p(p, v) stw_le_p(p, v) 143 #define stl_p(p, v) stl_le_p(p, v) 144 #define stq_p(p, v) stq_le_p(p, v) 145 #define stfl_p(p, v) stfl_le_p(p, v) 146 #define stfq_p(p, v) stfq_le_p(p, v) 147 #endif 148 149 /* MMU memory access macros */ 150 151 #if defined(CONFIG_USER_ONLY) 152 #include "exec/user/abitypes.h" 153 154 /* On some host systems the guest address space is reserved on the host. 155 * This allows the guest address space to be offset to a convenient location. 156 */ 157 extern unsigned long guest_base; 158 extern int have_guest_base; 159 extern unsigned long reserved_va; 160 161 #define GUEST_ADDR_MAX (reserved_va ? reserved_va : \ 162 (1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1) 163 #else 164 165 #include "exec/hwaddr.h" 166 uint32_t lduw_phys(AddressSpace *as, hwaddr addr); 167 uint32_t ldl_phys(AddressSpace *as, hwaddr addr); 168 uint64_t ldq_phys(AddressSpace *as, hwaddr addr); 169 void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val); 170 void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val); 171 void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val); 172 void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val); 173 174 uint32_t address_space_lduw(AddressSpace *as, hwaddr addr, 175 MemTxAttrs attrs, MemTxResult *result); 176 uint32_t address_space_ldl(AddressSpace *as, hwaddr addr, 177 MemTxAttrs attrs, MemTxResult *result); 178 uint64_t address_space_ldq(AddressSpace *as, hwaddr addr, 179 MemTxAttrs attrs, MemTxResult *result); 180 void address_space_stl_notdirty(AddressSpace *as, hwaddr addr, uint32_t val, 181 MemTxAttrs attrs, MemTxResult *result); 182 void address_space_stw(AddressSpace *as, hwaddr addr, uint32_t val, 183 MemTxAttrs attrs, MemTxResult *result); 184 void address_space_stl(AddressSpace *as, hwaddr addr, uint32_t val, 185 MemTxAttrs attrs, MemTxResult *result); 186 void address_space_stq(AddressSpace *as, hwaddr addr, uint64_t val, 187 MemTxAttrs attrs, MemTxResult *result); 188 #endif 189 190 /* page related stuff */ 191 192 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 193 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) 194 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) 195 196 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 197 * when intptr_t is 32-bit and we are aligning a long long. 198 */ 199 extern uintptr_t qemu_real_host_page_size; 200 extern intptr_t qemu_real_host_page_mask; 201 extern uintptr_t qemu_host_page_size; 202 extern intptr_t qemu_host_page_mask; 203 204 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) 205 #define REAL_HOST_PAGE_ALIGN(addr) (((addr) + qemu_real_host_page_size - 1) & \ 206 qemu_real_host_page_mask) 207 208 /* same as PROT_xxx */ 209 #define PAGE_READ 0x0001 210 #define PAGE_WRITE 0x0002 211 #define PAGE_EXEC 0x0004 212 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 213 #define PAGE_VALID 0x0008 214 /* original state of the write flag (used when tracking self-modifying 215 code */ 216 #define PAGE_WRITE_ORG 0x0010 217 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 218 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 219 #define PAGE_RESERVED 0x0020 220 #endif 221 222 #if defined(CONFIG_USER_ONLY) 223 void page_dump(FILE *f); 224 225 typedef int (*walk_memory_regions_fn)(void *, target_ulong, 226 target_ulong, unsigned long); 227 int walk_memory_regions(void *, walk_memory_regions_fn); 228 229 int page_get_flags(target_ulong address); 230 void page_set_flags(target_ulong start, target_ulong end, int flags); 231 int page_check_range(target_ulong start, target_ulong len, int flags); 232 #endif 233 234 CPUArchState *cpu_copy(CPUArchState *env); 235 236 /* Flags for use in ENV->INTERRUPT_PENDING. 237 238 The numbers assigned here are non-sequential in order to preserve 239 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 240 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 241 the vmstate dump. */ 242 243 /* External hardware interrupt pending. This is typically used for 244 interrupts from devices. */ 245 #define CPU_INTERRUPT_HARD 0x0002 246 247 /* Exit the current TB. This is typically used when some system-level device 248 makes some change to the memory mapping. E.g. the a20 line change. */ 249 #define CPU_INTERRUPT_EXITTB 0x0004 250 251 /* Halt the CPU. */ 252 #define CPU_INTERRUPT_HALT 0x0020 253 254 /* Debug event pending. */ 255 #define CPU_INTERRUPT_DEBUG 0x0080 256 257 /* Reset signal. */ 258 #define CPU_INTERRUPT_RESET 0x0400 259 260 /* Several target-specific external hardware interrupts. Each target/cpu.h 261 should define proper names based on these defines. */ 262 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 263 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 264 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 265 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 266 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 267 268 /* Several target-specific internal interrupts. These differ from the 269 preceding target-specific interrupts in that they are intended to 270 originate from within the cpu itself, typically in response to some 271 instruction being executed. These, therefore, are not masked while 272 single-stepping within the debugger. */ 273 #define CPU_INTERRUPT_TGT_INT_0 0x0100 274 #define CPU_INTERRUPT_TGT_INT_1 0x0800 275 #define CPU_INTERRUPT_TGT_INT_2 0x2000 276 277 /* First unused bit: 0x4000. */ 278 279 /* The set of all bits that should be masked when single-stepping. */ 280 #define CPU_INTERRUPT_SSTEP_MASK \ 281 (CPU_INTERRUPT_HARD \ 282 | CPU_INTERRUPT_TGT_EXT_0 \ 283 | CPU_INTERRUPT_TGT_EXT_1 \ 284 | CPU_INTERRUPT_TGT_EXT_2 \ 285 | CPU_INTERRUPT_TGT_EXT_3 \ 286 | CPU_INTERRUPT_TGT_EXT_4) 287 288 #if !defined(CONFIG_USER_ONLY) 289 290 /* Flags stored in the low bits of the TLB virtual address. These are 291 defined so that fast path ram access is all zeros. */ 292 /* Zero if TLB entry is valid. */ 293 #define TLB_INVALID_MASK (1 << 3) 294 /* Set if TLB entry references a clean RAM page. The iotlb entry will 295 contain the page physical address. */ 296 #define TLB_NOTDIRTY (1 << 4) 297 /* Set if TLB entry is an IO callback. */ 298 #define TLB_MMIO (1 << 5) 299 300 void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); 301 void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf); 302 #endif /* !CONFIG_USER_ONLY */ 303 304 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 305 uint8_t *buf, int len, int is_write); 306 307 #endif /* CPU_ALL_H */ 308