1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "qemu-common.h" 23 #include "exec/cpu-common.h" 24 #include "qemu/thread.h" 25 #include "qom/cpu.h" 26 27 /* some important defines: 28 * 29 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned 30 * memory accesses. 31 * 32 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and 33 * otherwise little endian. 34 * 35 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet)) 36 * 37 * TARGET_WORDS_BIGENDIAN : same for target cpu 38 */ 39 40 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) 41 #define BSWAP_NEEDED 42 #endif 43 44 #ifdef BSWAP_NEEDED 45 46 static inline uint16_t tswap16(uint16_t s) 47 { 48 return bswap16(s); 49 } 50 51 static inline uint32_t tswap32(uint32_t s) 52 { 53 return bswap32(s); 54 } 55 56 static inline uint64_t tswap64(uint64_t s) 57 { 58 return bswap64(s); 59 } 60 61 static inline void tswap16s(uint16_t *s) 62 { 63 *s = bswap16(*s); 64 } 65 66 static inline void tswap32s(uint32_t *s) 67 { 68 *s = bswap32(*s); 69 } 70 71 static inline void tswap64s(uint64_t *s) 72 { 73 *s = bswap64(*s); 74 } 75 76 #else 77 78 static inline uint16_t tswap16(uint16_t s) 79 { 80 return s; 81 } 82 83 static inline uint32_t tswap32(uint32_t s) 84 { 85 return s; 86 } 87 88 static inline uint64_t tswap64(uint64_t s) 89 { 90 return s; 91 } 92 93 static inline void tswap16s(uint16_t *s) 94 { 95 } 96 97 static inline void tswap32s(uint32_t *s) 98 { 99 } 100 101 static inline void tswap64s(uint64_t *s) 102 { 103 } 104 105 #endif 106 107 #if TARGET_LONG_SIZE == 4 108 #define tswapl(s) tswap32(s) 109 #define tswapls(s) tswap32s((uint32_t *)(s)) 110 #define bswaptls(s) bswap32s(s) 111 #else 112 #define tswapl(s) tswap64(s) 113 #define tswapls(s) tswap64s((uint64_t *)(s)) 114 #define bswaptls(s) bswap64s(s) 115 #endif 116 117 /* CPU memory access without any memory or io remapping */ 118 119 /* 120 * the generic syntax for the memory accesses is: 121 * 122 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr) 123 * 124 * store: st{type}{size}{endian}_{access_type}(ptr, val) 125 * 126 * type is: 127 * (empty): integer access 128 * f : float access 129 * 130 * sign is: 131 * (empty): for floats or 32 bit size 132 * u : unsigned 133 * s : signed 134 * 135 * size is: 136 * b: 8 bits 137 * w: 16 bits 138 * l: 32 bits 139 * q: 64 bits 140 * 141 * endian is: 142 * (empty): target cpu endianness or 8 bit access 143 * r : reversed target cpu endianness (not implemented yet) 144 * be : big endian (not implemented yet) 145 * le : little endian (not implemented yet) 146 * 147 * access_type is: 148 * raw : host memory access 149 * user : user mode access using soft MMU 150 * kernel : kernel mode access using soft MMU 151 */ 152 153 /* target-endianness CPU memory access functions */ 154 #if defined(TARGET_WORDS_BIGENDIAN) 155 #define lduw_p(p) lduw_be_p(p) 156 #define ldsw_p(p) ldsw_be_p(p) 157 #define ldl_p(p) ldl_be_p(p) 158 #define ldq_p(p) ldq_be_p(p) 159 #define ldfl_p(p) ldfl_be_p(p) 160 #define ldfq_p(p) ldfq_be_p(p) 161 #define stw_p(p, v) stw_be_p(p, v) 162 #define stl_p(p, v) stl_be_p(p, v) 163 #define stq_p(p, v) stq_be_p(p, v) 164 #define stfl_p(p, v) stfl_be_p(p, v) 165 #define stfq_p(p, v) stfq_be_p(p, v) 166 #else 167 #define lduw_p(p) lduw_le_p(p) 168 #define ldsw_p(p) ldsw_le_p(p) 169 #define ldl_p(p) ldl_le_p(p) 170 #define ldq_p(p) ldq_le_p(p) 171 #define ldfl_p(p) ldfl_le_p(p) 172 #define ldfq_p(p) ldfq_le_p(p) 173 #define stw_p(p, v) stw_le_p(p, v) 174 #define stl_p(p, v) stl_le_p(p, v) 175 #define stq_p(p, v) stq_le_p(p, v) 176 #define stfl_p(p, v) stfl_le_p(p, v) 177 #define stfq_p(p, v) stfq_le_p(p, v) 178 #endif 179 180 /* MMU memory access macros */ 181 182 #if defined(CONFIG_USER_ONLY) 183 #include <assert.h> 184 #include "exec/user/abitypes.h" 185 186 /* On some host systems the guest address space is reserved on the host. 187 * This allows the guest address space to be offset to a convenient location. 188 */ 189 #if defined(CONFIG_USE_GUEST_BASE) 190 extern unsigned long guest_base; 191 extern int have_guest_base; 192 extern unsigned long reserved_va; 193 #define GUEST_BASE guest_base 194 #define RESERVED_VA reserved_va 195 #else 196 #define GUEST_BASE 0ul 197 #define RESERVED_VA 0ul 198 #endif 199 200 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ 201 #define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE)) 202 203 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS 204 #define h2g_valid(x) 1 205 #else 206 #define h2g_valid(x) ({ \ 207 unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ 208 (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \ 209 (!RESERVED_VA || (__guest < RESERVED_VA)); \ 210 }) 211 #endif 212 213 #define h2g_nocheck(x) ({ \ 214 unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ 215 (abi_ulong)__ret; \ 216 }) 217 218 #define h2g(x) ({ \ 219 /* Check if given address fits target address space */ \ 220 assert(h2g_valid(x)); \ 221 h2g_nocheck(x); \ 222 }) 223 224 #define saddr(x) g2h(x) 225 #define laddr(x) g2h(x) 226 227 #else /* !CONFIG_USER_ONLY */ 228 /* NOTE: we use double casts if pointers and target_ulong have 229 different sizes */ 230 #define saddr(x) (uint8_t *)(intptr_t)(x) 231 #define laddr(x) (uint8_t *)(intptr_t)(x) 232 #endif 233 234 #define ldub_raw(p) ldub_p(laddr((p))) 235 #define ldsb_raw(p) ldsb_p(laddr((p))) 236 #define lduw_raw(p) lduw_p(laddr((p))) 237 #define ldsw_raw(p) ldsw_p(laddr((p))) 238 #define ldl_raw(p) ldl_p(laddr((p))) 239 #define ldq_raw(p) ldq_p(laddr((p))) 240 #define ldfl_raw(p) ldfl_p(laddr((p))) 241 #define ldfq_raw(p) ldfq_p(laddr((p))) 242 #define stb_raw(p, v) stb_p(saddr((p)), v) 243 #define stw_raw(p, v) stw_p(saddr((p)), v) 244 #define stl_raw(p, v) stl_p(saddr((p)), v) 245 #define stq_raw(p, v) stq_p(saddr((p)), v) 246 #define stfl_raw(p, v) stfl_p(saddr((p)), v) 247 #define stfq_raw(p, v) stfq_p(saddr((p)), v) 248 249 250 #if defined(CONFIG_USER_ONLY) 251 252 /* if user mode, no other memory access functions */ 253 #define ldub(p) ldub_raw(p) 254 #define ldsb(p) ldsb_raw(p) 255 #define lduw(p) lduw_raw(p) 256 #define ldsw(p) ldsw_raw(p) 257 #define ldl(p) ldl_raw(p) 258 #define ldq(p) ldq_raw(p) 259 #define ldfl(p) ldfl_raw(p) 260 #define ldfq(p) ldfq_raw(p) 261 #define stb(p, v) stb_raw(p, v) 262 #define stw(p, v) stw_raw(p, v) 263 #define stl(p, v) stl_raw(p, v) 264 #define stq(p, v) stq_raw(p, v) 265 #define stfl(p, v) stfl_raw(p, v) 266 #define stfq(p, v) stfq_raw(p, v) 267 268 #define cpu_ldub_code(env1, p) ldub_raw(p) 269 #define cpu_ldsb_code(env1, p) ldsb_raw(p) 270 #define cpu_lduw_code(env1, p) lduw_raw(p) 271 #define cpu_ldsw_code(env1, p) ldsw_raw(p) 272 #define cpu_ldl_code(env1, p) ldl_raw(p) 273 #define cpu_ldq_code(env1, p) ldq_raw(p) 274 275 #define cpu_ldub_data(env, addr) ldub_raw(addr) 276 #define cpu_lduw_data(env, addr) lduw_raw(addr) 277 #define cpu_ldsw_data(env, addr) ldsw_raw(addr) 278 #define cpu_ldl_data(env, addr) ldl_raw(addr) 279 #define cpu_ldq_data(env, addr) ldq_raw(addr) 280 281 #define cpu_stb_data(env, addr, data) stb_raw(addr, data) 282 #define cpu_stw_data(env, addr, data) stw_raw(addr, data) 283 #define cpu_stl_data(env, addr, data) stl_raw(addr, data) 284 #define cpu_stq_data(env, addr, data) stq_raw(addr, data) 285 286 #define cpu_ldub_kernel(env, addr) ldub_raw(addr) 287 #define cpu_lduw_kernel(env, addr) lduw_raw(addr) 288 #define cpu_ldsw_kernel(env, addr) ldsw_raw(addr) 289 #define cpu_ldl_kernel(env, addr) ldl_raw(addr) 290 #define cpu_ldq_kernel(env, addr) ldq_raw(addr) 291 292 #define cpu_stb_kernel(env, addr, data) stb_raw(addr, data) 293 #define cpu_stw_kernel(env, addr, data) stw_raw(addr, data) 294 #define cpu_stl_kernel(env, addr, data) stl_raw(addr, data) 295 #define cpu_stq_kernel(env, addr, data) stq_raw(addr, data) 296 297 #define ldub_kernel(p) ldub_raw(p) 298 #define ldsb_kernel(p) ldsb_raw(p) 299 #define lduw_kernel(p) lduw_raw(p) 300 #define ldsw_kernel(p) ldsw_raw(p) 301 #define ldl_kernel(p) ldl_raw(p) 302 #define ldq_kernel(p) ldq_raw(p) 303 #define ldfl_kernel(p) ldfl_raw(p) 304 #define ldfq_kernel(p) ldfq_raw(p) 305 #define stb_kernel(p, v) stb_raw(p, v) 306 #define stw_kernel(p, v) stw_raw(p, v) 307 #define stl_kernel(p, v) stl_raw(p, v) 308 #define stq_kernel(p, v) stq_raw(p, v) 309 #define stfl_kernel(p, v) stfl_raw(p, v) 310 #define stfq_kernel(p, vt) stfq_raw(p, v) 311 312 #define cpu_ldub_data(env, addr) ldub_raw(addr) 313 #define cpu_lduw_data(env, addr) lduw_raw(addr) 314 #define cpu_ldl_data(env, addr) ldl_raw(addr) 315 316 #define cpu_stb_data(env, addr, data) stb_raw(addr, data) 317 #define cpu_stw_data(env, addr, data) stw_raw(addr, data) 318 #define cpu_stl_data(env, addr, data) stl_raw(addr, data) 319 #endif /* defined(CONFIG_USER_ONLY) */ 320 321 /* page related stuff */ 322 323 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 324 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) 325 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) 326 327 /* ??? These should be the larger of uintptr_t and target_ulong. */ 328 extern uintptr_t qemu_real_host_page_size; 329 extern uintptr_t qemu_host_page_size; 330 extern uintptr_t qemu_host_page_mask; 331 332 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) 333 334 /* same as PROT_xxx */ 335 #define PAGE_READ 0x0001 336 #define PAGE_WRITE 0x0002 337 #define PAGE_EXEC 0x0004 338 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 339 #define PAGE_VALID 0x0008 340 /* original state of the write flag (used when tracking self-modifying 341 code */ 342 #define PAGE_WRITE_ORG 0x0010 343 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 344 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 345 #define PAGE_RESERVED 0x0020 346 #endif 347 348 #if defined(CONFIG_USER_ONLY) 349 void page_dump(FILE *f); 350 351 typedef int (*walk_memory_regions_fn)(void *, abi_ulong, 352 abi_ulong, unsigned long); 353 int walk_memory_regions(void *, walk_memory_regions_fn); 354 355 int page_get_flags(target_ulong address); 356 void page_set_flags(target_ulong start, target_ulong end, int flags); 357 int page_check_range(target_ulong start, target_ulong len, int flags); 358 #endif 359 360 CPUArchState *cpu_copy(CPUArchState *env); 361 362 void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) 363 GCC_FMT_ATTR(2, 3); 364 365 /* Flags for use in ENV->INTERRUPT_PENDING. 366 367 The numbers assigned here are non-sequential in order to preserve 368 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 369 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 370 the vmstate dump. */ 371 372 /* External hardware interrupt pending. This is typically used for 373 interrupts from devices. */ 374 #define CPU_INTERRUPT_HARD 0x0002 375 376 /* Exit the current TB. This is typically used when some system-level device 377 makes some change to the memory mapping. E.g. the a20 line change. */ 378 #define CPU_INTERRUPT_EXITTB 0x0004 379 380 /* Halt the CPU. */ 381 #define CPU_INTERRUPT_HALT 0x0020 382 383 /* Debug event pending. */ 384 #define CPU_INTERRUPT_DEBUG 0x0080 385 386 /* Several target-specific external hardware interrupts. Each target/cpu.h 387 should define proper names based on these defines. */ 388 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 389 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 390 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 391 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 392 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 393 394 /* Several target-specific internal interrupts. These differ from the 395 preceding target-specific interrupts in that they are intended to 396 originate from within the cpu itself, typically in response to some 397 instruction being executed. These, therefore, are not masked while 398 single-stepping within the debugger. */ 399 #define CPU_INTERRUPT_TGT_INT_0 0x0100 400 #define CPU_INTERRUPT_TGT_INT_1 0x0400 401 #define CPU_INTERRUPT_TGT_INT_2 0x0800 402 #define CPU_INTERRUPT_TGT_INT_3 0x2000 403 404 /* First unused bit: 0x4000. */ 405 406 /* The set of all bits that should be masked when single-stepping. */ 407 #define CPU_INTERRUPT_SSTEP_MASK \ 408 (CPU_INTERRUPT_HARD \ 409 | CPU_INTERRUPT_TGT_EXT_0 \ 410 | CPU_INTERRUPT_TGT_EXT_1 \ 411 | CPU_INTERRUPT_TGT_EXT_2 \ 412 | CPU_INTERRUPT_TGT_EXT_3 \ 413 | CPU_INTERRUPT_TGT_EXT_4) 414 415 /* Breakpoint/watchpoint flags */ 416 #define BP_MEM_READ 0x01 417 #define BP_MEM_WRITE 0x02 418 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) 419 #define BP_STOP_BEFORE_ACCESS 0x04 420 #define BP_WATCHPOINT_HIT 0x08 421 #define BP_GDB 0x10 422 #define BP_CPU 0x20 423 424 int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, 425 CPUBreakpoint **breakpoint); 426 int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); 427 void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint); 428 void cpu_breakpoint_remove_all(CPUArchState *env, int mask); 429 int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, 430 int flags, CPUWatchpoint **watchpoint); 431 int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, 432 target_ulong len, int flags); 433 void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint); 434 void cpu_watchpoint_remove_all(CPUArchState *env, int mask); 435 436 #if !defined(CONFIG_USER_ONLY) 437 438 /* memory API */ 439 440 extern ram_addr_t ram_size; 441 442 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */ 443 #define RAM_PREALLOC_MASK (1 << 0) 444 445 typedef struct RAMBlock { 446 struct MemoryRegion *mr; 447 uint8_t *host; 448 ram_addr_t offset; 449 ram_addr_t length; 450 uint32_t flags; 451 char idstr[256]; 452 /* Reads can take either the iothread or the ramlist lock. 453 * Writes must take both locks. 454 */ 455 QTAILQ_ENTRY(RAMBlock) next; 456 int fd; 457 } RAMBlock; 458 459 typedef struct RAMList { 460 QemuMutex mutex; 461 /* Protected by the iothread lock. */ 462 uint8_t *phys_dirty; 463 RAMBlock *mru_block; 464 /* Protected by the ramlist lock. */ 465 QTAILQ_HEAD(, RAMBlock) blocks; 466 uint32_t version; 467 } RAMList; 468 extern RAMList ram_list; 469 470 extern const char *mem_path; 471 extern int mem_prealloc; 472 473 /* Flags stored in the low bits of the TLB virtual address. These are 474 defined so that fast path ram access is all zeros. */ 475 /* Zero if TLB entry is valid. */ 476 #define TLB_INVALID_MASK (1 << 3) 477 /* Set if TLB entry references a clean RAM page. The iotlb entry will 478 contain the page physical address. */ 479 #define TLB_NOTDIRTY (1 << 4) 480 /* Set if TLB entry is an IO callback. */ 481 #define TLB_MMIO (1 << 5) 482 483 void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); 484 ram_addr_t last_ram_offset(void); 485 void qemu_mutex_lock_ramlist(void); 486 void qemu_mutex_unlock_ramlist(void); 487 #endif /* !CONFIG_USER_ONLY */ 488 489 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 490 uint8_t *buf, int len, int is_write); 491 492 #endif /* CPU_ALL_H */ 493