1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "qemu-common.h" 23 #include "exec/cpu-common.h" 24 #include "exec/memory.h" 25 #include "qemu/thread.h" 26 #include "qom/cpu.h" 27 28 /* some important defines: 29 * 30 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned 31 * memory accesses. 32 * 33 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and 34 * otherwise little endian. 35 * 36 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet)) 37 * 38 * TARGET_WORDS_BIGENDIAN : same for target cpu 39 */ 40 41 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) 42 #define BSWAP_NEEDED 43 #endif 44 45 #ifdef BSWAP_NEEDED 46 47 static inline uint16_t tswap16(uint16_t s) 48 { 49 return bswap16(s); 50 } 51 52 static inline uint32_t tswap32(uint32_t s) 53 { 54 return bswap32(s); 55 } 56 57 static inline uint64_t tswap64(uint64_t s) 58 { 59 return bswap64(s); 60 } 61 62 static inline void tswap16s(uint16_t *s) 63 { 64 *s = bswap16(*s); 65 } 66 67 static inline void tswap32s(uint32_t *s) 68 { 69 *s = bswap32(*s); 70 } 71 72 static inline void tswap64s(uint64_t *s) 73 { 74 *s = bswap64(*s); 75 } 76 77 #else 78 79 static inline uint16_t tswap16(uint16_t s) 80 { 81 return s; 82 } 83 84 static inline uint32_t tswap32(uint32_t s) 85 { 86 return s; 87 } 88 89 static inline uint64_t tswap64(uint64_t s) 90 { 91 return s; 92 } 93 94 static inline void tswap16s(uint16_t *s) 95 { 96 } 97 98 static inline void tswap32s(uint32_t *s) 99 { 100 } 101 102 static inline void tswap64s(uint64_t *s) 103 { 104 } 105 106 #endif 107 108 #if TARGET_LONG_SIZE == 4 109 #define tswapl(s) tswap32(s) 110 #define tswapls(s) tswap32s((uint32_t *)(s)) 111 #define bswaptls(s) bswap32s(s) 112 #else 113 #define tswapl(s) tswap64(s) 114 #define tswapls(s) tswap64s((uint64_t *)(s)) 115 #define bswaptls(s) bswap64s(s) 116 #endif 117 118 /* CPU memory access without any memory or io remapping */ 119 120 /* 121 * the generic syntax for the memory accesses is: 122 * 123 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr) 124 * 125 * store: st{type}{size}{endian}_{access_type}(ptr, val) 126 * 127 * type is: 128 * (empty): integer access 129 * f : float access 130 * 131 * sign is: 132 * (empty): for floats or 32 bit size 133 * u : unsigned 134 * s : signed 135 * 136 * size is: 137 * b: 8 bits 138 * w: 16 bits 139 * l: 32 bits 140 * q: 64 bits 141 * 142 * endian is: 143 * (empty): target cpu endianness or 8 bit access 144 * r : reversed target cpu endianness (not implemented yet) 145 * be : big endian (not implemented yet) 146 * le : little endian (not implemented yet) 147 * 148 * access_type is: 149 * raw : host memory access 150 * user : user mode access using soft MMU 151 * kernel : kernel mode access using soft MMU 152 */ 153 154 /* target-endianness CPU memory access functions */ 155 #if defined(TARGET_WORDS_BIGENDIAN) 156 #define lduw_p(p) lduw_be_p(p) 157 #define ldsw_p(p) ldsw_be_p(p) 158 #define ldl_p(p) ldl_be_p(p) 159 #define ldq_p(p) ldq_be_p(p) 160 #define ldfl_p(p) ldfl_be_p(p) 161 #define ldfq_p(p) ldfq_be_p(p) 162 #define stw_p(p, v) stw_be_p(p, v) 163 #define stl_p(p, v) stl_be_p(p, v) 164 #define stq_p(p, v) stq_be_p(p, v) 165 #define stfl_p(p, v) stfl_be_p(p, v) 166 #define stfq_p(p, v) stfq_be_p(p, v) 167 #else 168 #define lduw_p(p) lduw_le_p(p) 169 #define ldsw_p(p) ldsw_le_p(p) 170 #define ldl_p(p) ldl_le_p(p) 171 #define ldq_p(p) ldq_le_p(p) 172 #define ldfl_p(p) ldfl_le_p(p) 173 #define ldfq_p(p) ldfq_le_p(p) 174 #define stw_p(p, v) stw_le_p(p, v) 175 #define stl_p(p, v) stl_le_p(p, v) 176 #define stq_p(p, v) stq_le_p(p, v) 177 #define stfl_p(p, v) stfl_le_p(p, v) 178 #define stfq_p(p, v) stfq_le_p(p, v) 179 #endif 180 181 /* MMU memory access macros */ 182 183 #if defined(CONFIG_USER_ONLY) 184 #include <assert.h> 185 #include "exec/user/abitypes.h" 186 187 /* On some host systems the guest address space is reserved on the host. 188 * This allows the guest address space to be offset to a convenient location. 189 */ 190 #if defined(CONFIG_USE_GUEST_BASE) 191 extern unsigned long guest_base; 192 extern int have_guest_base; 193 extern unsigned long reserved_va; 194 #define GUEST_BASE guest_base 195 #define RESERVED_VA reserved_va 196 #else 197 #define GUEST_BASE 0ul 198 #define RESERVED_VA 0ul 199 #endif 200 201 #endif 202 203 /* page related stuff */ 204 205 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 206 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) 207 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) 208 209 /* ??? These should be the larger of uintptr_t and target_ulong. */ 210 extern uintptr_t qemu_real_host_page_size; 211 extern uintptr_t qemu_host_page_size; 212 extern uintptr_t qemu_host_page_mask; 213 214 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) 215 216 /* same as PROT_xxx */ 217 #define PAGE_READ 0x0001 218 #define PAGE_WRITE 0x0002 219 #define PAGE_EXEC 0x0004 220 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 221 #define PAGE_VALID 0x0008 222 /* original state of the write flag (used when tracking self-modifying 223 code */ 224 #define PAGE_WRITE_ORG 0x0010 225 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 226 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 227 #define PAGE_RESERVED 0x0020 228 #endif 229 230 #if defined(CONFIG_USER_ONLY) 231 void page_dump(FILE *f); 232 233 typedef int (*walk_memory_regions_fn)(void *, abi_ulong, 234 abi_ulong, unsigned long); 235 int walk_memory_regions(void *, walk_memory_regions_fn); 236 237 int page_get_flags(target_ulong address); 238 void page_set_flags(target_ulong start, target_ulong end, int flags); 239 int page_check_range(target_ulong start, target_ulong len, int flags); 240 #endif 241 242 CPUArchState *cpu_copy(CPUArchState *env); 243 244 /* Flags for use in ENV->INTERRUPT_PENDING. 245 246 The numbers assigned here are non-sequential in order to preserve 247 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 248 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 249 the vmstate dump. */ 250 251 /* External hardware interrupt pending. This is typically used for 252 interrupts from devices. */ 253 #define CPU_INTERRUPT_HARD 0x0002 254 255 /* Exit the current TB. This is typically used when some system-level device 256 makes some change to the memory mapping. E.g. the a20 line change. */ 257 #define CPU_INTERRUPT_EXITTB 0x0004 258 259 /* Halt the CPU. */ 260 #define CPU_INTERRUPT_HALT 0x0020 261 262 /* Debug event pending. */ 263 #define CPU_INTERRUPT_DEBUG 0x0080 264 265 /* Reset signal. */ 266 #define CPU_INTERRUPT_RESET 0x0400 267 268 /* Several target-specific external hardware interrupts. Each target/cpu.h 269 should define proper names based on these defines. */ 270 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 271 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 272 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 273 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 274 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 275 276 /* Several target-specific internal interrupts. These differ from the 277 preceding target-specific interrupts in that they are intended to 278 originate from within the cpu itself, typically in response to some 279 instruction being executed. These, therefore, are not masked while 280 single-stepping within the debugger. */ 281 #define CPU_INTERRUPT_TGT_INT_0 0x0100 282 #define CPU_INTERRUPT_TGT_INT_1 0x0800 283 #define CPU_INTERRUPT_TGT_INT_2 0x2000 284 285 /* First unused bit: 0x4000. */ 286 287 /* The set of all bits that should be masked when single-stepping. */ 288 #define CPU_INTERRUPT_SSTEP_MASK \ 289 (CPU_INTERRUPT_HARD \ 290 | CPU_INTERRUPT_TGT_EXT_0 \ 291 | CPU_INTERRUPT_TGT_EXT_1 \ 292 | CPU_INTERRUPT_TGT_EXT_2 \ 293 | CPU_INTERRUPT_TGT_EXT_3 \ 294 | CPU_INTERRUPT_TGT_EXT_4) 295 296 #if !defined(CONFIG_USER_ONLY) 297 298 /* memory API */ 299 300 typedef struct RAMBlock { 301 struct MemoryRegion *mr; 302 uint8_t *host; 303 ram_addr_t offset; 304 ram_addr_t length; 305 uint32_t flags; 306 char idstr[256]; 307 /* Reads can take either the iothread or the ramlist lock. 308 * Writes must take both locks. 309 */ 310 QTAILQ_ENTRY(RAMBlock) next; 311 int fd; 312 } RAMBlock; 313 314 typedef struct RAMList { 315 QemuMutex mutex; 316 /* Protected by the iothread lock. */ 317 unsigned long *dirty_memory[DIRTY_MEMORY_NUM]; 318 RAMBlock *mru_block; 319 /* Protected by the ramlist lock. */ 320 QTAILQ_HEAD(, RAMBlock) blocks; 321 uint32_t version; 322 } RAMList; 323 extern RAMList ram_list; 324 325 /* Flags stored in the low bits of the TLB virtual address. These are 326 defined so that fast path ram access is all zeros. */ 327 /* Zero if TLB entry is valid. */ 328 #define TLB_INVALID_MASK (1 << 3) 329 /* Set if TLB entry references a clean RAM page. The iotlb entry will 330 contain the page physical address. */ 331 #define TLB_NOTDIRTY (1 << 4) 332 /* Set if TLB entry is an IO callback. */ 333 #define TLB_MMIO (1 << 5) 334 335 void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); 336 ram_addr_t last_ram_offset(void); 337 void qemu_mutex_lock_ramlist(void); 338 void qemu_mutex_unlock_ramlist(void); 339 #endif /* !CONFIG_USER_ONLY */ 340 341 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 342 uint8_t *buf, int len, int is_write); 343 344 #endif /* CPU_ALL_H */ 345