1 #ifndef BLOCK_NVME_H 2 #define BLOCK_NVME_H 3 4 typedef struct QEMU_PACKED NvmeBar { 5 uint64_t cap; 6 uint32_t vs; 7 uint32_t intms; 8 uint32_t intmc; 9 uint32_t cc; 10 uint32_t rsvd1; 11 uint32_t csts; 12 uint32_t nssrc; 13 uint32_t aqa; 14 uint64_t asq; 15 uint64_t acq; 16 uint32_t cmbloc; 17 uint32_t cmbsz; 18 uint8_t padding[3520]; /* not used by QEMU */ 19 uint32_t pmrcap; 20 uint32_t pmrctl; 21 uint32_t pmrsts; 22 uint32_t pmrebs; 23 uint32_t pmrswtp; 24 uint64_t pmrmsc; 25 uint8_t reserved[484]; 26 } NvmeBar; 27 28 enum NvmeCapShift { 29 CAP_MQES_SHIFT = 0, 30 CAP_CQR_SHIFT = 16, 31 CAP_AMS_SHIFT = 17, 32 CAP_TO_SHIFT = 24, 33 CAP_DSTRD_SHIFT = 32, 34 CAP_NSSRS_SHIFT = 36, 35 CAP_CSS_SHIFT = 37, 36 CAP_MPSMIN_SHIFT = 48, 37 CAP_MPSMAX_SHIFT = 52, 38 CAP_PMR_SHIFT = 56, 39 }; 40 41 enum NvmeCapMask { 42 CAP_MQES_MASK = 0xffff, 43 CAP_CQR_MASK = 0x1, 44 CAP_AMS_MASK = 0x3, 45 CAP_TO_MASK = 0xff, 46 CAP_DSTRD_MASK = 0xf, 47 CAP_NSSRS_MASK = 0x1, 48 CAP_CSS_MASK = 0xff, 49 CAP_MPSMIN_MASK = 0xf, 50 CAP_MPSMAX_MASK = 0xf, 51 CAP_PMR_MASK = 0x1, 52 }; 53 54 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) 55 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) 56 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) 57 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK) 58 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK) 59 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK) 60 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK) 61 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK) 62 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK) 63 64 #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \ 65 << CAP_MQES_SHIFT) 66 #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \ 67 << CAP_CQR_SHIFT) 68 #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \ 69 << CAP_AMS_SHIFT) 70 #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \ 71 << CAP_TO_SHIFT) 72 #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \ 73 << CAP_DSTRD_SHIFT) 74 #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \ 75 << CAP_NSSRS_SHIFT) 76 #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \ 77 << CAP_CSS_SHIFT) 78 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ 79 << CAP_MPSMIN_SHIFT) 80 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ 81 << CAP_MPSMAX_SHIFT) 82 #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ 83 << CAP_PMR_SHIFT) 84 85 enum NvmeCapCss { 86 NVME_CAP_CSS_NVM = 1 << 0, 87 NVME_CAP_CSS_ADMIN_ONLY = 1 << 7, 88 }; 89 90 enum NvmeCcShift { 91 CC_EN_SHIFT = 0, 92 CC_CSS_SHIFT = 4, 93 CC_MPS_SHIFT = 7, 94 CC_AMS_SHIFT = 11, 95 CC_SHN_SHIFT = 14, 96 CC_IOSQES_SHIFT = 16, 97 CC_IOCQES_SHIFT = 20, 98 }; 99 100 enum NvmeCcMask { 101 CC_EN_MASK = 0x1, 102 CC_CSS_MASK = 0x7, 103 CC_MPS_MASK = 0xf, 104 CC_AMS_MASK = 0x7, 105 CC_SHN_MASK = 0x3, 106 CC_IOSQES_MASK = 0xf, 107 CC_IOCQES_MASK = 0xf, 108 }; 109 110 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) 111 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) 112 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) 113 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK) 114 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK) 115 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) 116 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) 117 118 enum NvmeCcCss { 119 NVME_CC_CSS_NVM = 0x0, 120 NVME_CC_CSS_ADMIN_ONLY = 0x7, 121 }; 122 123 enum NvmeCstsShift { 124 CSTS_RDY_SHIFT = 0, 125 CSTS_CFS_SHIFT = 1, 126 CSTS_SHST_SHIFT = 2, 127 CSTS_NSSRO_SHIFT = 4, 128 }; 129 130 enum NvmeCstsMask { 131 CSTS_RDY_MASK = 0x1, 132 CSTS_CFS_MASK = 0x1, 133 CSTS_SHST_MASK = 0x3, 134 CSTS_NSSRO_MASK = 0x1, 135 }; 136 137 enum NvmeCsts { 138 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT, 139 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT, 140 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT, 141 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT, 142 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT, 143 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT, 144 }; 145 146 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK) 147 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK) 148 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK) 149 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK) 150 151 enum NvmeAqaShift { 152 AQA_ASQS_SHIFT = 0, 153 AQA_ACQS_SHIFT = 16, 154 }; 155 156 enum NvmeAqaMask { 157 AQA_ASQS_MASK = 0xfff, 158 AQA_ACQS_MASK = 0xfff, 159 }; 160 161 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK) 162 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK) 163 164 enum NvmeCmblocShift { 165 CMBLOC_BIR_SHIFT = 0, 166 CMBLOC_OFST_SHIFT = 12, 167 }; 168 169 enum NvmeCmblocMask { 170 CMBLOC_BIR_MASK = 0x7, 171 CMBLOC_OFST_MASK = 0xfffff, 172 }; 173 174 #define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \ 175 CMBLOC_BIR_MASK) 176 #define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \ 177 CMBLOC_OFST_MASK) 178 179 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \ 180 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT) 181 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \ 182 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT) 183 184 enum NvmeCmbszShift { 185 CMBSZ_SQS_SHIFT = 0, 186 CMBSZ_CQS_SHIFT = 1, 187 CMBSZ_LISTS_SHIFT = 2, 188 CMBSZ_RDS_SHIFT = 3, 189 CMBSZ_WDS_SHIFT = 4, 190 CMBSZ_SZU_SHIFT = 8, 191 CMBSZ_SZ_SHIFT = 12, 192 }; 193 194 enum NvmeCmbszMask { 195 CMBSZ_SQS_MASK = 0x1, 196 CMBSZ_CQS_MASK = 0x1, 197 CMBSZ_LISTS_MASK = 0x1, 198 CMBSZ_RDS_MASK = 0x1, 199 CMBSZ_WDS_MASK = 0x1, 200 CMBSZ_SZU_MASK = 0xf, 201 CMBSZ_SZ_MASK = 0xfffff, 202 }; 203 204 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK) 205 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK) 206 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK) 207 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK) 208 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK) 209 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK) 210 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK) 211 212 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \ 213 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT) 214 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \ 215 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT) 216 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \ 217 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT) 218 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \ 219 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT) 220 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \ 221 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT) 222 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \ 223 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT) 224 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \ 225 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT) 226 227 #define NVME_CMBSZ_GETSIZE(cmbsz) \ 228 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz)))) 229 230 enum NvmePmrcapShift { 231 PMRCAP_RDS_SHIFT = 3, 232 PMRCAP_WDS_SHIFT = 4, 233 PMRCAP_BIR_SHIFT = 5, 234 PMRCAP_PMRTU_SHIFT = 8, 235 PMRCAP_PMRWBM_SHIFT = 10, 236 PMRCAP_PMRTO_SHIFT = 16, 237 PMRCAP_CMSS_SHIFT = 24, 238 }; 239 240 enum NvmePmrcapMask { 241 PMRCAP_RDS_MASK = 0x1, 242 PMRCAP_WDS_MASK = 0x1, 243 PMRCAP_BIR_MASK = 0x7, 244 PMRCAP_PMRTU_MASK = 0x3, 245 PMRCAP_PMRWBM_MASK = 0xf, 246 PMRCAP_PMRTO_MASK = 0xff, 247 PMRCAP_CMSS_MASK = 0x1, 248 }; 249 250 #define NVME_PMRCAP_RDS(pmrcap) \ 251 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK) 252 #define NVME_PMRCAP_WDS(pmrcap) \ 253 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK) 254 #define NVME_PMRCAP_BIR(pmrcap) \ 255 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK) 256 #define NVME_PMRCAP_PMRTU(pmrcap) \ 257 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK) 258 #define NVME_PMRCAP_PMRWBM(pmrcap) \ 259 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK) 260 #define NVME_PMRCAP_PMRTO(pmrcap) \ 261 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK) 262 #define NVME_PMRCAP_CMSS(pmrcap) \ 263 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK) 264 265 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \ 266 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT) 267 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \ 268 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT) 269 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \ 270 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT) 271 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \ 272 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT) 273 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \ 274 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT) 275 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \ 276 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT) 277 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \ 278 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT) 279 280 enum NvmePmrctlShift { 281 PMRCTL_EN_SHIFT = 0, 282 }; 283 284 enum NvmePmrctlMask { 285 PMRCTL_EN_MASK = 0x1, 286 }; 287 288 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK) 289 290 #define NVME_PMRCTL_SET_EN(pmrctl, val) \ 291 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT) 292 293 enum NvmePmrstsShift { 294 PMRSTS_ERR_SHIFT = 0, 295 PMRSTS_NRDY_SHIFT = 8, 296 PMRSTS_HSTS_SHIFT = 9, 297 PMRSTS_CBAI_SHIFT = 12, 298 }; 299 300 enum NvmePmrstsMask { 301 PMRSTS_ERR_MASK = 0xff, 302 PMRSTS_NRDY_MASK = 0x1, 303 PMRSTS_HSTS_MASK = 0x7, 304 PMRSTS_CBAI_MASK = 0x1, 305 }; 306 307 #define NVME_PMRSTS_ERR(pmrsts) \ 308 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK) 309 #define NVME_PMRSTS_NRDY(pmrsts) \ 310 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK) 311 #define NVME_PMRSTS_HSTS(pmrsts) \ 312 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK) 313 #define NVME_PMRSTS_CBAI(pmrsts) \ 314 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK) 315 316 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \ 317 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT) 318 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \ 319 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT) 320 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \ 321 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT) 322 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \ 323 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT) 324 325 enum NvmePmrebsShift { 326 PMREBS_PMRSZU_SHIFT = 0, 327 PMREBS_RBB_SHIFT = 4, 328 PMREBS_PMRWBZ_SHIFT = 8, 329 }; 330 331 enum NvmePmrebsMask { 332 PMREBS_PMRSZU_MASK = 0xf, 333 PMREBS_RBB_MASK = 0x1, 334 PMREBS_PMRWBZ_MASK = 0xffffff, 335 }; 336 337 #define NVME_PMREBS_PMRSZU(pmrebs) \ 338 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK) 339 #define NVME_PMREBS_RBB(pmrebs) \ 340 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK) 341 #define NVME_PMREBS_PMRWBZ(pmrebs) \ 342 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK) 343 344 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \ 345 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT) 346 #define NVME_PMREBS_SET_RBB(pmrebs, val) \ 347 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT) 348 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \ 349 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT) 350 351 enum NvmePmrswtpShift { 352 PMRSWTP_PMRSWTU_SHIFT = 0, 353 PMRSWTP_PMRSWTV_SHIFT = 8, 354 }; 355 356 enum NvmePmrswtpMask { 357 PMRSWTP_PMRSWTU_MASK = 0xf, 358 PMRSWTP_PMRSWTV_MASK = 0xffffff, 359 }; 360 361 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \ 362 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK) 363 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \ 364 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK) 365 366 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \ 367 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT) 368 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ 369 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT) 370 371 enum NvmePmrmscShift { 372 PMRMSC_CMSE_SHIFT = 1, 373 PMRMSC_CBA_SHIFT = 12, 374 }; 375 376 enum NvmePmrmscMask { 377 PMRMSC_CMSE_MASK = 0x1, 378 PMRMSC_CBA_MASK = 0xfffffffffffff, 379 }; 380 381 #define NVME_PMRMSC_CMSE(pmrmsc) \ 382 ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) 383 #define NVME_PMRMSC_CBA(pmrmsc) \ 384 ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) 385 386 #define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ 387 (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) 388 #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ 389 (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) 390 391 enum NvmeSglDescriptorType { 392 NVME_SGL_DESCR_TYPE_DATA_BLOCK = 0x0, 393 NVME_SGL_DESCR_TYPE_BIT_BUCKET = 0x1, 394 NVME_SGL_DESCR_TYPE_SEGMENT = 0x2, 395 NVME_SGL_DESCR_TYPE_LAST_SEGMENT = 0x3, 396 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK = 0x4, 397 398 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC = 0xf, 399 }; 400 401 enum NvmeSglDescriptorSubtype { 402 NVME_SGL_DESCR_SUBTYPE_ADDRESS = 0x0, 403 }; 404 405 typedef struct QEMU_PACKED NvmeSglDescriptor { 406 uint64_t addr; 407 uint32_t len; 408 uint8_t rsvd[3]; 409 uint8_t type; 410 } NvmeSglDescriptor; 411 412 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf) 413 #define NVME_SGL_SUBTYPE(type) (type & 0xf) 414 415 typedef union NvmeCmdDptr { 416 struct { 417 uint64_t prp1; 418 uint64_t prp2; 419 }; 420 421 NvmeSglDescriptor sgl; 422 } NvmeCmdDptr; 423 424 enum NvmePsdt { 425 NVME_PSDT_PRP = 0x0, 426 NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1, 427 NVME_PSDT_SGL_MPTR_SGL = 0x2, 428 }; 429 430 typedef struct QEMU_PACKED NvmeCmd { 431 uint8_t opcode; 432 uint8_t flags; 433 uint16_t cid; 434 uint32_t nsid; 435 uint64_t res1; 436 uint64_t mptr; 437 NvmeCmdDptr dptr; 438 uint32_t cdw10; 439 uint32_t cdw11; 440 uint32_t cdw12; 441 uint32_t cdw13; 442 uint32_t cdw14; 443 uint32_t cdw15; 444 } NvmeCmd; 445 446 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3) 447 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3) 448 449 enum NvmeAdminCommands { 450 NVME_ADM_CMD_DELETE_SQ = 0x00, 451 NVME_ADM_CMD_CREATE_SQ = 0x01, 452 NVME_ADM_CMD_GET_LOG_PAGE = 0x02, 453 NVME_ADM_CMD_DELETE_CQ = 0x04, 454 NVME_ADM_CMD_CREATE_CQ = 0x05, 455 NVME_ADM_CMD_IDENTIFY = 0x06, 456 NVME_ADM_CMD_ABORT = 0x08, 457 NVME_ADM_CMD_SET_FEATURES = 0x09, 458 NVME_ADM_CMD_GET_FEATURES = 0x0a, 459 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c, 460 NVME_ADM_CMD_ACTIVATE_FW = 0x10, 461 NVME_ADM_CMD_DOWNLOAD_FW = 0x11, 462 NVME_ADM_CMD_FORMAT_NVM = 0x80, 463 NVME_ADM_CMD_SECURITY_SEND = 0x81, 464 NVME_ADM_CMD_SECURITY_RECV = 0x82, 465 }; 466 467 enum NvmeIoCommands { 468 NVME_CMD_FLUSH = 0x00, 469 NVME_CMD_WRITE = 0x01, 470 NVME_CMD_READ = 0x02, 471 NVME_CMD_WRITE_UNCOR = 0x04, 472 NVME_CMD_COMPARE = 0x05, 473 NVME_CMD_WRITE_ZEROES = 0x08, 474 NVME_CMD_DSM = 0x09, 475 }; 476 477 typedef struct QEMU_PACKED NvmeDeleteQ { 478 uint8_t opcode; 479 uint8_t flags; 480 uint16_t cid; 481 uint32_t rsvd1[9]; 482 uint16_t qid; 483 uint16_t rsvd10; 484 uint32_t rsvd11[5]; 485 } NvmeDeleteQ; 486 487 typedef struct QEMU_PACKED NvmeCreateCq { 488 uint8_t opcode; 489 uint8_t flags; 490 uint16_t cid; 491 uint32_t rsvd1[5]; 492 uint64_t prp1; 493 uint64_t rsvd8; 494 uint16_t cqid; 495 uint16_t qsize; 496 uint16_t cq_flags; 497 uint16_t irq_vector; 498 uint32_t rsvd12[4]; 499 } NvmeCreateCq; 500 501 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1) 502 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1) 503 504 enum NvmeFlagsCq { 505 NVME_CQ_PC = 1, 506 NVME_CQ_IEN = 2, 507 }; 508 509 typedef struct QEMU_PACKED NvmeCreateSq { 510 uint8_t opcode; 511 uint8_t flags; 512 uint16_t cid; 513 uint32_t rsvd1[5]; 514 uint64_t prp1; 515 uint64_t rsvd8; 516 uint16_t sqid; 517 uint16_t qsize; 518 uint16_t sq_flags; 519 uint16_t cqid; 520 uint32_t rsvd12[4]; 521 } NvmeCreateSq; 522 523 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1) 524 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3) 525 526 enum NvmeFlagsSq { 527 NVME_SQ_PC = 1, 528 529 NVME_SQ_PRIO_URGENT = 0, 530 NVME_SQ_PRIO_HIGH = 1, 531 NVME_SQ_PRIO_NORMAL = 2, 532 NVME_SQ_PRIO_LOW = 3, 533 }; 534 535 typedef struct QEMU_PACKED NvmeIdentify { 536 uint8_t opcode; 537 uint8_t flags; 538 uint16_t cid; 539 uint32_t nsid; 540 uint64_t rsvd2[2]; 541 uint64_t prp1; 542 uint64_t prp2; 543 uint32_t cns; 544 uint32_t rsvd11[5]; 545 } NvmeIdentify; 546 547 typedef struct QEMU_PACKED NvmeRwCmd { 548 uint8_t opcode; 549 uint8_t flags; 550 uint16_t cid; 551 uint32_t nsid; 552 uint64_t rsvd2; 553 uint64_t mptr; 554 NvmeCmdDptr dptr; 555 uint64_t slba; 556 uint16_t nlb; 557 uint16_t control; 558 uint32_t dsmgmt; 559 uint32_t reftag; 560 uint16_t apptag; 561 uint16_t appmask; 562 } NvmeRwCmd; 563 564 enum { 565 NVME_RW_LR = 1 << 15, 566 NVME_RW_FUA = 1 << 14, 567 NVME_RW_DSM_FREQ_UNSPEC = 0, 568 NVME_RW_DSM_FREQ_TYPICAL = 1, 569 NVME_RW_DSM_FREQ_RARE = 2, 570 NVME_RW_DSM_FREQ_READS = 3, 571 NVME_RW_DSM_FREQ_WRITES = 4, 572 NVME_RW_DSM_FREQ_RW = 5, 573 NVME_RW_DSM_FREQ_ONCE = 6, 574 NVME_RW_DSM_FREQ_PREFETCH = 7, 575 NVME_RW_DSM_FREQ_TEMP = 8, 576 NVME_RW_DSM_LATENCY_NONE = 0 << 4, 577 NVME_RW_DSM_LATENCY_IDLE = 1 << 4, 578 NVME_RW_DSM_LATENCY_NORM = 2 << 4, 579 NVME_RW_DSM_LATENCY_LOW = 3 << 4, 580 NVME_RW_DSM_SEQ_REQ = 1 << 6, 581 NVME_RW_DSM_COMPRESSED = 1 << 7, 582 NVME_RW_PRINFO_PRACT = 1 << 13, 583 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, 584 NVME_RW_PRINFO_PRCHK_APP = 1 << 11, 585 NVME_RW_PRINFO_PRCHK_REF = 1 << 10, 586 }; 587 588 typedef struct QEMU_PACKED NvmeDsmCmd { 589 uint8_t opcode; 590 uint8_t flags; 591 uint16_t cid; 592 uint32_t nsid; 593 uint64_t rsvd2[2]; 594 NvmeCmdDptr dptr; 595 uint32_t nr; 596 uint32_t attributes; 597 uint32_t rsvd12[4]; 598 } NvmeDsmCmd; 599 600 enum { 601 NVME_DSMGMT_IDR = 1 << 0, 602 NVME_DSMGMT_IDW = 1 << 1, 603 NVME_DSMGMT_AD = 1 << 2, 604 }; 605 606 typedef struct QEMU_PACKED NvmeDsmRange { 607 uint32_t cattr; 608 uint32_t nlb; 609 uint64_t slba; 610 } NvmeDsmRange; 611 612 enum NvmeAsyncEventRequest { 613 NVME_AER_TYPE_ERROR = 0, 614 NVME_AER_TYPE_SMART = 1, 615 NVME_AER_TYPE_IO_SPECIFIC = 6, 616 NVME_AER_TYPE_VENDOR_SPECIFIC = 7, 617 NVME_AER_INFO_ERR_INVALID_DB_REGISTER = 0, 618 NVME_AER_INFO_ERR_INVALID_DB_VALUE = 1, 619 NVME_AER_INFO_ERR_DIAG_FAIL = 2, 620 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3, 621 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4, 622 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5, 623 NVME_AER_INFO_SMART_RELIABILITY = 0, 624 NVME_AER_INFO_SMART_TEMP_THRESH = 1, 625 NVME_AER_INFO_SMART_SPARE_THRESH = 2, 626 }; 627 628 typedef struct QEMU_PACKED NvmeAerResult { 629 uint8_t event_type; 630 uint8_t event_info; 631 uint8_t log_page; 632 uint8_t resv; 633 } NvmeAerResult; 634 635 typedef struct QEMU_PACKED NvmeCqe { 636 uint32_t result; 637 uint32_t rsvd; 638 uint16_t sq_head; 639 uint16_t sq_id; 640 uint16_t cid; 641 uint16_t status; 642 } NvmeCqe; 643 644 enum NvmeStatusCodes { 645 NVME_SUCCESS = 0x0000, 646 NVME_INVALID_OPCODE = 0x0001, 647 NVME_INVALID_FIELD = 0x0002, 648 NVME_CID_CONFLICT = 0x0003, 649 NVME_DATA_TRAS_ERROR = 0x0004, 650 NVME_POWER_LOSS_ABORT = 0x0005, 651 NVME_INTERNAL_DEV_ERROR = 0x0006, 652 NVME_CMD_ABORT_REQ = 0x0007, 653 NVME_CMD_ABORT_SQ_DEL = 0x0008, 654 NVME_CMD_ABORT_FAILED_FUSE = 0x0009, 655 NVME_CMD_ABORT_MISSING_FUSE = 0x000a, 656 NVME_INVALID_NSID = 0x000b, 657 NVME_CMD_SEQ_ERROR = 0x000c, 658 NVME_INVALID_SGL_SEG_DESCR = 0x000d, 659 NVME_INVALID_NUM_SGL_DESCRS = 0x000e, 660 NVME_DATA_SGL_LEN_INVALID = 0x000f, 661 NVME_MD_SGL_LEN_INVALID = 0x0010, 662 NVME_SGL_DESCR_TYPE_INVALID = 0x0011, 663 NVME_INVALID_USE_OF_CMB = 0x0012, 664 NVME_INVALID_PRP_OFFSET = 0x0013, 665 NVME_LBA_RANGE = 0x0080, 666 NVME_CAP_EXCEEDED = 0x0081, 667 NVME_NS_NOT_READY = 0x0082, 668 NVME_NS_RESV_CONFLICT = 0x0083, 669 NVME_INVALID_CQID = 0x0100, 670 NVME_INVALID_QID = 0x0101, 671 NVME_MAX_QSIZE_EXCEEDED = 0x0102, 672 NVME_ACL_EXCEEDED = 0x0103, 673 NVME_RESERVED = 0x0104, 674 NVME_AER_LIMIT_EXCEEDED = 0x0105, 675 NVME_INVALID_FW_SLOT = 0x0106, 676 NVME_INVALID_FW_IMAGE = 0x0107, 677 NVME_INVALID_IRQ_VECTOR = 0x0108, 678 NVME_INVALID_LOG_ID = 0x0109, 679 NVME_INVALID_FORMAT = 0x010a, 680 NVME_FW_REQ_RESET = 0x010b, 681 NVME_INVALID_QUEUE_DEL = 0x010c, 682 NVME_FID_NOT_SAVEABLE = 0x010d, 683 NVME_FEAT_NOT_CHANGEABLE = 0x010e, 684 NVME_FEAT_NOT_NS_SPEC = 0x010f, 685 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110, 686 NVME_CONFLICTING_ATTRS = 0x0180, 687 NVME_INVALID_PROT_INFO = 0x0181, 688 NVME_WRITE_TO_RO = 0x0182, 689 NVME_WRITE_FAULT = 0x0280, 690 NVME_UNRECOVERED_READ = 0x0281, 691 NVME_E2E_GUARD_ERROR = 0x0282, 692 NVME_E2E_APP_ERROR = 0x0283, 693 NVME_E2E_REF_ERROR = 0x0284, 694 NVME_CMP_FAILURE = 0x0285, 695 NVME_ACCESS_DENIED = 0x0286, 696 NVME_MORE = 0x2000, 697 NVME_DNR = 0x4000, 698 NVME_NO_COMPLETE = 0xffff, 699 }; 700 701 typedef struct QEMU_PACKED NvmeFwSlotInfoLog { 702 uint8_t afi; 703 uint8_t reserved1[7]; 704 uint8_t frs1[8]; 705 uint8_t frs2[8]; 706 uint8_t frs3[8]; 707 uint8_t frs4[8]; 708 uint8_t frs5[8]; 709 uint8_t frs6[8]; 710 uint8_t frs7[8]; 711 uint8_t reserved2[448]; 712 } NvmeFwSlotInfoLog; 713 714 typedef struct QEMU_PACKED NvmeErrorLog { 715 uint64_t error_count; 716 uint16_t sqid; 717 uint16_t cid; 718 uint16_t status_field; 719 uint16_t param_error_location; 720 uint64_t lba; 721 uint32_t nsid; 722 uint8_t vs; 723 uint8_t resv[35]; 724 } NvmeErrorLog; 725 726 typedef struct QEMU_PACKED NvmeSmartLog { 727 uint8_t critical_warning; 728 uint16_t temperature; 729 uint8_t available_spare; 730 uint8_t available_spare_threshold; 731 uint8_t percentage_used; 732 uint8_t reserved1[26]; 733 uint64_t data_units_read[2]; 734 uint64_t data_units_written[2]; 735 uint64_t host_read_commands[2]; 736 uint64_t host_write_commands[2]; 737 uint64_t controller_busy_time[2]; 738 uint64_t power_cycles[2]; 739 uint64_t power_on_hours[2]; 740 uint64_t unsafe_shutdowns[2]; 741 uint64_t media_errors[2]; 742 uint64_t number_of_error_log_entries[2]; 743 uint8_t reserved2[320]; 744 } NvmeSmartLog; 745 746 enum NvmeSmartWarn { 747 NVME_SMART_SPARE = 1 << 0, 748 NVME_SMART_TEMPERATURE = 1 << 1, 749 NVME_SMART_RELIABILITY = 1 << 2, 750 NVME_SMART_MEDIA_READ_ONLY = 1 << 3, 751 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4, 752 }; 753 754 enum NvmeLogIdentifier { 755 NVME_LOG_ERROR_INFO = 0x01, 756 NVME_LOG_SMART_INFO = 0x02, 757 NVME_LOG_FW_SLOT_INFO = 0x03, 758 }; 759 760 typedef struct QEMU_PACKED NvmePSD { 761 uint16_t mp; 762 uint16_t reserved; 763 uint32_t enlat; 764 uint32_t exlat; 765 uint8_t rrt; 766 uint8_t rrl; 767 uint8_t rwt; 768 uint8_t rwl; 769 uint8_t resv[16]; 770 } NvmePSD; 771 772 #define NVME_IDENTIFY_DATA_SIZE 4096 773 774 enum { 775 NVME_ID_CNS_NS = 0x0, 776 NVME_ID_CNS_CTRL = 0x1, 777 NVME_ID_CNS_NS_ACTIVE_LIST = 0x2, 778 NVME_ID_CNS_NS_DESCR_LIST = 0x3, 779 }; 780 781 typedef struct QEMU_PACKED NvmeIdCtrl { 782 uint16_t vid; 783 uint16_t ssvid; 784 uint8_t sn[20]; 785 uint8_t mn[40]; 786 uint8_t fr[8]; 787 uint8_t rab; 788 uint8_t ieee[3]; 789 uint8_t cmic; 790 uint8_t mdts; 791 uint16_t cntlid; 792 uint32_t ver; 793 uint32_t rtd3r; 794 uint32_t rtd3e; 795 uint32_t oaes; 796 uint32_t ctratt; 797 uint8_t rsvd100[12]; 798 uint8_t fguid[16]; 799 uint8_t rsvd128[128]; 800 uint16_t oacs; 801 uint8_t acl; 802 uint8_t aerl; 803 uint8_t frmw; 804 uint8_t lpa; 805 uint8_t elpe; 806 uint8_t npss; 807 uint8_t avscc; 808 uint8_t apsta; 809 uint16_t wctemp; 810 uint16_t cctemp; 811 uint16_t mtfa; 812 uint32_t hmpre; 813 uint32_t hmmin; 814 uint8_t tnvmcap[16]; 815 uint8_t unvmcap[16]; 816 uint32_t rpmbs; 817 uint16_t edstt; 818 uint8_t dsto; 819 uint8_t fwug; 820 uint16_t kas; 821 uint16_t hctma; 822 uint16_t mntmt; 823 uint16_t mxtmt; 824 uint32_t sanicap; 825 uint8_t rsvd332[180]; 826 uint8_t sqes; 827 uint8_t cqes; 828 uint16_t maxcmd; 829 uint32_t nn; 830 uint16_t oncs; 831 uint16_t fuses; 832 uint8_t fna; 833 uint8_t vwc; 834 uint16_t awun; 835 uint16_t awupf; 836 uint8_t nvscc; 837 uint8_t rsvd531; 838 uint16_t acwu; 839 uint8_t rsvd534[2]; 840 uint32_t sgls; 841 uint8_t rsvd540[228]; 842 uint8_t subnqn[256]; 843 uint8_t rsvd1024[1024]; 844 NvmePSD psd[32]; 845 uint8_t vs[1024]; 846 } NvmeIdCtrl; 847 848 enum NvmeIdCtrlOacs { 849 NVME_OACS_SECURITY = 1 << 0, 850 NVME_OACS_FORMAT = 1 << 1, 851 NVME_OACS_FW = 1 << 2, 852 }; 853 854 enum NvmeIdCtrlOncs { 855 NVME_ONCS_COMPARE = 1 << 0, 856 NVME_ONCS_WRITE_UNCORR = 1 << 1, 857 NVME_ONCS_DSM = 1 << 2, 858 NVME_ONCS_WRITE_ZEROES = 1 << 3, 859 NVME_ONCS_FEATURES = 1 << 4, 860 NVME_ONCS_RESRVATIONS = 1 << 5, 861 NVME_ONCS_TIMESTAMP = 1 << 6, 862 }; 863 864 enum NvmeIdCtrlFrmw { 865 NVME_FRMW_SLOT1_RO = 1 << 0, 866 }; 867 868 enum NvmeIdCtrlLpa { 869 NVME_LPA_NS_SMART = 1 << 0, 870 NVME_LPA_EXTENDED = 1 << 2, 871 }; 872 873 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf) 874 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf) 875 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf) 876 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf) 877 878 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0) 879 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0) 880 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1) 881 #define NVME_CTRL_SGLS_KEYED (0x1 << 2) 882 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16) 883 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17) 884 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18) 885 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19) 886 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20) 887 888 #define NVME_ARB_AB(arb) (arb & 0x7) 889 #define NVME_ARB_AB_NOLIMIT 0x7 890 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff) 891 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff) 892 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff) 893 894 #define NVME_INTC_THR(intc) (intc & 0xff) 895 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) 896 897 #define NVME_INTVC_NOCOALESCING (0x1 << 16) 898 899 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) 900 #define NVME_TEMP_THSEL_OVER 0x0 901 #define NVME_TEMP_THSEL_UNDER 0x1 902 903 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) 904 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0 905 906 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff) 907 908 #define NVME_AEC_SMART(aec) (aec & 0xff) 909 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) 910 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) 911 912 enum NvmeFeatureIds { 913 NVME_ARBITRATION = 0x1, 914 NVME_POWER_MANAGEMENT = 0x2, 915 NVME_LBA_RANGE_TYPE = 0x3, 916 NVME_TEMPERATURE_THRESHOLD = 0x4, 917 NVME_ERROR_RECOVERY = 0x5, 918 NVME_VOLATILE_WRITE_CACHE = 0x6, 919 NVME_NUMBER_OF_QUEUES = 0x7, 920 NVME_INTERRUPT_COALESCING = 0x8, 921 NVME_INTERRUPT_VECTOR_CONF = 0x9, 922 NVME_WRITE_ATOMICITY = 0xa, 923 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb, 924 NVME_TIMESTAMP = 0xe, 925 NVME_SOFTWARE_PROGRESS_MARKER = 0x80, 926 NVME_FID_MAX = 0x100, 927 }; 928 929 typedef enum NvmeFeatureCap { 930 NVME_FEAT_CAP_SAVE = 1 << 0, 931 NVME_FEAT_CAP_NS = 1 << 1, 932 NVME_FEAT_CAP_CHANGE = 1 << 2, 933 } NvmeFeatureCap; 934 935 typedef enum NvmeGetFeatureSelect { 936 NVME_GETFEAT_SELECT_CURRENT = 0x0, 937 NVME_GETFEAT_SELECT_DEFAULT = 0x1, 938 NVME_GETFEAT_SELECT_SAVED = 0x2, 939 NVME_GETFEAT_SELECT_CAP = 0x3, 940 } NvmeGetFeatureSelect; 941 942 #define NVME_GETSETFEAT_FID_MASK 0xff 943 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK) 944 945 #define NVME_GETFEAT_SELECT_SHIFT 8 946 #define NVME_GETFEAT_SELECT_MASK 0x7 947 #define NVME_GETFEAT_SELECT(dw10) \ 948 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK) 949 950 #define NVME_SETFEAT_SAVE_SHIFT 31 951 #define NVME_SETFEAT_SAVE_MASK 0x1 952 #define NVME_SETFEAT_SAVE(dw10) \ 953 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK) 954 955 typedef struct QEMU_PACKED NvmeRangeType { 956 uint8_t type; 957 uint8_t attributes; 958 uint8_t rsvd2[14]; 959 uint64_t slba; 960 uint64_t nlb; 961 uint8_t guid[16]; 962 uint8_t rsvd48[16]; 963 } NvmeRangeType; 964 965 typedef struct QEMU_PACKED NvmeLBAF { 966 uint16_t ms; 967 uint8_t ds; 968 uint8_t rp; 969 } NvmeLBAF; 970 971 #define NVME_NSID_BROADCAST 0xffffffff 972 973 typedef struct QEMU_PACKED NvmeIdNs { 974 uint64_t nsze; 975 uint64_t ncap; 976 uint64_t nuse; 977 uint8_t nsfeat; 978 uint8_t nlbaf; 979 uint8_t flbas; 980 uint8_t mc; 981 uint8_t dpc; 982 uint8_t dps; 983 uint8_t nmic; 984 uint8_t rescap; 985 uint8_t fpi; 986 uint8_t dlfeat; 987 uint16_t nawun; 988 uint16_t nawupf; 989 uint16_t nacwu; 990 uint16_t nabsn; 991 uint16_t nabo; 992 uint16_t nabspf; 993 uint16_t noiob; 994 uint8_t nvmcap[16]; 995 uint8_t rsvd64[40]; 996 uint8_t nguid[16]; 997 uint64_t eui64; 998 NvmeLBAF lbaf[16]; 999 uint8_t rsvd192[192]; 1000 uint8_t vs[3712]; 1001 } NvmeIdNs; 1002 1003 typedef struct QEMU_PACKED NvmeIdNsDescr { 1004 uint8_t nidt; 1005 uint8_t nidl; 1006 uint8_t rsvd2[2]; 1007 } NvmeIdNsDescr; 1008 1009 enum { 1010 NVME_NIDT_EUI64_LEN = 8, 1011 NVME_NIDT_NGUID_LEN = 16, 1012 NVME_NIDT_UUID_LEN = 16, 1013 }; 1014 1015 enum NvmeNsIdentifierType { 1016 NVME_NIDT_EUI64 = 0x1, 1017 NVME_NIDT_NGUID = 0x2, 1018 NVME_NIDT_UUID = 0x3, 1019 }; 1020 1021 /*Deallocate Logical Block Features*/ 1022 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) 1023 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) 1024 1025 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7) 1026 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0 1027 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1 1028 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2 1029 1030 1031 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) 1032 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) 1033 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) 1034 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) 1035 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1)) 1036 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1) 1037 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1) 1038 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1) 1039 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1) 1040 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1)) 1041 #define NVME_ID_NS_DPC_TYPE_MASK 0x7 1042 1043 enum NvmeIdNsDps { 1044 DPS_TYPE_NONE = 0, 1045 DPS_TYPE_1 = 1, 1046 DPS_TYPE_2 = 2, 1047 DPS_TYPE_3 = 3, 1048 DPS_TYPE_MASK = 0x7, 1049 DPS_FIRST_EIGHT = 8, 1050 }; 1051 1052 static inline void _nvme_check_size(void) 1053 { 1054 QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096); 1055 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4); 1056 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16); 1057 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16); 1058 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64); 1059 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64); 1060 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64); 1061 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64); 1062 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64); 1063 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64); 1064 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64); 1065 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64); 1066 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64); 1067 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512); 1068 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512); 1069 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096); 1070 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096); 1071 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16); 1072 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4); 1073 } 1074 #endif 1075