1 /* 2 * TCG CPU-specific operations 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef TCG_CPU_OPS_H 11 #define TCG_CPU_OPS_H 12 13 #include "exec/breakpoint.h" 14 #include "exec/hwaddr.h" 15 #include "exec/memattrs.h" 16 #include "exec/memop.h" 17 #include "exec/mmu-access-type.h" 18 #include "exec/vaddr.h" 19 #include "tcg/tcg-mo.h" 20 21 struct TCGCPUOps { 22 /** 23 * mttcg_supported: multi-threaded TCG is supported 24 * 25 * Target (TCG frontend) supports: 26 * - atomic instructions 27 * - memory ordering primitives (barriers) 28 */ 29 bool mttcg_supported; 30 31 /** 32 * @precise_smc: Stores which modify code within the current TB force 33 * the TB to exit; the next executed instruction will see 34 * the result of the store. 35 */ 36 bool precise_smc; 37 38 /** 39 * @guest_default_memory_order: default barrier that is required 40 * for the guest memory ordering. 41 */ 42 TCGBar guest_default_memory_order; 43 44 /** 45 * @initialize: Initialize TCG state 46 * 47 * Called when the first CPU is realized. 48 */ 49 void (*initialize)(void); 50 /** 51 * @translate_code: Translate guest instructions to TCGOps 52 * @cpu: cpu context 53 * @tb: translation block 54 * @max_insns: max number of instructions to translate 55 * @pc: guest virtual program counter address 56 * @host_pc: host physical program counter address 57 * 58 * This function must be provided by the target, which should create 59 * the target-specific DisasContext, and then invoke translator_loop. 60 */ 61 void (*translate_code)(CPUState *cpu, TranslationBlock *tb, 62 int *max_insns, vaddr pc, void *host_pc); 63 /** 64 * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock 65 * 66 * This is called when we abandon execution of a TB before starting it, 67 * and must set all parts of the CPU state which the previous TB in the 68 * chain may not have updated. 69 * By default, when this is NULL, a call is made to @set_pc(tb->pc). 70 * 71 * If more state needs to be restored, the target must implement a 72 * function to restore all the state, and register it here. 73 */ 74 void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb); 75 /** 76 * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn 77 * 78 * This is called when we unwind state in the middle of a TB, 79 * usually before raising an exception. Set all part of the CPU 80 * state which are tracked insn-by-insn in the target-specific 81 * arguments to start_insn, passed as @data. 82 */ 83 void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb, 84 const uint64_t *data); 85 86 /** @cpu_exec_enter: Callback for cpu_exec preparation */ 87 void (*cpu_exec_enter)(CPUState *cpu); 88 /** @cpu_exec_exit: Callback for cpu_exec cleanup */ 89 void (*cpu_exec_exit)(CPUState *cpu); 90 /** @debug_excp_handler: Callback for handling debug exceptions */ 91 void (*debug_excp_handler)(CPUState *cpu); 92 93 /** @mmu_index: Callback for choosing softmmu mmu index */ 94 int (*mmu_index)(CPUState *cpu, bool ifetch); 95 96 #ifdef CONFIG_USER_ONLY 97 /** 98 * @fake_user_interrupt: Callback for 'fake exception' handling. 99 * 100 * Simulate 'fake exception' which will be handled outside the 101 * cpu execution loop (hack for x86 user mode). 102 */ 103 void (*fake_user_interrupt)(CPUState *cpu); 104 105 /** 106 * record_sigsegv: 107 * @cpu: cpu context 108 * @addr: faulting guest address 109 * @access_type: access was read/write/execute 110 * @maperr: true for invalid page, false for permission fault 111 * @ra: host pc for unwinding 112 * 113 * We are about to raise SIGSEGV with si_code set for @maperr, 114 * and si_addr set for @addr. Record anything further needed 115 * for the signal ucontext_t. 116 * 117 * If the emulated kernel does not provide anything to the signal 118 * handler with anything besides the user context registers, and 119 * the siginfo_t, then this hook need do nothing and may be omitted. 120 * Otherwise, record the data and return; the caller will raise 121 * the signal, unwind the cpu state, and return to the main loop. 122 * 123 * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided 124 * so that a "normal" cpu exception can be raised. In this case, 125 * the signal must be raised by the architecture cpu_loop. 126 */ 127 void (*record_sigsegv)(CPUState *cpu, vaddr addr, 128 MMUAccessType access_type, 129 bool maperr, uintptr_t ra); 130 /** 131 * record_sigbus: 132 * @cpu: cpu context 133 * @addr: misaligned guest address 134 * @access_type: access was read/write/execute 135 * @ra: host pc for unwinding 136 * 137 * We are about to raise SIGBUS with si_code BUS_ADRALN, 138 * and si_addr set for @addr. Record anything further needed 139 * for the signal ucontext_t. 140 * 141 * If the emulated kernel does not provide the signal handler with 142 * anything besides the user context registers, and the siginfo_t, 143 * then this hook need do nothing and may be omitted. 144 * Otherwise, record the data and return; the caller will raise 145 * the signal, unwind the cpu state, and return to the main loop. 146 * 147 * If it is simpler to re-use the sysemu do_unaligned_access code, 148 * @ra is provided so that a "normal" cpu exception can be raised. 149 * In this case, the signal must be raised by the architecture cpu_loop. 150 */ 151 void (*record_sigbus)(CPUState *cpu, vaddr addr, 152 MMUAccessType access_type, uintptr_t ra); 153 #else 154 /** @do_interrupt: Callback for interrupt handling. */ 155 void (*do_interrupt)(CPUState *cpu); 156 /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ 157 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 158 /** 159 * @cpu_exec_halt: Callback for handling halt in cpu_exec. 160 * 161 * The target CPU should do any special processing here that it needs 162 * to do when the CPU is in the halted state. 163 * 164 * Return true to indicate that the CPU should now leave halt, false 165 * if it should remain in the halted state. (This should generally 166 * be the same value that cpu_has_work() would return.) 167 * 168 * This method must be provided. If the target does not need to 169 * do anything special for halt, the same function used for its 170 * SysemuCPUOps::has_work method can be used here, as they have the 171 * same function signature. 172 */ 173 bool (*cpu_exec_halt)(CPUState *cpu); 174 /** 175 * @tlb_fill_align: Handle a softmmu tlb miss 176 * @cpu: cpu context 177 * @out: output page properties 178 * @addr: virtual address 179 * @access_type: read, write or execute 180 * @mmu_idx: mmu context 181 * @memop: memory operation for the access 182 * @size: memory access size, or 0 for whole page 183 * @probe: test only, no fault 184 * @ra: host return address for exception unwind 185 * 186 * If the access is valid, fill in @out and return true. 187 * Otherwise if probe is true, return false. 188 * Otherwise raise an exception and do not return. 189 * 190 * The alignment check for the access is deferred to this hook, 191 * so that the target can determine the priority of any alignment 192 * fault with respect to other potential faults from paging. 193 * Zero may be passed for @memop to skip any alignment check 194 * for non-memory-access operations such as probing. 195 */ 196 bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, 197 MMUAccessType access_type, int mmu_idx, 198 MemOp memop, int size, bool probe, uintptr_t ra); 199 /** 200 * @tlb_fill: Handle a softmmu tlb miss 201 * 202 * If the access is valid, call tlb_set_page and return true; 203 * if the access is invalid and probe is true, return false; 204 * otherwise raise an exception and do not return. 205 */ 206 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, 207 MMUAccessType access_type, int mmu_idx, 208 bool probe, uintptr_t retaddr); 209 /** 210 * @do_transaction_failed: Callback for handling failed memory transactions 211 * (ie bus faults or external aborts; not MMU faults) 212 */ 213 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 214 unsigned size, MMUAccessType access_type, 215 int mmu_idx, MemTxAttrs attrs, 216 MemTxResult response, uintptr_t retaddr); 217 /** 218 * @do_unaligned_access: Callback for unaligned access handling 219 * The callback must exit via raising an exception. 220 */ 221 G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 222 MMUAccessType access_type, 223 int mmu_idx, uintptr_t retaddr); 224 225 /** 226 * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM 227 */ 228 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 229 230 /** 231 * @debug_check_watchpoint: return true if the architectural 232 * watchpoint whose address has matched should really fire, used by ARM 233 * and RISC-V 234 */ 235 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 236 237 /** 238 * @debug_check_breakpoint: return true if the architectural 239 * breakpoint whose PC has matched should really fire. 240 */ 241 bool (*debug_check_breakpoint)(CPUState *cpu); 242 243 /** 244 * @io_recompile_replay_branch: Callback for cpu_io_recompile. 245 * 246 * The cpu has been stopped, and cpu_restore_state_from_tb has been 247 * called. If the faulting instruction is in a delay slot, and the 248 * target architecture requires re-execution of the branch, then 249 * adjust the cpu state as required and return true. 250 */ 251 bool (*io_recompile_replay_branch)(CPUState *cpu, 252 const TranslationBlock *tb); 253 /** 254 * @need_replay_interrupt: Return %true if @interrupt_request 255 * needs to be recorded for replay purposes. 256 */ 257 bool (*need_replay_interrupt)(int interrupt_request); 258 #endif /* !CONFIG_USER_ONLY */ 259 }; 260 261 #if defined(CONFIG_USER_ONLY) 262 263 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 264 MemTxAttrs atr, int fl, uintptr_t ra) 265 { 266 } 267 268 static inline int cpu_watchpoint_address_matches(CPUState *cpu, 269 vaddr addr, vaddr len) 270 { 271 return 0; 272 } 273 274 #else 275 276 /** 277 * cpu_check_watchpoint: 278 * @cpu: cpu context 279 * @addr: guest virtual address 280 * @len: access length 281 * @attrs: memory access attributes 282 * @flags: watchpoint access type 283 * @ra: unwind return address 284 * 285 * Check for a watchpoint hit in [addr, addr+len) of the type 286 * specified by @flags. Exit via exception with a hit. 287 */ 288 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 289 MemTxAttrs attrs, int flags, uintptr_t ra); 290 291 /** 292 * cpu_watchpoint_address_matches: 293 * @cpu: cpu context 294 * @addr: guest virtual address 295 * @len: access length 296 * 297 * Return the watchpoint flags that apply to [addr, addr+len). 298 * If no watchpoint is registered for the range, the result is 0. 299 */ 300 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); 301 302 #endif 303 304 #endif /* TCG_CPU_OPS_H */ 305