1 /* 2 * TCG CPU-specific operations 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef TCG_CPU_OPS_H 11 #define TCG_CPU_OPS_H 12 13 #include "exec/breakpoint.h" 14 #include "exec/hwaddr.h" 15 #include "exec/memattrs.h" 16 #include "exec/memop.h" 17 #include "exec/mmu-access-type.h" 18 #include "exec/vaddr.h" 19 20 struct TCGCPUOps { 21 /** 22 * @initialize: Initialize TCG state 23 * 24 * Called when the first CPU is realized. 25 */ 26 void (*initialize)(void); 27 /** 28 * @translate_code: Translate guest instructions to TCGOps 29 * @cpu: cpu context 30 * @tb: translation block 31 * @max_insns: max number of instructions to translate 32 * @pc: guest virtual program counter address 33 * @host_pc: host physical program counter address 34 * 35 * This function must be provided by the target, which should create 36 * the target-specific DisasContext, and then invoke translator_loop. 37 */ 38 void (*translate_code)(CPUState *cpu, TranslationBlock *tb, 39 int *max_insns, vaddr pc, void *host_pc); 40 /** 41 * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock 42 * 43 * This is called when we abandon execution of a TB before starting it, 44 * and must set all parts of the CPU state which the previous TB in the 45 * chain may not have updated. 46 * By default, when this is NULL, a call is made to @set_pc(tb->pc). 47 * 48 * If more state needs to be restored, the target must implement a 49 * function to restore all the state, and register it here. 50 */ 51 void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb); 52 /** 53 * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn 54 * 55 * This is called when we unwind state in the middle of a TB, 56 * usually before raising an exception. Set all part of the CPU 57 * state which are tracked insn-by-insn in the target-specific 58 * arguments to start_insn, passed as @data. 59 */ 60 void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb, 61 const uint64_t *data); 62 63 /** @cpu_exec_enter: Callback for cpu_exec preparation */ 64 void (*cpu_exec_enter)(CPUState *cpu); 65 /** @cpu_exec_exit: Callback for cpu_exec cleanup */ 66 void (*cpu_exec_exit)(CPUState *cpu); 67 /** @debug_excp_handler: Callback for handling debug exceptions */ 68 void (*debug_excp_handler)(CPUState *cpu); 69 70 /** @mmu_index: Callback for choosing softmmu mmu index */ 71 int (*mmu_index)(CPUState *cpu, bool ifetch); 72 73 #ifdef CONFIG_USER_ONLY 74 /** 75 * @fake_user_interrupt: Callback for 'fake exception' handling. 76 * 77 * Simulate 'fake exception' which will be handled outside the 78 * cpu execution loop (hack for x86 user mode). 79 */ 80 void (*fake_user_interrupt)(CPUState *cpu); 81 82 /** 83 * record_sigsegv: 84 * @cpu: cpu context 85 * @addr: faulting guest address 86 * @access_type: access was read/write/execute 87 * @maperr: true for invalid page, false for permission fault 88 * @ra: host pc for unwinding 89 * 90 * We are about to raise SIGSEGV with si_code set for @maperr, 91 * and si_addr set for @addr. Record anything further needed 92 * for the signal ucontext_t. 93 * 94 * If the emulated kernel does not provide anything to the signal 95 * handler with anything besides the user context registers, and 96 * the siginfo_t, then this hook need do nothing and may be omitted. 97 * Otherwise, record the data and return; the caller will raise 98 * the signal, unwind the cpu state, and return to the main loop. 99 * 100 * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided 101 * so that a "normal" cpu exception can be raised. In this case, 102 * the signal must be raised by the architecture cpu_loop. 103 */ 104 void (*record_sigsegv)(CPUState *cpu, vaddr addr, 105 MMUAccessType access_type, 106 bool maperr, uintptr_t ra); 107 /** 108 * record_sigbus: 109 * @cpu: cpu context 110 * @addr: misaligned guest address 111 * @access_type: access was read/write/execute 112 * @ra: host pc for unwinding 113 * 114 * We are about to raise SIGBUS with si_code BUS_ADRALN, 115 * and si_addr set for @addr. Record anything further needed 116 * for the signal ucontext_t. 117 * 118 * If the emulated kernel does not provide the signal handler with 119 * anything besides the user context registers, and the siginfo_t, 120 * then this hook need do nothing and may be omitted. 121 * Otherwise, record the data and return; the caller will raise 122 * the signal, unwind the cpu state, and return to the main loop. 123 * 124 * If it is simpler to re-use the sysemu do_unaligned_access code, 125 * @ra is provided so that a "normal" cpu exception can be raised. 126 * In this case, the signal must be raised by the architecture cpu_loop. 127 */ 128 void (*record_sigbus)(CPUState *cpu, vaddr addr, 129 MMUAccessType access_type, uintptr_t ra); 130 #else 131 /** @do_interrupt: Callback for interrupt handling. */ 132 void (*do_interrupt)(CPUState *cpu); 133 /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ 134 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 135 /** 136 * @cpu_exec_halt: Callback for handling halt in cpu_exec. 137 * 138 * The target CPU should do any special processing here that it needs 139 * to do when the CPU is in the halted state. 140 * 141 * Return true to indicate that the CPU should now leave halt, false 142 * if it should remain in the halted state. (This should generally 143 * be the same value that cpu_has_work() would return.) 144 * 145 * This method must be provided. If the target does not need to 146 * do anything special for halt, the same function used for its 147 * SysemuCPUOps::has_work method can be used here, as they have the 148 * same function signature. 149 */ 150 bool (*cpu_exec_halt)(CPUState *cpu); 151 /** 152 * @tlb_fill_align: Handle a softmmu tlb miss 153 * @cpu: cpu context 154 * @out: output page properties 155 * @addr: virtual address 156 * @access_type: read, write or execute 157 * @mmu_idx: mmu context 158 * @memop: memory operation for the access 159 * @size: memory access size, or 0 for whole page 160 * @probe: test only, no fault 161 * @ra: host return address for exception unwind 162 * 163 * If the access is valid, fill in @out and return true. 164 * Otherwise if probe is true, return false. 165 * Otherwise raise an exception and do not return. 166 * 167 * The alignment check for the access is deferred to this hook, 168 * so that the target can determine the priority of any alignment 169 * fault with respect to other potential faults from paging. 170 * Zero may be passed for @memop to skip any alignment check 171 * for non-memory-access operations such as probing. 172 */ 173 bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, 174 MMUAccessType access_type, int mmu_idx, 175 MemOp memop, int size, bool probe, uintptr_t ra); 176 /** 177 * @tlb_fill: Handle a softmmu tlb miss 178 * 179 * If the access is valid, call tlb_set_page and return true; 180 * if the access is invalid and probe is true, return false; 181 * otherwise raise an exception and do not return. 182 */ 183 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, 184 MMUAccessType access_type, int mmu_idx, 185 bool probe, uintptr_t retaddr); 186 /** 187 * @do_transaction_failed: Callback for handling failed memory transactions 188 * (ie bus faults or external aborts; not MMU faults) 189 */ 190 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 191 unsigned size, MMUAccessType access_type, 192 int mmu_idx, MemTxAttrs attrs, 193 MemTxResult response, uintptr_t retaddr); 194 /** 195 * @do_unaligned_access: Callback for unaligned access handling 196 * The callback must exit via raising an exception. 197 */ 198 G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 199 MMUAccessType access_type, 200 int mmu_idx, uintptr_t retaddr); 201 202 /** 203 * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM 204 */ 205 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 206 207 /** 208 * @debug_check_watchpoint: return true if the architectural 209 * watchpoint whose address has matched should really fire, used by ARM 210 * and RISC-V 211 */ 212 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 213 214 /** 215 * @debug_check_breakpoint: return true if the architectural 216 * breakpoint whose PC has matched should really fire. 217 */ 218 bool (*debug_check_breakpoint)(CPUState *cpu); 219 220 /** 221 * @io_recompile_replay_branch: Callback for cpu_io_recompile. 222 * 223 * The cpu has been stopped, and cpu_restore_state_from_tb has been 224 * called. If the faulting instruction is in a delay slot, and the 225 * target architecture requires re-execution of the branch, then 226 * adjust the cpu state as required and return true. 227 */ 228 bool (*io_recompile_replay_branch)(CPUState *cpu, 229 const TranslationBlock *tb); 230 /** 231 * @need_replay_interrupt: Return %true if @interrupt_request 232 * needs to be recorded for replay purposes. 233 */ 234 bool (*need_replay_interrupt)(int interrupt_request); 235 #endif /* !CONFIG_USER_ONLY */ 236 }; 237 238 #if defined(CONFIG_USER_ONLY) 239 240 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 241 MemTxAttrs atr, int fl, uintptr_t ra) 242 { 243 } 244 245 static inline int cpu_watchpoint_address_matches(CPUState *cpu, 246 vaddr addr, vaddr len) 247 { 248 return 0; 249 } 250 251 #else 252 253 /** 254 * cpu_check_watchpoint: 255 * @cpu: cpu context 256 * @addr: guest virtual address 257 * @len: access length 258 * @attrs: memory access attributes 259 * @flags: watchpoint access type 260 * @ra: unwind return address 261 * 262 * Check for a watchpoint hit in [addr, addr+len) of the type 263 * specified by @flags. Exit via exception with a hit. 264 */ 265 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 266 MemTxAttrs attrs, int flags, uintptr_t ra); 267 268 /** 269 * cpu_watchpoint_address_matches: 270 * @cpu: cpu context 271 * @addr: guest virtual address 272 * @len: access length 273 * 274 * Return the watchpoint flags that apply to [addr, addr+len). 275 * If no watchpoint is registered for the range, the result is 0. 276 */ 277 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); 278 279 #endif 280 281 #endif /* TCG_CPU_OPS_H */ 282