1 /* 2 * TCG CPU-specific operations 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef TCG_CPU_OPS_H 11 #define TCG_CPU_OPS_H 12 13 #include "exec/breakpoint.h" 14 #include "exec/hwaddr.h" 15 #include "exec/memattrs.h" 16 #include "exec/memop.h" 17 #include "exec/mmu-access-type.h" 18 #include "exec/vaddr.h" 19 #include "tcg/tcg-mo.h" 20 21 struct TCGCPUOps { 22 23 /** 24 * @guest_default_memory_order: default barrier that is required 25 * for the guest memory ordering. 26 */ 27 TCGBar guest_default_memory_order; 28 29 /** 30 * @initialize: Initialize TCG state 31 * 32 * Called when the first CPU is realized. 33 */ 34 void (*initialize)(void); 35 /** 36 * @translate_code: Translate guest instructions to TCGOps 37 * @cpu: cpu context 38 * @tb: translation block 39 * @max_insns: max number of instructions to translate 40 * @pc: guest virtual program counter address 41 * @host_pc: host physical program counter address 42 * 43 * This function must be provided by the target, which should create 44 * the target-specific DisasContext, and then invoke translator_loop. 45 */ 46 void (*translate_code)(CPUState *cpu, TranslationBlock *tb, 47 int *max_insns, vaddr pc, void *host_pc); 48 /** 49 * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock 50 * 51 * This is called when we abandon execution of a TB before starting it, 52 * and must set all parts of the CPU state which the previous TB in the 53 * chain may not have updated. 54 * By default, when this is NULL, a call is made to @set_pc(tb->pc). 55 * 56 * If more state needs to be restored, the target must implement a 57 * function to restore all the state, and register it here. 58 */ 59 void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb); 60 /** 61 * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn 62 * 63 * This is called when we unwind state in the middle of a TB, 64 * usually before raising an exception. Set all part of the CPU 65 * state which are tracked insn-by-insn in the target-specific 66 * arguments to start_insn, passed as @data. 67 */ 68 void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb, 69 const uint64_t *data); 70 71 /** @cpu_exec_enter: Callback for cpu_exec preparation */ 72 void (*cpu_exec_enter)(CPUState *cpu); 73 /** @cpu_exec_exit: Callback for cpu_exec cleanup */ 74 void (*cpu_exec_exit)(CPUState *cpu); 75 /** @debug_excp_handler: Callback for handling debug exceptions */ 76 void (*debug_excp_handler)(CPUState *cpu); 77 78 /** @mmu_index: Callback for choosing softmmu mmu index */ 79 int (*mmu_index)(CPUState *cpu, bool ifetch); 80 81 #ifdef CONFIG_USER_ONLY 82 /** 83 * @fake_user_interrupt: Callback for 'fake exception' handling. 84 * 85 * Simulate 'fake exception' which will be handled outside the 86 * cpu execution loop (hack for x86 user mode). 87 */ 88 void (*fake_user_interrupt)(CPUState *cpu); 89 90 /** 91 * record_sigsegv: 92 * @cpu: cpu context 93 * @addr: faulting guest address 94 * @access_type: access was read/write/execute 95 * @maperr: true for invalid page, false for permission fault 96 * @ra: host pc for unwinding 97 * 98 * We are about to raise SIGSEGV with si_code set for @maperr, 99 * and si_addr set for @addr. Record anything further needed 100 * for the signal ucontext_t. 101 * 102 * If the emulated kernel does not provide anything to the signal 103 * handler with anything besides the user context registers, and 104 * the siginfo_t, then this hook need do nothing and may be omitted. 105 * Otherwise, record the data and return; the caller will raise 106 * the signal, unwind the cpu state, and return to the main loop. 107 * 108 * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided 109 * so that a "normal" cpu exception can be raised. In this case, 110 * the signal must be raised by the architecture cpu_loop. 111 */ 112 void (*record_sigsegv)(CPUState *cpu, vaddr addr, 113 MMUAccessType access_type, 114 bool maperr, uintptr_t ra); 115 /** 116 * record_sigbus: 117 * @cpu: cpu context 118 * @addr: misaligned guest address 119 * @access_type: access was read/write/execute 120 * @ra: host pc for unwinding 121 * 122 * We are about to raise SIGBUS with si_code BUS_ADRALN, 123 * and si_addr set for @addr. Record anything further needed 124 * for the signal ucontext_t. 125 * 126 * If the emulated kernel does not provide the signal handler with 127 * anything besides the user context registers, and the siginfo_t, 128 * then this hook need do nothing and may be omitted. 129 * Otherwise, record the data and return; the caller will raise 130 * the signal, unwind the cpu state, and return to the main loop. 131 * 132 * If it is simpler to re-use the sysemu do_unaligned_access code, 133 * @ra is provided so that a "normal" cpu exception can be raised. 134 * In this case, the signal must be raised by the architecture cpu_loop. 135 */ 136 void (*record_sigbus)(CPUState *cpu, vaddr addr, 137 MMUAccessType access_type, uintptr_t ra); 138 #else 139 /** @do_interrupt: Callback for interrupt handling. */ 140 void (*do_interrupt)(CPUState *cpu); 141 /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ 142 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 143 /** 144 * @cpu_exec_halt: Callback for handling halt in cpu_exec. 145 * 146 * The target CPU should do any special processing here that it needs 147 * to do when the CPU is in the halted state. 148 * 149 * Return true to indicate that the CPU should now leave halt, false 150 * if it should remain in the halted state. (This should generally 151 * be the same value that cpu_has_work() would return.) 152 * 153 * This method must be provided. If the target does not need to 154 * do anything special for halt, the same function used for its 155 * SysemuCPUOps::has_work method can be used here, as they have the 156 * same function signature. 157 */ 158 bool (*cpu_exec_halt)(CPUState *cpu); 159 /** 160 * @tlb_fill_align: Handle a softmmu tlb miss 161 * @cpu: cpu context 162 * @out: output page properties 163 * @addr: virtual address 164 * @access_type: read, write or execute 165 * @mmu_idx: mmu context 166 * @memop: memory operation for the access 167 * @size: memory access size, or 0 for whole page 168 * @probe: test only, no fault 169 * @ra: host return address for exception unwind 170 * 171 * If the access is valid, fill in @out and return true. 172 * Otherwise if probe is true, return false. 173 * Otherwise raise an exception and do not return. 174 * 175 * The alignment check for the access is deferred to this hook, 176 * so that the target can determine the priority of any alignment 177 * fault with respect to other potential faults from paging. 178 * Zero may be passed for @memop to skip any alignment check 179 * for non-memory-access operations such as probing. 180 */ 181 bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, 182 MMUAccessType access_type, int mmu_idx, 183 MemOp memop, int size, bool probe, uintptr_t ra); 184 /** 185 * @tlb_fill: Handle a softmmu tlb miss 186 * 187 * If the access is valid, call tlb_set_page and return true; 188 * if the access is invalid and probe is true, return false; 189 * otherwise raise an exception and do not return. 190 */ 191 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, 192 MMUAccessType access_type, int mmu_idx, 193 bool probe, uintptr_t retaddr); 194 /** 195 * @do_transaction_failed: Callback for handling failed memory transactions 196 * (ie bus faults or external aborts; not MMU faults) 197 */ 198 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 199 unsigned size, MMUAccessType access_type, 200 int mmu_idx, MemTxAttrs attrs, 201 MemTxResult response, uintptr_t retaddr); 202 /** 203 * @do_unaligned_access: Callback for unaligned access handling 204 * The callback must exit via raising an exception. 205 */ 206 G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 207 MMUAccessType access_type, 208 int mmu_idx, uintptr_t retaddr); 209 210 /** 211 * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM 212 */ 213 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 214 215 /** 216 * @debug_check_watchpoint: return true if the architectural 217 * watchpoint whose address has matched should really fire, used by ARM 218 * and RISC-V 219 */ 220 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 221 222 /** 223 * @debug_check_breakpoint: return true if the architectural 224 * breakpoint whose PC has matched should really fire. 225 */ 226 bool (*debug_check_breakpoint)(CPUState *cpu); 227 228 /** 229 * @io_recompile_replay_branch: Callback for cpu_io_recompile. 230 * 231 * The cpu has been stopped, and cpu_restore_state_from_tb has been 232 * called. If the faulting instruction is in a delay slot, and the 233 * target architecture requires re-execution of the branch, then 234 * adjust the cpu state as required and return true. 235 */ 236 bool (*io_recompile_replay_branch)(CPUState *cpu, 237 const TranslationBlock *tb); 238 /** 239 * @need_replay_interrupt: Return %true if @interrupt_request 240 * needs to be recorded for replay purposes. 241 */ 242 bool (*need_replay_interrupt)(int interrupt_request); 243 #endif /* !CONFIG_USER_ONLY */ 244 }; 245 246 #if defined(CONFIG_USER_ONLY) 247 248 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 249 MemTxAttrs atr, int fl, uintptr_t ra) 250 { 251 } 252 253 static inline int cpu_watchpoint_address_matches(CPUState *cpu, 254 vaddr addr, vaddr len) 255 { 256 return 0; 257 } 258 259 #else 260 261 /** 262 * cpu_check_watchpoint: 263 * @cpu: cpu context 264 * @addr: guest virtual address 265 * @len: access length 266 * @attrs: memory access attributes 267 * @flags: watchpoint access type 268 * @ra: unwind return address 269 * 270 * Check for a watchpoint hit in [addr, addr+len) of the type 271 * specified by @flags. Exit via exception with a hit. 272 */ 273 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 274 MemTxAttrs attrs, int flags, uintptr_t ra); 275 276 /** 277 * cpu_watchpoint_address_matches: 278 * @cpu: cpu context 279 * @addr: guest virtual address 280 * @len: access length 281 * 282 * Return the watchpoint flags that apply to [addr, addr+len). 283 * If no watchpoint is registered for the range, the result is 0. 284 */ 285 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); 286 287 #endif 288 289 #endif /* TCG_CPU_OPS_H */ 290