1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "cpu.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/boards.h" 33 #include "hw/loader.h" 34 #include "elf.h" 35 #include "exec/memory.h" 36 #include "exec/address-spaces.h" 37 #include "hw/char/serial.h" 38 #include "net/net.h" 39 #include "hw/sysbus.h" 40 #include "hw/block/flash.h" 41 #include "sysemu/block-backend.h" 42 #include "chardev/char.h" 43 #include "sysemu/device_tree.h" 44 #include "qemu/error-report.h" 45 #include "qemu/option.h" 46 #include "bootparam.h" 47 #include "xtensa_memory.h" 48 49 typedef struct XtfpgaFlashDesc { 50 hwaddr base; 51 size_t size; 52 size_t boot_base; 53 size_t sector_size; 54 } XtfpgaFlashDesc; 55 56 typedef struct XtfpgaBoardDesc { 57 const XtfpgaFlashDesc *flash; 58 size_t sram_size; 59 const hwaddr *io; 60 } XtfpgaBoardDesc; 61 62 typedef struct XtfpgaFpgaState { 63 MemoryRegion iomem; 64 uint32_t leds; 65 uint32_t switches; 66 } XtfpgaFpgaState; 67 68 static void xtfpga_fpga_reset(void *opaque) 69 { 70 XtfpgaFpgaState *s = opaque; 71 72 s->leds = 0; 73 s->switches = 0; 74 } 75 76 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, 77 unsigned size) 78 { 79 XtfpgaFpgaState *s = opaque; 80 81 switch (addr) { 82 case 0x0: /*build date code*/ 83 return 0x09272011; 84 85 case 0x4: /*processor clock frequency, Hz*/ 86 return 10000000; 87 88 case 0x8: /*LEDs (off = 0, on = 1)*/ 89 return s->leds; 90 91 case 0xc: /*DIP switches (off = 0, on = 1)*/ 92 return s->switches; 93 } 94 return 0; 95 } 96 97 static void xtfpga_fpga_write(void *opaque, hwaddr addr, 98 uint64_t val, unsigned size) 99 { 100 XtfpgaFpgaState *s = opaque; 101 102 switch (addr) { 103 case 0x8: /*LEDs (off = 0, on = 1)*/ 104 s->leds = val; 105 break; 106 107 case 0x10: /*board reset*/ 108 if (val == 0xdead) { 109 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 110 } 111 break; 112 } 113 } 114 115 static const MemoryRegionOps xtfpga_fpga_ops = { 116 .read = xtfpga_fpga_read, 117 .write = xtfpga_fpga_write, 118 .endianness = DEVICE_NATIVE_ENDIAN, 119 }; 120 121 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, 122 hwaddr base) 123 { 124 XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState)); 125 126 memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, 127 "xtfpga.fpga", 0x10000); 128 memory_region_add_subregion(address_space, base, &s->iomem); 129 xtfpga_fpga_reset(s); 130 qemu_register_reset(xtfpga_fpga_reset, s); 131 return s; 132 } 133 134 static void xtfpga_net_init(MemoryRegion *address_space, 135 hwaddr base, 136 hwaddr descriptors, 137 hwaddr buffers, 138 qemu_irq irq, NICInfo *nd) 139 { 140 DeviceState *dev; 141 SysBusDevice *s; 142 MemoryRegion *ram; 143 144 dev = qdev_create(NULL, "open_eth"); 145 qdev_set_nic_properties(dev, nd); 146 qdev_init_nofail(dev); 147 148 s = SYS_BUS_DEVICE(dev); 149 sysbus_connect_irq(s, 0, irq); 150 memory_region_add_subregion(address_space, base, 151 sysbus_mmio_get_region(s, 0)); 152 memory_region_add_subregion(address_space, descriptors, 153 sysbus_mmio_get_region(s, 1)); 154 155 ram = g_malloc(sizeof(*ram)); 156 memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16384, 157 &error_fatal); 158 vmstate_register_ram_global(ram); 159 memory_region_add_subregion(address_space, buffers, ram); 160 } 161 162 static pflash_t *xtfpga_flash_init(MemoryRegion *address_space, 163 const XtfpgaBoardDesc *board, 164 DriveInfo *dinfo, int be) 165 { 166 SysBusDevice *s; 167 DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 168 169 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 170 &error_abort); 171 qdev_prop_set_uint32(dev, "num-blocks", 172 board->flash->size / board->flash->sector_size); 173 qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); 174 qdev_prop_set_uint8(dev, "width", 2); 175 qdev_prop_set_bit(dev, "big-endian", be); 176 qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 177 qdev_init_nofail(dev); 178 s = SYS_BUS_DEVICE(dev); 179 memory_region_add_subregion(address_space, board->flash->base, 180 sysbus_mmio_get_region(s, 0)); 181 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); 182 } 183 184 static uint64_t translate_phys_addr(void *opaque, uint64_t addr) 185 { 186 XtensaCPU *cpu = opaque; 187 188 return cpu_get_phys_page_debug(CPU(cpu), addr); 189 } 190 191 static void xtfpga_reset(void *opaque) 192 { 193 XtensaCPU *cpu = opaque; 194 195 cpu_reset(CPU(cpu)); 196 } 197 198 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, 199 unsigned size) 200 { 201 return 0; 202 } 203 204 static void xtfpga_io_write(void *opaque, hwaddr addr, 205 uint64_t val, unsigned size) 206 { 207 } 208 209 static const MemoryRegionOps xtfpga_io_ops = { 210 .read = xtfpga_io_read, 211 .write = xtfpga_io_write, 212 .endianness = DEVICE_NATIVE_ENDIAN, 213 }; 214 215 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 216 { 217 #ifdef TARGET_WORDS_BIGENDIAN 218 int be = 1; 219 #else 220 int be = 0; 221 #endif 222 MemoryRegion *system_memory = get_system_memory(); 223 XtensaCPU *cpu = NULL; 224 CPUXtensaState *env = NULL; 225 MemoryRegion *system_io; 226 DriveInfo *dinfo; 227 pflash_t *flash = NULL; 228 QemuOpts *machine_opts = qemu_get_machine_opts(); 229 const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); 230 const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); 231 const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); 232 const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); 233 const unsigned system_io_size = 224 * 1024 * 1024; 234 int n; 235 236 for (n = 0; n < smp_cpus; n++) { 237 cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); 238 env = &cpu->env; 239 240 env->sregs[PRID] = n; 241 qemu_register_reset(xtfpga_reset, cpu); 242 /* Need MMU initialized prior to ELF loading, 243 * so that ELF gets loaded into virtual addresses 244 */ 245 cpu_reset(CPU(cpu)); 246 } 247 248 if (env) { 249 XtensaMemory sysram = env->config->sysram; 250 251 sysram.location[0].size = machine->ram_size; 252 xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", 253 system_memory); 254 xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", 255 system_memory); 256 xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", 257 system_memory); 258 xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", 259 system_memory); 260 xtensa_create_memory_regions(&sysram, "xtensa.sysram", 261 system_memory); 262 } 263 264 system_io = g_malloc(sizeof(*system_io)); 265 memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", 266 system_io_size); 267 memory_region_add_subregion(system_memory, board->io[0], system_io); 268 if (board->io[1]) { 269 MemoryRegion *io = g_malloc(sizeof(*io)); 270 271 memory_region_init_alias(io, NULL, "xtfpga.io.cached", 272 system_io, 0, system_io_size); 273 memory_region_add_subregion(system_memory, board->io[1], io); 274 } 275 xtfpga_fpga_init(system_io, 0x0d020000); 276 if (nd_table[0].used) { 277 xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, 278 xtensa_get_extint(env, 1), nd_table); 279 } 280 281 if (!serial_hds[0]) { 282 serial_hds[0] = qemu_chr_new("serial0", "null"); 283 } 284 285 serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), 286 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); 287 288 dinfo = drive_get(IF_PFLASH, 0, 0); 289 if (dinfo) { 290 flash = xtfpga_flash_init(system_io, board, dinfo, be); 291 } 292 293 /* Use presence of kernel file name as 'boot from SRAM' switch. */ 294 if (kernel_filename) { 295 uint32_t entry_point = env->pc; 296 size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ 297 uint32_t tagptr = env->config->sysrom.location[0].addr + 298 board->sram_size; 299 uint32_t cur_tagptr; 300 BpMemInfo memory_location = { 301 .type = tswap32(MEMORY_TYPE_CONVENTIONAL), 302 .start = tswap32(env->config->sysram.location[0].addr), 303 .end = tswap32(env->config->sysram.location[0].addr + 304 machine->ram_size), 305 }; 306 uint32_t lowmem_end = machine->ram_size < 0x08000000 ? 307 machine->ram_size : 0x08000000; 308 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); 309 310 lowmem_end += env->config->sysram.location[0].addr; 311 cur_lowmem += env->config->sysram.location[0].addr; 312 313 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 314 system_memory); 315 316 if (kernel_cmdline) { 317 bp_size += get_tag_size(strlen(kernel_cmdline) + 1); 318 } 319 if (dtb_filename) { 320 bp_size += get_tag_size(sizeof(uint32_t)); 321 } 322 if (initrd_filename) { 323 bp_size += get_tag_size(sizeof(BpMemInfo)); 324 } 325 326 /* Put kernel bootparameters to the end of that SRAM */ 327 tagptr = (tagptr - bp_size) & ~0xff; 328 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); 329 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, 330 sizeof(memory_location), &memory_location); 331 332 if (kernel_cmdline) { 333 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, 334 strlen(kernel_cmdline) + 1, kernel_cmdline); 335 } 336 #ifdef CONFIG_FDT 337 if (dtb_filename) { 338 int fdt_size; 339 void *fdt = load_device_tree(dtb_filename, &fdt_size); 340 uint32_t dtb_addr = tswap32(cur_lowmem); 341 342 if (!fdt) { 343 error_report("could not load DTB '%s'", dtb_filename); 344 exit(EXIT_FAILURE); 345 } 346 347 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); 348 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, 349 sizeof(dtb_addr), &dtb_addr); 350 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096); 351 } 352 #else 353 if (dtb_filename) { 354 error_report("could not load DTB '%s': " 355 "FDT support is not configured in QEMU", 356 dtb_filename); 357 exit(EXIT_FAILURE); 358 } 359 #endif 360 if (initrd_filename) { 361 BpMemInfo initrd_location = { 0 }; 362 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, 363 lowmem_end - cur_lowmem); 364 365 if (initrd_size < 0) { 366 initrd_size = load_image_targphys(initrd_filename, 367 cur_lowmem, 368 lowmem_end - cur_lowmem); 369 } 370 if (initrd_size < 0) { 371 error_report("could not load initrd '%s'", initrd_filename); 372 exit(EXIT_FAILURE); 373 } 374 initrd_location.start = tswap32(cur_lowmem); 375 initrd_location.end = tswap32(cur_lowmem + initrd_size); 376 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, 377 sizeof(initrd_location), &initrd_location); 378 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096); 379 } 380 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); 381 env->regs[2] = tagptr; 382 383 uint64_t elf_entry; 384 uint64_t elf_lowaddr; 385 int success = load_elf(kernel_filename, translate_phys_addr, cpu, 386 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0); 387 if (success > 0) { 388 entry_point = elf_entry; 389 } else { 390 hwaddr ep; 391 int is_linux; 392 success = load_uimage(kernel_filename, &ep, NULL, &is_linux, 393 translate_phys_addr, cpu); 394 if (success > 0 && is_linux) { 395 entry_point = ep; 396 } else { 397 error_report("could not load kernel '%s'", 398 kernel_filename); 399 exit(EXIT_FAILURE); 400 } 401 } 402 if (entry_point != env->pc) { 403 uint8_t boot[] = { 404 #ifdef TARGET_WORDS_BIGENDIAN 405 0x60, 0x00, 0x08, /* j 1f */ 406 0x00, /* .literal_position */ 407 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 408 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 409 /* 1: */ 410 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 411 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 412 0x0a, 0x00, 0x00, /* jx a0 */ 413 #else 414 0x06, 0x02, 0x00, /* j 1f */ 415 0x00, /* .literal_position */ 416 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 417 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 418 /* 1: */ 419 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 420 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 421 0xa0, 0x00, 0x00, /* jx a0 */ 422 #endif 423 }; 424 uint32_t entry_pc = tswap32(entry_point); 425 uint32_t entry_a2 = tswap32(tagptr); 426 427 memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); 428 memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); 429 cpu_physical_memory_write(env->pc, boot, sizeof(boot)); 430 } 431 } else { 432 if (flash) { 433 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); 434 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); 435 uint32_t size = env->config->sysrom.location[0].size; 436 437 if (board->flash->size - board->flash->boot_base < size) { 438 size = board->flash->size - board->flash->boot_base; 439 } 440 441 memory_region_init_alias(flash_io, NULL, "xtfpga.flash", 442 flash_mr, board->flash->boot_base, size); 443 memory_region_add_subregion(system_memory, 444 env->config->sysrom.location[0].addr, 445 flash_io); 446 } else { 447 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 448 system_memory); 449 } 450 } 451 } 452 453 static const hwaddr xtfpga_mmu_io[2] = { 454 0xf0000000, 455 }; 456 457 static const hwaddr xtfpga_nommu_io[2] = { 458 0x90000000, 459 0x70000000, 460 }; 461 462 static const XtfpgaFlashDesc lx60_flash = { 463 .base = 0x08000000, 464 .size = 0x00400000, 465 .sector_size = 0x10000, 466 }; 467 468 static void xtfpga_lx60_init(MachineState *machine) 469 { 470 static const XtfpgaBoardDesc lx60_board = { 471 .flash = &lx60_flash, 472 .sram_size = 0x20000, 473 .io = xtfpga_mmu_io, 474 }; 475 xtfpga_init(&lx60_board, machine); 476 } 477 478 static void xtfpga_lx60_nommu_init(MachineState *machine) 479 { 480 static const XtfpgaBoardDesc lx60_board = { 481 .flash = &lx60_flash, 482 .sram_size = 0x20000, 483 .io = xtfpga_nommu_io, 484 }; 485 xtfpga_init(&lx60_board, machine); 486 } 487 488 static const XtfpgaFlashDesc lx200_flash = { 489 .base = 0x08000000, 490 .size = 0x01000000, 491 .sector_size = 0x20000, 492 }; 493 494 static void xtfpga_lx200_init(MachineState *machine) 495 { 496 static const XtfpgaBoardDesc lx200_board = { 497 .flash = &lx200_flash, 498 .sram_size = 0x2000000, 499 .io = xtfpga_mmu_io, 500 }; 501 xtfpga_init(&lx200_board, machine); 502 } 503 504 static void xtfpga_lx200_nommu_init(MachineState *machine) 505 { 506 static const XtfpgaBoardDesc lx200_board = { 507 .flash = &lx200_flash, 508 .sram_size = 0x2000000, 509 .io = xtfpga_nommu_io, 510 }; 511 xtfpga_init(&lx200_board, machine); 512 } 513 514 static const XtfpgaFlashDesc ml605_flash = { 515 .base = 0x08000000, 516 .size = 0x01000000, 517 .sector_size = 0x20000, 518 }; 519 520 static void xtfpga_ml605_init(MachineState *machine) 521 { 522 static const XtfpgaBoardDesc ml605_board = { 523 .flash = &ml605_flash, 524 .sram_size = 0x2000000, 525 .io = xtfpga_mmu_io, 526 }; 527 xtfpga_init(&ml605_board, machine); 528 } 529 530 static void xtfpga_ml605_nommu_init(MachineState *machine) 531 { 532 static const XtfpgaBoardDesc ml605_board = { 533 .flash = &ml605_flash, 534 .sram_size = 0x2000000, 535 .io = xtfpga_nommu_io, 536 }; 537 xtfpga_init(&ml605_board, machine); 538 } 539 540 static const XtfpgaFlashDesc kc705_flash = { 541 .base = 0x00000000, 542 .size = 0x08000000, 543 .boot_base = 0x06000000, 544 .sector_size = 0x20000, 545 }; 546 547 static void xtfpga_kc705_init(MachineState *machine) 548 { 549 static const XtfpgaBoardDesc kc705_board = { 550 .flash = &kc705_flash, 551 .sram_size = 0x2000000, 552 .io = xtfpga_mmu_io, 553 }; 554 xtfpga_init(&kc705_board, machine); 555 } 556 557 static void xtfpga_kc705_nommu_init(MachineState *machine) 558 { 559 static const XtfpgaBoardDesc kc705_board = { 560 .flash = &kc705_flash, 561 .sram_size = 0x2000000, 562 .io = xtfpga_nommu_io, 563 }; 564 xtfpga_init(&kc705_board, machine); 565 } 566 567 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) 568 { 569 MachineClass *mc = MACHINE_CLASS(oc); 570 571 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 572 mc->init = xtfpga_lx60_init; 573 mc->max_cpus = 4; 574 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 575 } 576 577 static const TypeInfo xtfpga_lx60_type = { 578 .name = MACHINE_TYPE_NAME("lx60"), 579 .parent = TYPE_MACHINE, 580 .class_init = xtfpga_lx60_class_init, 581 }; 582 583 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) 584 { 585 MachineClass *mc = MACHINE_CLASS(oc); 586 587 mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 588 mc->init = xtfpga_lx60_nommu_init; 589 mc->max_cpus = 4; 590 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 591 } 592 593 static const TypeInfo xtfpga_lx60_nommu_type = { 594 .name = MACHINE_TYPE_NAME("lx60-nommu"), 595 .parent = TYPE_MACHINE, 596 .class_init = xtfpga_lx60_nommu_class_init, 597 }; 598 599 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) 600 { 601 MachineClass *mc = MACHINE_CLASS(oc); 602 603 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 604 mc->init = xtfpga_lx200_init; 605 mc->max_cpus = 4; 606 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 607 } 608 609 static const TypeInfo xtfpga_lx200_type = { 610 .name = MACHINE_TYPE_NAME("lx200"), 611 .parent = TYPE_MACHINE, 612 .class_init = xtfpga_lx200_class_init, 613 }; 614 615 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) 616 { 617 MachineClass *mc = MACHINE_CLASS(oc); 618 619 mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 620 mc->init = xtfpga_lx200_nommu_init; 621 mc->max_cpus = 4; 622 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 623 } 624 625 static const TypeInfo xtfpga_lx200_nommu_type = { 626 .name = MACHINE_TYPE_NAME("lx200-nommu"), 627 .parent = TYPE_MACHINE, 628 .class_init = xtfpga_lx200_nommu_class_init, 629 }; 630 631 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) 632 { 633 MachineClass *mc = MACHINE_CLASS(oc); 634 635 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 636 mc->init = xtfpga_ml605_init; 637 mc->max_cpus = 4; 638 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 639 } 640 641 static const TypeInfo xtfpga_ml605_type = { 642 .name = MACHINE_TYPE_NAME("ml605"), 643 .parent = TYPE_MACHINE, 644 .class_init = xtfpga_ml605_class_init, 645 }; 646 647 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) 648 { 649 MachineClass *mc = MACHINE_CLASS(oc); 650 651 mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 652 mc->init = xtfpga_ml605_nommu_init; 653 mc->max_cpus = 4; 654 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 655 } 656 657 static const TypeInfo xtfpga_ml605_nommu_type = { 658 .name = MACHINE_TYPE_NAME("ml605-nommu"), 659 .parent = TYPE_MACHINE, 660 .class_init = xtfpga_ml605_nommu_class_init, 661 }; 662 663 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) 664 { 665 MachineClass *mc = MACHINE_CLASS(oc); 666 667 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 668 mc->init = xtfpga_kc705_init; 669 mc->max_cpus = 4; 670 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 671 } 672 673 static const TypeInfo xtfpga_kc705_type = { 674 .name = MACHINE_TYPE_NAME("kc705"), 675 .parent = TYPE_MACHINE, 676 .class_init = xtfpga_kc705_class_init, 677 }; 678 679 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) 680 { 681 MachineClass *mc = MACHINE_CLASS(oc); 682 683 mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 684 mc->init = xtfpga_kc705_nommu_init; 685 mc->max_cpus = 4; 686 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 687 } 688 689 static const TypeInfo xtfpga_kc705_nommu_type = { 690 .name = MACHINE_TYPE_NAME("kc705-nommu"), 691 .parent = TYPE_MACHINE, 692 .class_init = xtfpga_kc705_nommu_class_init, 693 }; 694 695 static void xtfpga_machines_init(void) 696 { 697 type_register_static(&xtfpga_lx60_type); 698 type_register_static(&xtfpga_lx200_type); 699 type_register_static(&xtfpga_ml605_type); 700 type_register_static(&xtfpga_kc705_type); 701 type_register_static(&xtfpga_lx60_nommu_type); 702 type_register_static(&xtfpga_lx200_nommu_type); 703 type_register_static(&xtfpga_ml605_nommu_type); 704 type_register_static(&xtfpga_kc705_nommu_type); 705 } 706 707 type_init(xtfpga_machines_init) 708