1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "cpu.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/boards.h" 34 #include "hw/loader.h" 35 #include "hw/qdev-properties.h" 36 #include "elf.h" 37 #include "exec/memory.h" 38 #include "exec/address-spaces.h" 39 #include "hw/char/serial.h" 40 #include "net/net.h" 41 #include "hw/sysbus.h" 42 #include "hw/block/flash.h" 43 #include "chardev/char.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/reset.h" 46 #include "sysemu/runstate.h" 47 #include "qemu/error-report.h" 48 #include "qemu/option.h" 49 #include "bootparam.h" 50 #include "xtensa_memory.h" 51 #include "hw/xtensa/mx_pic.h" 52 #include "migration/vmstate.h" 53 54 typedef struct XtfpgaFlashDesc { 55 hwaddr base; 56 size_t size; 57 size_t boot_base; 58 size_t sector_size; 59 } XtfpgaFlashDesc; 60 61 typedef struct XtfpgaBoardDesc { 62 const XtfpgaFlashDesc *flash; 63 size_t sram_size; 64 const hwaddr *io; 65 } XtfpgaBoardDesc; 66 67 typedef struct XtfpgaFpgaState { 68 MemoryRegion iomem; 69 uint32_t freq; 70 uint32_t leds; 71 uint32_t switches; 72 } XtfpgaFpgaState; 73 74 static void xtfpga_fpga_reset(void *opaque) 75 { 76 XtfpgaFpgaState *s = opaque; 77 78 s->leds = 0; 79 s->switches = 0; 80 } 81 82 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, 83 unsigned size) 84 { 85 XtfpgaFpgaState *s = opaque; 86 87 switch (addr) { 88 case 0x0: /*build date code*/ 89 return 0x09272011; 90 91 case 0x4: /*processor clock frequency, Hz*/ 92 return s->freq; 93 94 case 0x8: /*LEDs (off = 0, on = 1)*/ 95 return s->leds; 96 97 case 0xc: /*DIP switches (off = 0, on = 1)*/ 98 return s->switches; 99 } 100 return 0; 101 } 102 103 static void xtfpga_fpga_write(void *opaque, hwaddr addr, 104 uint64_t val, unsigned size) 105 { 106 XtfpgaFpgaState *s = opaque; 107 108 switch (addr) { 109 case 0x8: /*LEDs (off = 0, on = 1)*/ 110 s->leds = val; 111 break; 112 113 case 0x10: /*board reset*/ 114 if (val == 0xdead) { 115 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 116 } 117 break; 118 } 119 } 120 121 static const MemoryRegionOps xtfpga_fpga_ops = { 122 .read = xtfpga_fpga_read, 123 .write = xtfpga_fpga_write, 124 .endianness = DEVICE_NATIVE_ENDIAN, 125 }; 126 127 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, 128 hwaddr base, uint32_t freq) 129 { 130 XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState)); 131 132 memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, 133 "xtfpga.fpga", 0x10000); 134 memory_region_add_subregion(address_space, base, &s->iomem); 135 s->freq = freq; 136 xtfpga_fpga_reset(s); 137 qemu_register_reset(xtfpga_fpga_reset, s); 138 return s; 139 } 140 141 static void xtfpga_net_init(MemoryRegion *address_space, 142 hwaddr base, 143 hwaddr descriptors, 144 hwaddr buffers, 145 qemu_irq irq, NICInfo *nd) 146 { 147 DeviceState *dev; 148 SysBusDevice *s; 149 MemoryRegion *ram; 150 151 dev = qdev_new("open_eth"); 152 qdev_set_nic_properties(dev, nd); 153 154 s = SYS_BUS_DEVICE(dev); 155 sysbus_realize_and_unref(s, &error_fatal); 156 sysbus_connect_irq(s, 0, irq); 157 memory_region_add_subregion(address_space, base, 158 sysbus_mmio_get_region(s, 0)); 159 memory_region_add_subregion(address_space, descriptors, 160 sysbus_mmio_get_region(s, 1)); 161 162 ram = g_malloc(sizeof(*ram)); 163 memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, 164 &error_fatal); 165 vmstate_register_ram_global(ram); 166 memory_region_add_subregion(address_space, buffers, ram); 167 } 168 169 static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, 170 const XtfpgaBoardDesc *board, 171 DriveInfo *dinfo, int be) 172 { 173 SysBusDevice *s; 174 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 175 176 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 177 qdev_prop_set_uint32(dev, "num-blocks", 178 board->flash->size / board->flash->sector_size); 179 qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); 180 qdev_prop_set_uint8(dev, "width", 2); 181 qdev_prop_set_bit(dev, "big-endian", be); 182 qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 183 s = SYS_BUS_DEVICE(dev); 184 sysbus_realize_and_unref(s, &error_fatal); 185 memory_region_add_subregion(address_space, board->flash->base, 186 sysbus_mmio_get_region(s, 0)); 187 return PFLASH_CFI01(dev); 188 } 189 190 static uint64_t translate_phys_addr(void *opaque, uint64_t addr) 191 { 192 XtensaCPU *cpu = opaque; 193 194 return cpu_get_phys_page_debug(CPU(cpu), addr); 195 } 196 197 static void xtfpga_reset(void *opaque) 198 { 199 XtensaCPU *cpu = opaque; 200 201 cpu_reset(CPU(cpu)); 202 } 203 204 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, 205 unsigned size) 206 { 207 return 0; 208 } 209 210 static void xtfpga_io_write(void *opaque, hwaddr addr, 211 uint64_t val, unsigned size) 212 { 213 } 214 215 static const MemoryRegionOps xtfpga_io_ops = { 216 .read = xtfpga_io_read, 217 .write = xtfpga_io_write, 218 .endianness = DEVICE_NATIVE_ENDIAN, 219 }; 220 221 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 222 { 223 #ifdef TARGET_WORDS_BIGENDIAN 224 int be = 1; 225 #else 226 int be = 0; 227 #endif 228 MemoryRegion *system_memory = get_system_memory(); 229 XtensaCPU *cpu = NULL; 230 CPUXtensaState *env = NULL; 231 MemoryRegion *system_io; 232 XtensaMxPic *mx_pic = NULL; 233 qemu_irq *extints; 234 DriveInfo *dinfo; 235 PFlashCFI01 *flash = NULL; 236 const char *kernel_filename = machine->kernel_filename; 237 const char *kernel_cmdline = machine->kernel_cmdline; 238 const char *dtb_filename = machine->dtb; 239 const char *initrd_filename = machine->initrd_filename; 240 const unsigned system_io_size = 224 * MiB; 241 uint32_t freq = 10000000; 242 int n; 243 unsigned int smp_cpus = machine->smp.cpus; 244 245 if (smp_cpus > 1) { 246 mx_pic = xtensa_mx_pic_init(31); 247 qemu_register_reset(xtensa_mx_pic_reset, mx_pic); 248 } 249 for (n = 0; n < smp_cpus; n++) { 250 CPUXtensaState *cenv = NULL; 251 252 cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); 253 cenv = &cpu->env; 254 if (!env) { 255 env = cenv; 256 freq = env->config->clock_freq_khz * 1000; 257 } 258 259 if (mx_pic) { 260 MemoryRegion *mx_eri; 261 262 mx_eri = xtensa_mx_pic_register_cpu(mx_pic, 263 xtensa_get_extints(cenv), 264 xtensa_get_runstall(cenv)); 265 memory_region_add_subregion(xtensa_get_er_region(cenv), 266 0, mx_eri); 267 } 268 cenv->sregs[PRID] = n; 269 xtensa_select_static_vectors(cenv, n != 0); 270 qemu_register_reset(xtfpga_reset, cpu); 271 /* Need MMU initialized prior to ELF loading, 272 * so that ELF gets loaded into virtual addresses 273 */ 274 cpu_reset(CPU(cpu)); 275 } 276 if (smp_cpus > 1) { 277 extints = xtensa_mx_pic_get_extints(mx_pic); 278 } else { 279 extints = xtensa_get_extints(env); 280 } 281 282 if (env) { 283 XtensaMemory sysram = env->config->sysram; 284 285 sysram.location[0].size = machine->ram_size; 286 xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", 287 system_memory); 288 xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", 289 system_memory); 290 xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", 291 system_memory); 292 xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", 293 system_memory); 294 xtensa_create_memory_regions(&sysram, "xtensa.sysram", 295 system_memory); 296 } 297 298 system_io = g_malloc(sizeof(*system_io)); 299 memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", 300 system_io_size); 301 memory_region_add_subregion(system_memory, board->io[0], system_io); 302 if (board->io[1]) { 303 MemoryRegion *io = g_malloc(sizeof(*io)); 304 305 memory_region_init_alias(io, NULL, "xtfpga.io.cached", 306 system_io, 0, system_io_size); 307 memory_region_add_subregion(system_memory, board->io[1], io); 308 } 309 xtfpga_fpga_init(system_io, 0x0d020000, freq); 310 if (nd_table[0].used) { 311 xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, 312 extints[1], nd_table); 313 } 314 315 serial_mm_init(system_io, 0x0d050020, 2, extints[0], 316 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 317 318 dinfo = drive_get(IF_PFLASH, 0, 0); 319 if (dinfo) { 320 flash = xtfpga_flash_init(system_io, board, dinfo, be); 321 } 322 323 /* Use presence of kernel file name as 'boot from SRAM' switch. */ 324 if (kernel_filename) { 325 uint32_t entry_point = env->pc; 326 size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ 327 uint32_t tagptr = env->config->sysrom.location[0].addr + 328 board->sram_size; 329 uint32_t cur_tagptr; 330 BpMemInfo memory_location = { 331 .type = tswap32(MEMORY_TYPE_CONVENTIONAL), 332 .start = tswap32(env->config->sysram.location[0].addr), 333 .end = tswap32(env->config->sysram.location[0].addr + 334 machine->ram_size), 335 }; 336 uint32_t lowmem_end = machine->ram_size < 0x08000000 ? 337 machine->ram_size : 0x08000000; 338 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); 339 340 lowmem_end += env->config->sysram.location[0].addr; 341 cur_lowmem += env->config->sysram.location[0].addr; 342 343 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 344 system_memory); 345 346 if (kernel_cmdline) { 347 bp_size += get_tag_size(strlen(kernel_cmdline) + 1); 348 } 349 if (dtb_filename) { 350 bp_size += get_tag_size(sizeof(uint32_t)); 351 } 352 if (initrd_filename) { 353 bp_size += get_tag_size(sizeof(BpMemInfo)); 354 } 355 356 /* Put kernel bootparameters to the end of that SRAM */ 357 tagptr = (tagptr - bp_size) & ~0xff; 358 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); 359 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, 360 sizeof(memory_location), &memory_location); 361 362 if (kernel_cmdline) { 363 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, 364 strlen(kernel_cmdline) + 1, kernel_cmdline); 365 } 366 #ifdef CONFIG_FDT 367 if (dtb_filename) { 368 int fdt_size; 369 void *fdt = load_device_tree(dtb_filename, &fdt_size); 370 uint32_t dtb_addr = tswap32(cur_lowmem); 371 372 if (!fdt) { 373 error_report("could not load DTB '%s'", dtb_filename); 374 exit(EXIT_FAILURE); 375 } 376 377 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); 378 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, 379 sizeof(dtb_addr), &dtb_addr); 380 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); 381 g_free(fdt); 382 } 383 #else 384 if (dtb_filename) { 385 error_report("could not load DTB '%s': " 386 "FDT support is not configured in QEMU", 387 dtb_filename); 388 exit(EXIT_FAILURE); 389 } 390 #endif 391 if (initrd_filename) { 392 BpMemInfo initrd_location = { 0 }; 393 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, 394 lowmem_end - cur_lowmem); 395 396 if (initrd_size < 0) { 397 initrd_size = load_image_targphys(initrd_filename, 398 cur_lowmem, 399 lowmem_end - cur_lowmem); 400 } 401 if (initrd_size < 0) { 402 error_report("could not load initrd '%s'", initrd_filename); 403 exit(EXIT_FAILURE); 404 } 405 initrd_location.start = tswap32(cur_lowmem); 406 initrd_location.end = tswap32(cur_lowmem + initrd_size); 407 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, 408 sizeof(initrd_location), &initrd_location); 409 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); 410 } 411 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); 412 env->regs[2] = tagptr; 413 414 uint64_t elf_entry; 415 int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, 416 &elf_entry, NULL, NULL, NULL, be, EM_XTENSA, 0, 0); 417 if (success > 0) { 418 entry_point = elf_entry; 419 } else { 420 hwaddr ep; 421 int is_linux; 422 success = load_uimage(kernel_filename, &ep, NULL, &is_linux, 423 translate_phys_addr, cpu); 424 if (success > 0 && is_linux) { 425 entry_point = ep; 426 } else { 427 error_report("could not load kernel '%s'", 428 kernel_filename); 429 exit(EXIT_FAILURE); 430 } 431 } 432 if (entry_point != env->pc) { 433 uint8_t boot[] = { 434 #ifdef TARGET_WORDS_BIGENDIAN 435 0x60, 0x00, 0x08, /* j 1f */ 436 0x00, /* .literal_position */ 437 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 438 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 439 /* 1: */ 440 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 441 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 442 0x0a, 0x00, 0x00, /* jx a0 */ 443 #else 444 0x06, 0x02, 0x00, /* j 1f */ 445 0x00, /* .literal_position */ 446 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 447 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 448 /* 1: */ 449 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 450 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 451 0xa0, 0x00, 0x00, /* jx a0 */ 452 #endif 453 }; 454 uint32_t entry_pc = tswap32(entry_point); 455 uint32_t entry_a2 = tswap32(tagptr); 456 457 memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); 458 memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); 459 cpu_physical_memory_write(env->pc, boot, sizeof(boot)); 460 } 461 } else { 462 if (flash) { 463 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); 464 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); 465 uint32_t size = env->config->sysrom.location[0].size; 466 467 if (board->flash->size - board->flash->boot_base < size) { 468 size = board->flash->size - board->flash->boot_base; 469 } 470 471 memory_region_init_alias(flash_io, NULL, "xtfpga.flash", 472 flash_mr, board->flash->boot_base, size); 473 memory_region_add_subregion(system_memory, 474 env->config->sysrom.location[0].addr, 475 flash_io); 476 } else { 477 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 478 system_memory); 479 } 480 } 481 } 482 483 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) 484 485 static const hwaddr xtfpga_mmu_io[2] = { 486 0xf0000000, 487 }; 488 489 static const hwaddr xtfpga_nommu_io[2] = { 490 0x90000000, 491 0x70000000, 492 }; 493 494 static const XtfpgaFlashDesc lx60_flash = { 495 .base = 0x08000000, 496 .size = 0x00400000, 497 .sector_size = 0x10000, 498 }; 499 500 static void xtfpga_lx60_init(MachineState *machine) 501 { 502 static const XtfpgaBoardDesc lx60_board = { 503 .flash = &lx60_flash, 504 .sram_size = 0x20000, 505 .io = xtfpga_mmu_io, 506 }; 507 xtfpga_init(&lx60_board, machine); 508 } 509 510 static void xtfpga_lx60_nommu_init(MachineState *machine) 511 { 512 static const XtfpgaBoardDesc lx60_board = { 513 .flash = &lx60_flash, 514 .sram_size = 0x20000, 515 .io = xtfpga_nommu_io, 516 }; 517 xtfpga_init(&lx60_board, machine); 518 } 519 520 static const XtfpgaFlashDesc lx200_flash = { 521 .base = 0x08000000, 522 .size = 0x01000000, 523 .sector_size = 0x20000, 524 }; 525 526 static void xtfpga_lx200_init(MachineState *machine) 527 { 528 static const XtfpgaBoardDesc lx200_board = { 529 .flash = &lx200_flash, 530 .sram_size = 0x2000000, 531 .io = xtfpga_mmu_io, 532 }; 533 xtfpga_init(&lx200_board, machine); 534 } 535 536 static void xtfpga_lx200_nommu_init(MachineState *machine) 537 { 538 static const XtfpgaBoardDesc lx200_board = { 539 .flash = &lx200_flash, 540 .sram_size = 0x2000000, 541 .io = xtfpga_nommu_io, 542 }; 543 xtfpga_init(&lx200_board, machine); 544 } 545 546 static const XtfpgaFlashDesc ml605_flash = { 547 .base = 0x08000000, 548 .size = 0x01000000, 549 .sector_size = 0x20000, 550 }; 551 552 static void xtfpga_ml605_init(MachineState *machine) 553 { 554 static const XtfpgaBoardDesc ml605_board = { 555 .flash = &ml605_flash, 556 .sram_size = 0x2000000, 557 .io = xtfpga_mmu_io, 558 }; 559 xtfpga_init(&ml605_board, machine); 560 } 561 562 static void xtfpga_ml605_nommu_init(MachineState *machine) 563 { 564 static const XtfpgaBoardDesc ml605_board = { 565 .flash = &ml605_flash, 566 .sram_size = 0x2000000, 567 .io = xtfpga_nommu_io, 568 }; 569 xtfpga_init(&ml605_board, machine); 570 } 571 572 static const XtfpgaFlashDesc kc705_flash = { 573 .base = 0x00000000, 574 .size = 0x08000000, 575 .boot_base = 0x06000000, 576 .sector_size = 0x20000, 577 }; 578 579 static void xtfpga_kc705_init(MachineState *machine) 580 { 581 static const XtfpgaBoardDesc kc705_board = { 582 .flash = &kc705_flash, 583 .sram_size = 0x2000000, 584 .io = xtfpga_mmu_io, 585 }; 586 xtfpga_init(&kc705_board, machine); 587 } 588 589 static void xtfpga_kc705_nommu_init(MachineState *machine) 590 { 591 static const XtfpgaBoardDesc kc705_board = { 592 .flash = &kc705_flash, 593 .sram_size = 0x2000000, 594 .io = xtfpga_nommu_io, 595 }; 596 xtfpga_init(&kc705_board, machine); 597 } 598 599 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) 600 { 601 MachineClass *mc = MACHINE_CLASS(oc); 602 603 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 604 mc->init = xtfpga_lx60_init; 605 mc->max_cpus = 32; 606 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 607 mc->default_ram_size = 64 * MiB; 608 } 609 610 static const TypeInfo xtfpga_lx60_type = { 611 .name = MACHINE_TYPE_NAME("lx60"), 612 .parent = TYPE_MACHINE, 613 .class_init = xtfpga_lx60_class_init, 614 }; 615 616 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) 617 { 618 MachineClass *mc = MACHINE_CLASS(oc); 619 620 mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 621 mc->init = xtfpga_lx60_nommu_init; 622 mc->max_cpus = 32; 623 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 624 mc->default_ram_size = 64 * MiB; 625 } 626 627 static const TypeInfo xtfpga_lx60_nommu_type = { 628 .name = MACHINE_TYPE_NAME("lx60-nommu"), 629 .parent = TYPE_MACHINE, 630 .class_init = xtfpga_lx60_nommu_class_init, 631 }; 632 633 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) 634 { 635 MachineClass *mc = MACHINE_CLASS(oc); 636 637 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 638 mc->init = xtfpga_lx200_init; 639 mc->max_cpus = 32; 640 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 641 mc->default_ram_size = 96 * MiB; 642 } 643 644 static const TypeInfo xtfpga_lx200_type = { 645 .name = MACHINE_TYPE_NAME("lx200"), 646 .parent = TYPE_MACHINE, 647 .class_init = xtfpga_lx200_class_init, 648 }; 649 650 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) 651 { 652 MachineClass *mc = MACHINE_CLASS(oc); 653 654 mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 655 mc->init = xtfpga_lx200_nommu_init; 656 mc->max_cpus = 32; 657 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 658 mc->default_ram_size = 96 * MiB; 659 } 660 661 static const TypeInfo xtfpga_lx200_nommu_type = { 662 .name = MACHINE_TYPE_NAME("lx200-nommu"), 663 .parent = TYPE_MACHINE, 664 .class_init = xtfpga_lx200_nommu_class_init, 665 }; 666 667 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) 668 { 669 MachineClass *mc = MACHINE_CLASS(oc); 670 671 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 672 mc->init = xtfpga_ml605_init; 673 mc->max_cpus = 32; 674 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 675 mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 676 } 677 678 static const TypeInfo xtfpga_ml605_type = { 679 .name = MACHINE_TYPE_NAME("ml605"), 680 .parent = TYPE_MACHINE, 681 .class_init = xtfpga_ml605_class_init, 682 }; 683 684 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) 685 { 686 MachineClass *mc = MACHINE_CLASS(oc); 687 688 mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 689 mc->init = xtfpga_ml605_nommu_init; 690 mc->max_cpus = 32; 691 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 692 mc->default_ram_size = 256 * MiB; 693 } 694 695 static const TypeInfo xtfpga_ml605_nommu_type = { 696 .name = MACHINE_TYPE_NAME("ml605-nommu"), 697 .parent = TYPE_MACHINE, 698 .class_init = xtfpga_ml605_nommu_class_init, 699 }; 700 701 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) 702 { 703 MachineClass *mc = MACHINE_CLASS(oc); 704 705 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 706 mc->init = xtfpga_kc705_init; 707 mc->max_cpus = 32; 708 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 709 mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 710 } 711 712 static const TypeInfo xtfpga_kc705_type = { 713 .name = MACHINE_TYPE_NAME("kc705"), 714 .parent = TYPE_MACHINE, 715 .class_init = xtfpga_kc705_class_init, 716 }; 717 718 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) 719 { 720 MachineClass *mc = MACHINE_CLASS(oc); 721 722 mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 723 mc->init = xtfpga_kc705_nommu_init; 724 mc->max_cpus = 32; 725 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 726 mc->default_ram_size = 256 * MiB; 727 } 728 729 static const TypeInfo xtfpga_kc705_nommu_type = { 730 .name = MACHINE_TYPE_NAME("kc705-nommu"), 731 .parent = TYPE_MACHINE, 732 .class_init = xtfpga_kc705_nommu_class_init, 733 }; 734 735 static void xtfpga_machines_init(void) 736 { 737 type_register_static(&xtfpga_lx60_type); 738 type_register_static(&xtfpga_lx200_type); 739 type_register_static(&xtfpga_ml605_type); 740 type_register_static(&xtfpga_kc705_type); 741 type_register_static(&xtfpga_lx60_nommu_type); 742 type_register_static(&xtfpga_lx200_nommu_type); 743 type_register_static(&xtfpga_ml605_nommu_type); 744 type_register_static(&xtfpga_kc705_nommu_type); 745 } 746 747 type_init(xtfpga_machines_init) 748