1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "cpu.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/boards.h" 34 #include "hw/loader.h" 35 #include "hw/qdev-properties.h" 36 #include "elf.h" 37 #include "exec/memory.h" 38 #include "exec/address-spaces.h" 39 #include "hw/char/serial.h" 40 #include "net/net.h" 41 #include "hw/sysbus.h" 42 #include "hw/block/flash.h" 43 #include "chardev/char.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/reset.h" 46 #include "sysemu/runstate.h" 47 #include "qemu/error-report.h" 48 #include "qemu/option.h" 49 #include "bootparam.h" 50 #include "xtensa_memory.h" 51 #include "hw/xtensa/mx_pic.h" 52 #include "migration/vmstate.h" 53 54 typedef struct XtfpgaFlashDesc { 55 hwaddr base; 56 size_t size; 57 size_t boot_base; 58 size_t sector_size; 59 } XtfpgaFlashDesc; 60 61 typedef struct XtfpgaBoardDesc { 62 const XtfpgaFlashDesc *flash; 63 size_t sram_size; 64 const hwaddr *io; 65 } XtfpgaBoardDesc; 66 67 typedef struct XtfpgaFpgaState { 68 MemoryRegion iomem; 69 uint32_t freq; 70 uint32_t leds; 71 uint32_t switches; 72 } XtfpgaFpgaState; 73 74 static void xtfpga_fpga_reset(void *opaque) 75 { 76 XtfpgaFpgaState *s = opaque; 77 78 s->leds = 0; 79 s->switches = 0; 80 } 81 82 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, 83 unsigned size) 84 { 85 XtfpgaFpgaState *s = opaque; 86 87 switch (addr) { 88 case 0x0: /*build date code*/ 89 return 0x09272011; 90 91 case 0x4: /*processor clock frequency, Hz*/ 92 return s->freq; 93 94 case 0x8: /*LEDs (off = 0, on = 1)*/ 95 return s->leds; 96 97 case 0xc: /*DIP switches (off = 0, on = 1)*/ 98 return s->switches; 99 } 100 return 0; 101 } 102 103 static void xtfpga_fpga_write(void *opaque, hwaddr addr, 104 uint64_t val, unsigned size) 105 { 106 XtfpgaFpgaState *s = opaque; 107 108 switch (addr) { 109 case 0x8: /*LEDs (off = 0, on = 1)*/ 110 s->leds = val; 111 break; 112 113 case 0x10: /*board reset*/ 114 if (val == 0xdead) { 115 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 116 } 117 break; 118 } 119 } 120 121 static const MemoryRegionOps xtfpga_fpga_ops = { 122 .read = xtfpga_fpga_read, 123 .write = xtfpga_fpga_write, 124 .endianness = DEVICE_NATIVE_ENDIAN, 125 }; 126 127 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, 128 hwaddr base, uint32_t freq) 129 { 130 XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState)); 131 132 memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, 133 "xtfpga.fpga", 0x10000); 134 memory_region_add_subregion(address_space, base, &s->iomem); 135 s->freq = freq; 136 xtfpga_fpga_reset(s); 137 qemu_register_reset(xtfpga_fpga_reset, s); 138 return s; 139 } 140 141 static void xtfpga_net_init(MemoryRegion *address_space, 142 hwaddr base, 143 hwaddr descriptors, 144 hwaddr buffers, 145 qemu_irq irq, NICInfo *nd) 146 { 147 DeviceState *dev; 148 SysBusDevice *s; 149 MemoryRegion *ram; 150 151 dev = qdev_new("open_eth"); 152 qdev_set_nic_properties(dev, nd); 153 154 s = SYS_BUS_DEVICE(dev); 155 sysbus_realize_and_unref(s, &error_fatal); 156 sysbus_connect_irq(s, 0, irq); 157 memory_region_add_subregion(address_space, base, 158 sysbus_mmio_get_region(s, 0)); 159 memory_region_add_subregion(address_space, descriptors, 160 sysbus_mmio_get_region(s, 1)); 161 162 ram = g_malloc(sizeof(*ram)); 163 memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, 164 &error_fatal); 165 vmstate_register_ram_global(ram); 166 memory_region_add_subregion(address_space, buffers, ram); 167 } 168 169 static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, 170 const XtfpgaBoardDesc *board, 171 DriveInfo *dinfo, int be) 172 { 173 SysBusDevice *s; 174 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 175 176 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 177 qdev_prop_set_uint32(dev, "num-blocks", 178 board->flash->size / board->flash->sector_size); 179 qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); 180 qdev_prop_set_uint8(dev, "width", 2); 181 qdev_prop_set_bit(dev, "big-endian", be); 182 qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 183 s = SYS_BUS_DEVICE(dev); 184 sysbus_realize_and_unref(s, &error_fatal); 185 memory_region_add_subregion(address_space, board->flash->base, 186 sysbus_mmio_get_region(s, 0)); 187 return PFLASH_CFI01(dev); 188 } 189 190 static uint64_t translate_phys_addr(void *opaque, uint64_t addr) 191 { 192 XtensaCPU *cpu = opaque; 193 194 return cpu_get_phys_page_debug(CPU(cpu), addr); 195 } 196 197 static void xtfpga_reset(void *opaque) 198 { 199 XtensaCPU *cpu = opaque; 200 201 cpu_reset(CPU(cpu)); 202 } 203 204 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, 205 unsigned size) 206 { 207 return 0; 208 } 209 210 static void xtfpga_io_write(void *opaque, hwaddr addr, 211 uint64_t val, unsigned size) 212 { 213 } 214 215 static const MemoryRegionOps xtfpga_io_ops = { 216 .read = xtfpga_io_read, 217 .write = xtfpga_io_write, 218 .endianness = DEVICE_NATIVE_ENDIAN, 219 }; 220 221 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 222 { 223 #ifdef TARGET_WORDS_BIGENDIAN 224 int be = 1; 225 #else 226 int be = 0; 227 #endif 228 MemoryRegion *system_memory = get_system_memory(); 229 XtensaCPU *cpu = NULL; 230 CPUXtensaState *env = NULL; 231 MemoryRegion *system_io; 232 XtensaMxPic *mx_pic = NULL; 233 qemu_irq *extints; 234 DriveInfo *dinfo; 235 PFlashCFI01 *flash = NULL; 236 QemuOpts *machine_opts = qemu_get_machine_opts(); 237 const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); 238 const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); 239 const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); 240 const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); 241 const unsigned system_io_size = 224 * MiB; 242 uint32_t freq = 10000000; 243 int n; 244 unsigned int smp_cpus = machine->smp.cpus; 245 246 if (smp_cpus > 1) { 247 mx_pic = xtensa_mx_pic_init(31); 248 qemu_register_reset(xtensa_mx_pic_reset, mx_pic); 249 } 250 for (n = 0; n < smp_cpus; n++) { 251 CPUXtensaState *cenv = NULL; 252 253 cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); 254 cenv = &cpu->env; 255 if (!env) { 256 env = cenv; 257 freq = env->config->clock_freq_khz * 1000; 258 } 259 260 if (mx_pic) { 261 MemoryRegion *mx_eri; 262 263 mx_eri = xtensa_mx_pic_register_cpu(mx_pic, 264 xtensa_get_extints(cenv), 265 xtensa_get_runstall(cenv)); 266 memory_region_add_subregion(xtensa_get_er_region(cenv), 267 0, mx_eri); 268 } 269 cenv->sregs[PRID] = n; 270 xtensa_select_static_vectors(cenv, n != 0); 271 qemu_register_reset(xtfpga_reset, cpu); 272 /* Need MMU initialized prior to ELF loading, 273 * so that ELF gets loaded into virtual addresses 274 */ 275 cpu_reset(CPU(cpu)); 276 } 277 if (smp_cpus > 1) { 278 extints = xtensa_mx_pic_get_extints(mx_pic); 279 } else { 280 extints = xtensa_get_extints(env); 281 } 282 283 if (env) { 284 XtensaMemory sysram = env->config->sysram; 285 286 sysram.location[0].size = machine->ram_size; 287 xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", 288 system_memory); 289 xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", 290 system_memory); 291 xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", 292 system_memory); 293 xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", 294 system_memory); 295 xtensa_create_memory_regions(&sysram, "xtensa.sysram", 296 system_memory); 297 } 298 299 system_io = g_malloc(sizeof(*system_io)); 300 memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", 301 system_io_size); 302 memory_region_add_subregion(system_memory, board->io[0], system_io); 303 if (board->io[1]) { 304 MemoryRegion *io = g_malloc(sizeof(*io)); 305 306 memory_region_init_alias(io, NULL, "xtfpga.io.cached", 307 system_io, 0, system_io_size); 308 memory_region_add_subregion(system_memory, board->io[1], io); 309 } 310 xtfpga_fpga_init(system_io, 0x0d020000, freq); 311 if (nd_table[0].used) { 312 xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, 313 extints[1], nd_table); 314 } 315 316 serial_mm_init(system_io, 0x0d050020, 2, extints[0], 317 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 318 319 dinfo = drive_get(IF_PFLASH, 0, 0); 320 if (dinfo) { 321 flash = xtfpga_flash_init(system_io, board, dinfo, be); 322 } 323 324 /* Use presence of kernel file name as 'boot from SRAM' switch. */ 325 if (kernel_filename) { 326 uint32_t entry_point = env->pc; 327 size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ 328 uint32_t tagptr = env->config->sysrom.location[0].addr + 329 board->sram_size; 330 uint32_t cur_tagptr; 331 BpMemInfo memory_location = { 332 .type = tswap32(MEMORY_TYPE_CONVENTIONAL), 333 .start = tswap32(env->config->sysram.location[0].addr), 334 .end = tswap32(env->config->sysram.location[0].addr + 335 machine->ram_size), 336 }; 337 uint32_t lowmem_end = machine->ram_size < 0x08000000 ? 338 machine->ram_size : 0x08000000; 339 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); 340 341 lowmem_end += env->config->sysram.location[0].addr; 342 cur_lowmem += env->config->sysram.location[0].addr; 343 344 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 345 system_memory); 346 347 if (kernel_cmdline) { 348 bp_size += get_tag_size(strlen(kernel_cmdline) + 1); 349 } 350 if (dtb_filename) { 351 bp_size += get_tag_size(sizeof(uint32_t)); 352 } 353 if (initrd_filename) { 354 bp_size += get_tag_size(sizeof(BpMemInfo)); 355 } 356 357 /* Put kernel bootparameters to the end of that SRAM */ 358 tagptr = (tagptr - bp_size) & ~0xff; 359 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); 360 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, 361 sizeof(memory_location), &memory_location); 362 363 if (kernel_cmdline) { 364 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, 365 strlen(kernel_cmdline) + 1, kernel_cmdline); 366 } 367 #ifdef CONFIG_FDT 368 if (dtb_filename) { 369 int fdt_size; 370 void *fdt = load_device_tree(dtb_filename, &fdt_size); 371 uint32_t dtb_addr = tswap32(cur_lowmem); 372 373 if (!fdt) { 374 error_report("could not load DTB '%s'", dtb_filename); 375 exit(EXIT_FAILURE); 376 } 377 378 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); 379 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, 380 sizeof(dtb_addr), &dtb_addr); 381 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); 382 g_free(fdt); 383 } 384 #else 385 if (dtb_filename) { 386 error_report("could not load DTB '%s': " 387 "FDT support is not configured in QEMU", 388 dtb_filename); 389 exit(EXIT_FAILURE); 390 } 391 #endif 392 if (initrd_filename) { 393 BpMemInfo initrd_location = { 0 }; 394 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, 395 lowmem_end - cur_lowmem); 396 397 if (initrd_size < 0) { 398 initrd_size = load_image_targphys(initrd_filename, 399 cur_lowmem, 400 lowmem_end - cur_lowmem); 401 } 402 if (initrd_size < 0) { 403 error_report("could not load initrd '%s'", initrd_filename); 404 exit(EXIT_FAILURE); 405 } 406 initrd_location.start = tswap32(cur_lowmem); 407 initrd_location.end = tswap32(cur_lowmem + initrd_size); 408 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, 409 sizeof(initrd_location), &initrd_location); 410 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); 411 } 412 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); 413 env->regs[2] = tagptr; 414 415 uint64_t elf_entry; 416 int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, 417 &elf_entry, NULL, NULL, NULL, be, EM_XTENSA, 0, 0); 418 if (success > 0) { 419 entry_point = elf_entry; 420 } else { 421 hwaddr ep; 422 int is_linux; 423 success = load_uimage(kernel_filename, &ep, NULL, &is_linux, 424 translate_phys_addr, cpu); 425 if (success > 0 && is_linux) { 426 entry_point = ep; 427 } else { 428 error_report("could not load kernel '%s'", 429 kernel_filename); 430 exit(EXIT_FAILURE); 431 } 432 } 433 if (entry_point != env->pc) { 434 uint8_t boot[] = { 435 #ifdef TARGET_WORDS_BIGENDIAN 436 0x60, 0x00, 0x08, /* j 1f */ 437 0x00, /* .literal_position */ 438 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 439 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 440 /* 1: */ 441 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 442 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 443 0x0a, 0x00, 0x00, /* jx a0 */ 444 #else 445 0x06, 0x02, 0x00, /* j 1f */ 446 0x00, /* .literal_position */ 447 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 448 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 449 /* 1: */ 450 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 451 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 452 0xa0, 0x00, 0x00, /* jx a0 */ 453 #endif 454 }; 455 uint32_t entry_pc = tswap32(entry_point); 456 uint32_t entry_a2 = tswap32(tagptr); 457 458 memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); 459 memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); 460 cpu_physical_memory_write(env->pc, boot, sizeof(boot)); 461 } 462 } else { 463 if (flash) { 464 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); 465 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); 466 uint32_t size = env->config->sysrom.location[0].size; 467 468 if (board->flash->size - board->flash->boot_base < size) { 469 size = board->flash->size - board->flash->boot_base; 470 } 471 472 memory_region_init_alias(flash_io, NULL, "xtfpga.flash", 473 flash_mr, board->flash->boot_base, size); 474 memory_region_add_subregion(system_memory, 475 env->config->sysrom.location[0].addr, 476 flash_io); 477 } else { 478 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 479 system_memory); 480 } 481 } 482 } 483 484 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) 485 486 static const hwaddr xtfpga_mmu_io[2] = { 487 0xf0000000, 488 }; 489 490 static const hwaddr xtfpga_nommu_io[2] = { 491 0x90000000, 492 0x70000000, 493 }; 494 495 static const XtfpgaFlashDesc lx60_flash = { 496 .base = 0x08000000, 497 .size = 0x00400000, 498 .sector_size = 0x10000, 499 }; 500 501 static void xtfpga_lx60_init(MachineState *machine) 502 { 503 static const XtfpgaBoardDesc lx60_board = { 504 .flash = &lx60_flash, 505 .sram_size = 0x20000, 506 .io = xtfpga_mmu_io, 507 }; 508 xtfpga_init(&lx60_board, machine); 509 } 510 511 static void xtfpga_lx60_nommu_init(MachineState *machine) 512 { 513 static const XtfpgaBoardDesc lx60_board = { 514 .flash = &lx60_flash, 515 .sram_size = 0x20000, 516 .io = xtfpga_nommu_io, 517 }; 518 xtfpga_init(&lx60_board, machine); 519 } 520 521 static const XtfpgaFlashDesc lx200_flash = { 522 .base = 0x08000000, 523 .size = 0x01000000, 524 .sector_size = 0x20000, 525 }; 526 527 static void xtfpga_lx200_init(MachineState *machine) 528 { 529 static const XtfpgaBoardDesc lx200_board = { 530 .flash = &lx200_flash, 531 .sram_size = 0x2000000, 532 .io = xtfpga_mmu_io, 533 }; 534 xtfpga_init(&lx200_board, machine); 535 } 536 537 static void xtfpga_lx200_nommu_init(MachineState *machine) 538 { 539 static const XtfpgaBoardDesc lx200_board = { 540 .flash = &lx200_flash, 541 .sram_size = 0x2000000, 542 .io = xtfpga_nommu_io, 543 }; 544 xtfpga_init(&lx200_board, machine); 545 } 546 547 static const XtfpgaFlashDesc ml605_flash = { 548 .base = 0x08000000, 549 .size = 0x01000000, 550 .sector_size = 0x20000, 551 }; 552 553 static void xtfpga_ml605_init(MachineState *machine) 554 { 555 static const XtfpgaBoardDesc ml605_board = { 556 .flash = &ml605_flash, 557 .sram_size = 0x2000000, 558 .io = xtfpga_mmu_io, 559 }; 560 xtfpga_init(&ml605_board, machine); 561 } 562 563 static void xtfpga_ml605_nommu_init(MachineState *machine) 564 { 565 static const XtfpgaBoardDesc ml605_board = { 566 .flash = &ml605_flash, 567 .sram_size = 0x2000000, 568 .io = xtfpga_nommu_io, 569 }; 570 xtfpga_init(&ml605_board, machine); 571 } 572 573 static const XtfpgaFlashDesc kc705_flash = { 574 .base = 0x00000000, 575 .size = 0x08000000, 576 .boot_base = 0x06000000, 577 .sector_size = 0x20000, 578 }; 579 580 static void xtfpga_kc705_init(MachineState *machine) 581 { 582 static const XtfpgaBoardDesc kc705_board = { 583 .flash = &kc705_flash, 584 .sram_size = 0x2000000, 585 .io = xtfpga_mmu_io, 586 }; 587 xtfpga_init(&kc705_board, machine); 588 } 589 590 static void xtfpga_kc705_nommu_init(MachineState *machine) 591 { 592 static const XtfpgaBoardDesc kc705_board = { 593 .flash = &kc705_flash, 594 .sram_size = 0x2000000, 595 .io = xtfpga_nommu_io, 596 }; 597 xtfpga_init(&kc705_board, machine); 598 } 599 600 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) 601 { 602 MachineClass *mc = MACHINE_CLASS(oc); 603 604 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 605 mc->init = xtfpga_lx60_init; 606 mc->max_cpus = 32; 607 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 608 mc->default_ram_size = 64 * MiB; 609 } 610 611 static const TypeInfo xtfpga_lx60_type = { 612 .name = MACHINE_TYPE_NAME("lx60"), 613 .parent = TYPE_MACHINE, 614 .class_init = xtfpga_lx60_class_init, 615 }; 616 617 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) 618 { 619 MachineClass *mc = MACHINE_CLASS(oc); 620 621 mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 622 mc->init = xtfpga_lx60_nommu_init; 623 mc->max_cpus = 32; 624 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 625 mc->default_ram_size = 64 * MiB; 626 } 627 628 static const TypeInfo xtfpga_lx60_nommu_type = { 629 .name = MACHINE_TYPE_NAME("lx60-nommu"), 630 .parent = TYPE_MACHINE, 631 .class_init = xtfpga_lx60_nommu_class_init, 632 }; 633 634 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) 635 { 636 MachineClass *mc = MACHINE_CLASS(oc); 637 638 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 639 mc->init = xtfpga_lx200_init; 640 mc->max_cpus = 32; 641 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 642 mc->default_ram_size = 96 * MiB; 643 } 644 645 static const TypeInfo xtfpga_lx200_type = { 646 .name = MACHINE_TYPE_NAME("lx200"), 647 .parent = TYPE_MACHINE, 648 .class_init = xtfpga_lx200_class_init, 649 }; 650 651 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) 652 { 653 MachineClass *mc = MACHINE_CLASS(oc); 654 655 mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 656 mc->init = xtfpga_lx200_nommu_init; 657 mc->max_cpus = 32; 658 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 659 mc->default_ram_size = 96 * MiB; 660 } 661 662 static const TypeInfo xtfpga_lx200_nommu_type = { 663 .name = MACHINE_TYPE_NAME("lx200-nommu"), 664 .parent = TYPE_MACHINE, 665 .class_init = xtfpga_lx200_nommu_class_init, 666 }; 667 668 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) 669 { 670 MachineClass *mc = MACHINE_CLASS(oc); 671 672 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 673 mc->init = xtfpga_ml605_init; 674 mc->max_cpus = 32; 675 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 676 mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 677 } 678 679 static const TypeInfo xtfpga_ml605_type = { 680 .name = MACHINE_TYPE_NAME("ml605"), 681 .parent = TYPE_MACHINE, 682 .class_init = xtfpga_ml605_class_init, 683 }; 684 685 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) 686 { 687 MachineClass *mc = MACHINE_CLASS(oc); 688 689 mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 690 mc->init = xtfpga_ml605_nommu_init; 691 mc->max_cpus = 32; 692 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 693 mc->default_ram_size = 256 * MiB; 694 } 695 696 static const TypeInfo xtfpga_ml605_nommu_type = { 697 .name = MACHINE_TYPE_NAME("ml605-nommu"), 698 .parent = TYPE_MACHINE, 699 .class_init = xtfpga_ml605_nommu_class_init, 700 }; 701 702 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) 703 { 704 MachineClass *mc = MACHINE_CLASS(oc); 705 706 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 707 mc->init = xtfpga_kc705_init; 708 mc->max_cpus = 32; 709 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 710 mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 711 } 712 713 static const TypeInfo xtfpga_kc705_type = { 714 .name = MACHINE_TYPE_NAME("kc705"), 715 .parent = TYPE_MACHINE, 716 .class_init = xtfpga_kc705_class_init, 717 }; 718 719 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) 720 { 721 MachineClass *mc = MACHINE_CLASS(oc); 722 723 mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 724 mc->init = xtfpga_kc705_nommu_init; 725 mc->max_cpus = 32; 726 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 727 mc->default_ram_size = 256 * MiB; 728 } 729 730 static const TypeInfo xtfpga_kc705_nommu_type = { 731 .name = MACHINE_TYPE_NAME("kc705-nommu"), 732 .parent = TYPE_MACHINE, 733 .class_init = xtfpga_kc705_nommu_class_init, 734 }; 735 736 static void xtfpga_machines_init(void) 737 { 738 type_register_static(&xtfpga_lx60_type); 739 type_register_static(&xtfpga_lx200_type); 740 type_register_static(&xtfpga_ml605_type); 741 type_register_static(&xtfpga_kc705_type); 742 type_register_static(&xtfpga_lx60_nommu_type); 743 type_register_static(&xtfpga_lx200_nommu_type); 744 type_register_static(&xtfpga_ml605_nommu_type); 745 type_register_static(&xtfpga_kc705_nommu_type); 746 } 747 748 type_init(xtfpga_machines_init) 749