1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "sysemu/sysemu.h" 29 #include "hw/boards.h" 30 #include "hw/loader.h" 31 #include "elf.h" 32 #include "exec/memory.h" 33 #include "exec/address-spaces.h" 34 #include "hw/char/serial.h" 35 #include "net/net.h" 36 #include "hw/sysbus.h" 37 #include "hw/block/flash.h" 38 #include "sysemu/block-backend.h" 39 #include "sysemu/char.h" 40 #include "sysemu/device_tree.h" 41 #include "qemu/error-report.h" 42 #include "bootparam.h" 43 44 typedef struct LxBoardDesc { 45 hwaddr flash_base; 46 size_t flash_size; 47 size_t flash_boot_base; 48 size_t flash_sector_size; 49 size_t sram_size; 50 } LxBoardDesc; 51 52 typedef struct Lx60FpgaState { 53 MemoryRegion iomem; 54 uint32_t leds; 55 uint32_t switches; 56 } Lx60FpgaState; 57 58 static void lx60_fpga_reset(void *opaque) 59 { 60 Lx60FpgaState *s = opaque; 61 62 s->leds = 0; 63 s->switches = 0; 64 } 65 66 static uint64_t lx60_fpga_read(void *opaque, hwaddr addr, 67 unsigned size) 68 { 69 Lx60FpgaState *s = opaque; 70 71 switch (addr) { 72 case 0x0: /*build date code*/ 73 return 0x09272011; 74 75 case 0x4: /*processor clock frequency, Hz*/ 76 return 10000000; 77 78 case 0x8: /*LEDs (off = 0, on = 1)*/ 79 return s->leds; 80 81 case 0xc: /*DIP switches (off = 0, on = 1)*/ 82 return s->switches; 83 } 84 return 0; 85 } 86 87 static void lx60_fpga_write(void *opaque, hwaddr addr, 88 uint64_t val, unsigned size) 89 { 90 Lx60FpgaState *s = opaque; 91 92 switch (addr) { 93 case 0x8: /*LEDs (off = 0, on = 1)*/ 94 s->leds = val; 95 break; 96 97 case 0x10: /*board reset*/ 98 if (val == 0xdead) { 99 qemu_system_reset_request(); 100 } 101 break; 102 } 103 } 104 105 static const MemoryRegionOps lx60_fpga_ops = { 106 .read = lx60_fpga_read, 107 .write = lx60_fpga_write, 108 .endianness = DEVICE_NATIVE_ENDIAN, 109 }; 110 111 static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space, 112 hwaddr base) 113 { 114 Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState)); 115 116 memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s, 117 "lx60.fpga", 0x10000); 118 memory_region_add_subregion(address_space, base, &s->iomem); 119 lx60_fpga_reset(s); 120 qemu_register_reset(lx60_fpga_reset, s); 121 return s; 122 } 123 124 static void lx60_net_init(MemoryRegion *address_space, 125 hwaddr base, 126 hwaddr descriptors, 127 hwaddr buffers, 128 qemu_irq irq, NICInfo *nd) 129 { 130 DeviceState *dev; 131 SysBusDevice *s; 132 MemoryRegion *ram; 133 134 dev = qdev_create(NULL, "open_eth"); 135 qdev_set_nic_properties(dev, nd); 136 qdev_init_nofail(dev); 137 138 s = SYS_BUS_DEVICE(dev); 139 sysbus_connect_irq(s, 0, irq); 140 memory_region_add_subregion(address_space, base, 141 sysbus_mmio_get_region(s, 0)); 142 memory_region_add_subregion(address_space, descriptors, 143 sysbus_mmio_get_region(s, 1)); 144 145 ram = g_malloc(sizeof(*ram)); 146 memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384, &error_abort); 147 vmstate_register_ram_global(ram); 148 memory_region_add_subregion(address_space, buffers, ram); 149 } 150 151 static uint64_t translate_phys_addr(void *opaque, uint64_t addr) 152 { 153 XtensaCPU *cpu = opaque; 154 155 return cpu_get_phys_page_debug(CPU(cpu), addr); 156 } 157 158 static void lx60_reset(void *opaque) 159 { 160 XtensaCPU *cpu = opaque; 161 162 cpu_reset(CPU(cpu)); 163 } 164 165 static uint64_t lx60_io_read(void *opaque, hwaddr addr, 166 unsigned size) 167 { 168 return 0; 169 } 170 171 static void lx60_io_write(void *opaque, hwaddr addr, 172 uint64_t val, unsigned size) 173 { 174 } 175 176 static const MemoryRegionOps lx60_io_ops = { 177 .read = lx60_io_read, 178 .write = lx60_io_write, 179 .endianness = DEVICE_NATIVE_ENDIAN, 180 }; 181 182 static void lx_init(const LxBoardDesc *board, MachineState *machine) 183 { 184 #ifdef TARGET_WORDS_BIGENDIAN 185 int be = 1; 186 #else 187 int be = 0; 188 #endif 189 MemoryRegion *system_memory = get_system_memory(); 190 XtensaCPU *cpu = NULL; 191 CPUXtensaState *env = NULL; 192 MemoryRegion *ram, *rom, *system_io; 193 DriveInfo *dinfo; 194 pflash_t *flash = NULL; 195 QemuOpts *machine_opts = qemu_get_machine_opts(); 196 const char *cpu_model = machine->cpu_model; 197 const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); 198 const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); 199 const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); 200 const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); 201 int n; 202 203 if (!cpu_model) { 204 cpu_model = XTENSA_DEFAULT_CPU_MODEL; 205 } 206 207 for (n = 0; n < smp_cpus; n++) { 208 cpu = cpu_xtensa_init(cpu_model); 209 if (cpu == NULL) { 210 error_report("unable to find CPU definition '%s'", 211 cpu_model); 212 exit(EXIT_FAILURE); 213 } 214 env = &cpu->env; 215 216 env->sregs[PRID] = n; 217 qemu_register_reset(lx60_reset, cpu); 218 /* Need MMU initialized prior to ELF loading, 219 * so that ELF gets loaded into virtual addresses 220 */ 221 cpu_reset(CPU(cpu)); 222 } 223 224 ram = g_malloc(sizeof(*ram)); 225 memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size, 226 &error_abort); 227 vmstate_register_ram_global(ram); 228 memory_region_add_subregion(system_memory, 0, ram); 229 230 system_io = g_malloc(sizeof(*system_io)); 231 memory_region_init_io(system_io, NULL, &lx60_io_ops, NULL, "lx60.io", 232 224 * 1024 * 1024); 233 memory_region_add_subregion(system_memory, 0xf0000000, system_io); 234 lx60_fpga_init(system_io, 0x0d020000); 235 if (nd_table[0].used) { 236 lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, 237 xtensa_get_extint(env, 1), nd_table); 238 } 239 240 if (!serial_hds[0]) { 241 serial_hds[0] = qemu_chr_new("serial0", "null", NULL); 242 } 243 244 serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), 245 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); 246 247 dinfo = drive_get(IF_PFLASH, 0, 0); 248 if (dinfo) { 249 flash = pflash_cfi01_register(board->flash_base, 250 NULL, "lx60.io.flash", board->flash_size, 251 blk_by_legacy_dinfo(dinfo), 252 board->flash_sector_size, 253 board->flash_size / board->flash_sector_size, 254 4, 0x0000, 0x0000, 0x0000, 0x0000, be); 255 if (flash == NULL) { 256 error_report("unable to mount pflash"); 257 exit(EXIT_FAILURE); 258 } 259 } 260 261 /* Use presence of kernel file name as 'boot from SRAM' switch. */ 262 if (kernel_filename) { 263 uint32_t entry_point = env->pc; 264 size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ 265 uint32_t tagptr = 0xfe000000 + board->sram_size; 266 uint32_t cur_tagptr; 267 BpMemInfo memory_location = { 268 .type = tswap32(MEMORY_TYPE_CONVENTIONAL), 269 .start = tswap32(0), 270 .end = tswap32(machine->ram_size), 271 }; 272 uint32_t lowmem_end = machine->ram_size < 0x08000000 ? 273 machine->ram_size : 0x08000000; 274 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); 275 276 rom = g_malloc(sizeof(*rom)); 277 memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size, 278 &error_abort); 279 vmstate_register_ram_global(rom); 280 memory_region_add_subregion(system_memory, 0xfe000000, rom); 281 282 if (kernel_cmdline) { 283 bp_size += get_tag_size(strlen(kernel_cmdline) + 1); 284 } 285 if (dtb_filename) { 286 bp_size += get_tag_size(sizeof(uint32_t)); 287 } 288 if (initrd_filename) { 289 bp_size += get_tag_size(sizeof(BpMemInfo)); 290 } 291 292 /* Put kernel bootparameters to the end of that SRAM */ 293 tagptr = (tagptr - bp_size) & ~0xff; 294 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); 295 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, 296 sizeof(memory_location), &memory_location); 297 298 if (kernel_cmdline) { 299 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, 300 strlen(kernel_cmdline) + 1, kernel_cmdline); 301 } 302 if (dtb_filename) { 303 int fdt_size; 304 void *fdt = load_device_tree(dtb_filename, &fdt_size); 305 uint32_t dtb_addr = tswap32(cur_lowmem); 306 307 if (!fdt) { 308 error_report("could not load DTB '%s'", dtb_filename); 309 exit(EXIT_FAILURE); 310 } 311 312 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); 313 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, 314 sizeof(dtb_addr), &dtb_addr); 315 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096); 316 } 317 if (initrd_filename) { 318 BpMemInfo initrd_location = { 0 }; 319 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, 320 lowmem_end - cur_lowmem); 321 322 if (initrd_size < 0) { 323 initrd_size = load_image_targphys(initrd_filename, 324 cur_lowmem, 325 lowmem_end - cur_lowmem); 326 } 327 if (initrd_size < 0) { 328 error_report("could not load initrd '%s'", initrd_filename); 329 exit(EXIT_FAILURE); 330 } 331 initrd_location.start = tswap32(cur_lowmem); 332 initrd_location.end = tswap32(cur_lowmem + initrd_size); 333 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, 334 sizeof(initrd_location), &initrd_location); 335 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096); 336 } 337 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); 338 env->regs[2] = tagptr; 339 340 uint64_t elf_entry; 341 uint64_t elf_lowaddr; 342 int success = load_elf(kernel_filename, translate_phys_addr, cpu, 343 &elf_entry, &elf_lowaddr, NULL, be, ELF_MACHINE, 0); 344 if (success > 0) { 345 entry_point = elf_entry; 346 } else { 347 hwaddr ep; 348 int is_linux; 349 success = load_uimage(kernel_filename, &ep, NULL, &is_linux, 350 translate_phys_addr, cpu); 351 if (success > 0 && is_linux) { 352 entry_point = ep; 353 } else { 354 error_report("could not load kernel '%s'", 355 kernel_filename); 356 exit(EXIT_FAILURE); 357 } 358 } 359 if (entry_point != env->pc) { 360 static const uint8_t jx_a0[] = { 361 #ifdef TARGET_WORDS_BIGENDIAN 362 0x0a, 0, 0, 363 #else 364 0xa0, 0, 0, 365 #endif 366 }; 367 env->regs[0] = entry_point; 368 cpu_physical_memory_write(env->pc, jx_a0, sizeof(jx_a0)); 369 } 370 } else { 371 if (flash) { 372 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); 373 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); 374 375 memory_region_init_alias(flash_io, NULL, "lx60.flash", 376 flash_mr, board->flash_boot_base, 377 board->flash_size - board->flash_boot_base < 0x02000000 ? 378 board->flash_size - board->flash_boot_base : 0x02000000); 379 memory_region_add_subregion(system_memory, 0xfe000000, 380 flash_io); 381 } 382 } 383 } 384 385 static void xtensa_lx60_init(MachineState *machine) 386 { 387 static const LxBoardDesc lx60_board = { 388 .flash_base = 0xf8000000, 389 .flash_size = 0x00400000, 390 .flash_sector_size = 0x10000, 391 .sram_size = 0x20000, 392 }; 393 lx_init(&lx60_board, machine); 394 } 395 396 static void xtensa_lx200_init(MachineState *machine) 397 { 398 static const LxBoardDesc lx200_board = { 399 .flash_base = 0xf8000000, 400 .flash_size = 0x01000000, 401 .flash_sector_size = 0x20000, 402 .sram_size = 0x2000000, 403 }; 404 lx_init(&lx200_board, machine); 405 } 406 407 static void xtensa_ml605_init(MachineState *machine) 408 { 409 static const LxBoardDesc ml605_board = { 410 .flash_base = 0xf8000000, 411 .flash_size = 0x01000000, 412 .flash_sector_size = 0x20000, 413 .sram_size = 0x2000000, 414 }; 415 lx_init(&ml605_board, machine); 416 } 417 418 static void xtensa_kc705_init(MachineState *machine) 419 { 420 static const LxBoardDesc kc705_board = { 421 .flash_base = 0xf0000000, 422 .flash_size = 0x08000000, 423 .flash_boot_base = 0x06000000, 424 .flash_sector_size = 0x20000, 425 .sram_size = 0x2000000, 426 }; 427 lx_init(&kc705_board, machine); 428 } 429 430 static QEMUMachine xtensa_lx60_machine = { 431 .name = "lx60", 432 .desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")", 433 .init = xtensa_lx60_init, 434 .max_cpus = 4, 435 }; 436 437 static QEMUMachine xtensa_lx200_machine = { 438 .name = "lx200", 439 .desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")", 440 .init = xtensa_lx200_init, 441 .max_cpus = 4, 442 }; 443 444 static QEMUMachine xtensa_ml605_machine = { 445 .name = "ml605", 446 .desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")", 447 .init = xtensa_ml605_init, 448 .max_cpus = 4, 449 }; 450 451 static QEMUMachine xtensa_kc705_machine = { 452 .name = "kc705", 453 .desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")", 454 .init = xtensa_kc705_init, 455 .max_cpus = 4, 456 }; 457 458 static void xtensa_lx_machines_init(void) 459 { 460 qemu_register_machine(&xtensa_lx60_machine); 461 qemu_register_machine(&xtensa_lx200_machine); 462 qemu_register_machine(&xtensa_ml605_machine); 463 qemu_register_machine(&xtensa_kc705_machine); 464 } 465 466 machine_init(xtensa_lx_machines_init); 467