1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "cpu.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/boards.h" 34 #include "hw/loader.h" 35 #include "hw/qdev-properties.h" 36 #include "elf.h" 37 #include "exec/memory.h" 38 #include "exec/address-spaces.h" 39 #include "hw/char/serial.h" 40 #include "net/net.h" 41 #include "hw/sysbus.h" 42 #include "hw/block/flash.h" 43 #include "chardev/char.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/reset.h" 46 #include "sysemu/runstate.h" 47 #include "qemu/error-report.h" 48 #include "qemu/option.h" 49 #include "bootparam.h" 50 #include "xtensa_memory.h" 51 #include "hw/xtensa/mx_pic.h" 52 #include "migration/vmstate.h" 53 54 typedef struct XtfpgaFlashDesc { 55 hwaddr base; 56 size_t size; 57 size_t boot_base; 58 size_t sector_size; 59 } XtfpgaFlashDesc; 60 61 typedef struct XtfpgaBoardDesc { 62 const XtfpgaFlashDesc *flash; 63 size_t sram_size; 64 const hwaddr *io; 65 } XtfpgaBoardDesc; 66 67 typedef struct XtfpgaFpgaState { 68 MemoryRegion iomem; 69 uint32_t freq; 70 uint32_t leds; 71 uint32_t switches; 72 } XtfpgaFpgaState; 73 74 static void xtfpga_fpga_reset(void *opaque) 75 { 76 XtfpgaFpgaState *s = opaque; 77 78 s->leds = 0; 79 s->switches = 0; 80 } 81 82 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, 83 unsigned size) 84 { 85 XtfpgaFpgaState *s = opaque; 86 87 switch (addr) { 88 case 0x0: /*build date code*/ 89 return 0x09272011; 90 91 case 0x4: /*processor clock frequency, Hz*/ 92 return s->freq; 93 94 case 0x8: /*LEDs (off = 0, on = 1)*/ 95 return s->leds; 96 97 case 0xc: /*DIP switches (off = 0, on = 1)*/ 98 return s->switches; 99 } 100 return 0; 101 } 102 103 static void xtfpga_fpga_write(void *opaque, hwaddr addr, 104 uint64_t val, unsigned size) 105 { 106 XtfpgaFpgaState *s = opaque; 107 108 switch (addr) { 109 case 0x8: /*LEDs (off = 0, on = 1)*/ 110 s->leds = val; 111 break; 112 113 case 0x10: /*board reset*/ 114 if (val == 0xdead) { 115 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 116 } 117 break; 118 } 119 } 120 121 static const MemoryRegionOps xtfpga_fpga_ops = { 122 .read = xtfpga_fpga_read, 123 .write = xtfpga_fpga_write, 124 .endianness = DEVICE_NATIVE_ENDIAN, 125 }; 126 127 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, 128 hwaddr base, uint32_t freq) 129 { 130 XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState)); 131 132 memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, 133 "xtfpga.fpga", 0x10000); 134 memory_region_add_subregion(address_space, base, &s->iomem); 135 s->freq = freq; 136 xtfpga_fpga_reset(s); 137 qemu_register_reset(xtfpga_fpga_reset, s); 138 return s; 139 } 140 141 static void xtfpga_net_init(MemoryRegion *address_space, 142 hwaddr base, 143 hwaddr descriptors, 144 hwaddr buffers, 145 qemu_irq irq, NICInfo *nd) 146 { 147 DeviceState *dev; 148 SysBusDevice *s; 149 MemoryRegion *ram; 150 151 dev = qdev_create(NULL, "open_eth"); 152 qdev_set_nic_properties(dev, nd); 153 qdev_init_nofail(dev); 154 155 s = SYS_BUS_DEVICE(dev); 156 sysbus_connect_irq(s, 0, irq); 157 memory_region_add_subregion(address_space, base, 158 sysbus_mmio_get_region(s, 0)); 159 memory_region_add_subregion(address_space, descriptors, 160 sysbus_mmio_get_region(s, 1)); 161 162 ram = g_malloc(sizeof(*ram)); 163 memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, 164 &error_fatal); 165 vmstate_register_ram_global(ram); 166 memory_region_add_subregion(address_space, buffers, ram); 167 } 168 169 static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, 170 const XtfpgaBoardDesc *board, 171 DriveInfo *dinfo, int be) 172 { 173 SysBusDevice *s; 174 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); 175 176 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 177 &error_abort); 178 qdev_prop_set_uint32(dev, "num-blocks", 179 board->flash->size / board->flash->sector_size); 180 qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); 181 qdev_prop_set_uint8(dev, "width", 2); 182 qdev_prop_set_bit(dev, "big-endian", be); 183 qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 184 qdev_init_nofail(dev); 185 s = SYS_BUS_DEVICE(dev); 186 memory_region_add_subregion(address_space, board->flash->base, 187 sysbus_mmio_get_region(s, 0)); 188 return PFLASH_CFI01(dev); 189 } 190 191 static uint64_t translate_phys_addr(void *opaque, uint64_t addr) 192 { 193 XtensaCPU *cpu = opaque; 194 195 return cpu_get_phys_page_debug(CPU(cpu), addr); 196 } 197 198 static void xtfpga_reset(void *opaque) 199 { 200 XtensaCPU *cpu = opaque; 201 202 cpu_reset(CPU(cpu)); 203 } 204 205 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, 206 unsigned size) 207 { 208 return 0; 209 } 210 211 static void xtfpga_io_write(void *opaque, hwaddr addr, 212 uint64_t val, unsigned size) 213 { 214 } 215 216 static const MemoryRegionOps xtfpga_io_ops = { 217 .read = xtfpga_io_read, 218 .write = xtfpga_io_write, 219 .endianness = DEVICE_NATIVE_ENDIAN, 220 }; 221 222 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 223 { 224 #ifdef TARGET_WORDS_BIGENDIAN 225 int be = 1; 226 #else 227 int be = 0; 228 #endif 229 MemoryRegion *system_memory = get_system_memory(); 230 XtensaCPU *cpu = NULL; 231 CPUXtensaState *env = NULL; 232 MemoryRegion *system_io; 233 XtensaMxPic *mx_pic = NULL; 234 qemu_irq *extints; 235 DriveInfo *dinfo; 236 PFlashCFI01 *flash = NULL; 237 QemuOpts *machine_opts = qemu_get_machine_opts(); 238 const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); 239 const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); 240 const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); 241 const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); 242 const unsigned system_io_size = 224 * MiB; 243 uint32_t freq = 10000000; 244 int n; 245 unsigned int smp_cpus = machine->smp.cpus; 246 247 if (smp_cpus > 1) { 248 mx_pic = xtensa_mx_pic_init(31); 249 qemu_register_reset(xtensa_mx_pic_reset, mx_pic); 250 } 251 for (n = 0; n < smp_cpus; n++) { 252 CPUXtensaState *cenv = NULL; 253 254 cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); 255 cenv = &cpu->env; 256 if (!env) { 257 env = cenv; 258 freq = env->config->clock_freq_khz * 1000; 259 } 260 261 if (mx_pic) { 262 MemoryRegion *mx_eri; 263 264 mx_eri = xtensa_mx_pic_register_cpu(mx_pic, 265 xtensa_get_extints(cenv), 266 xtensa_get_runstall(cenv)); 267 memory_region_add_subregion(xtensa_get_er_region(cenv), 268 0, mx_eri); 269 } 270 cenv->sregs[PRID] = n; 271 xtensa_select_static_vectors(cenv, n != 0); 272 qemu_register_reset(xtfpga_reset, cpu); 273 /* Need MMU initialized prior to ELF loading, 274 * so that ELF gets loaded into virtual addresses 275 */ 276 cpu_reset(CPU(cpu)); 277 } 278 if (smp_cpus > 1) { 279 extints = xtensa_mx_pic_get_extints(mx_pic); 280 } else { 281 extints = xtensa_get_extints(env); 282 } 283 284 if (env) { 285 XtensaMemory sysram = env->config->sysram; 286 287 sysram.location[0].size = machine->ram_size; 288 xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", 289 system_memory); 290 xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", 291 system_memory); 292 xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", 293 system_memory); 294 xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", 295 system_memory); 296 xtensa_create_memory_regions(&sysram, "xtensa.sysram", 297 system_memory); 298 } 299 300 system_io = g_malloc(sizeof(*system_io)); 301 memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", 302 system_io_size); 303 memory_region_add_subregion(system_memory, board->io[0], system_io); 304 if (board->io[1]) { 305 MemoryRegion *io = g_malloc(sizeof(*io)); 306 307 memory_region_init_alias(io, NULL, "xtfpga.io.cached", 308 system_io, 0, system_io_size); 309 memory_region_add_subregion(system_memory, board->io[1], io); 310 } 311 xtfpga_fpga_init(system_io, 0x0d020000, freq); 312 if (nd_table[0].used) { 313 xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, 314 extints[1], nd_table); 315 } 316 317 serial_mm_init(system_io, 0x0d050020, 2, extints[0], 318 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 319 320 dinfo = drive_get(IF_PFLASH, 0, 0); 321 if (dinfo) { 322 flash = xtfpga_flash_init(system_io, board, dinfo, be); 323 } 324 325 /* Use presence of kernel file name as 'boot from SRAM' switch. */ 326 if (kernel_filename) { 327 uint32_t entry_point = env->pc; 328 size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ 329 uint32_t tagptr = env->config->sysrom.location[0].addr + 330 board->sram_size; 331 uint32_t cur_tagptr; 332 BpMemInfo memory_location = { 333 .type = tswap32(MEMORY_TYPE_CONVENTIONAL), 334 .start = tswap32(env->config->sysram.location[0].addr), 335 .end = tswap32(env->config->sysram.location[0].addr + 336 machine->ram_size), 337 }; 338 uint32_t lowmem_end = machine->ram_size < 0x08000000 ? 339 machine->ram_size : 0x08000000; 340 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); 341 342 lowmem_end += env->config->sysram.location[0].addr; 343 cur_lowmem += env->config->sysram.location[0].addr; 344 345 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 346 system_memory); 347 348 if (kernel_cmdline) { 349 bp_size += get_tag_size(strlen(kernel_cmdline) + 1); 350 } 351 if (dtb_filename) { 352 bp_size += get_tag_size(sizeof(uint32_t)); 353 } 354 if (initrd_filename) { 355 bp_size += get_tag_size(sizeof(BpMemInfo)); 356 } 357 358 /* Put kernel bootparameters to the end of that SRAM */ 359 tagptr = (tagptr - bp_size) & ~0xff; 360 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); 361 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, 362 sizeof(memory_location), &memory_location); 363 364 if (kernel_cmdline) { 365 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, 366 strlen(kernel_cmdline) + 1, kernel_cmdline); 367 } 368 #ifdef CONFIG_FDT 369 if (dtb_filename) { 370 int fdt_size; 371 void *fdt = load_device_tree(dtb_filename, &fdt_size); 372 uint32_t dtb_addr = tswap32(cur_lowmem); 373 374 if (!fdt) { 375 error_report("could not load DTB '%s'", dtb_filename); 376 exit(EXIT_FAILURE); 377 } 378 379 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); 380 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, 381 sizeof(dtb_addr), &dtb_addr); 382 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); 383 } 384 #else 385 if (dtb_filename) { 386 error_report("could not load DTB '%s': " 387 "FDT support is not configured in QEMU", 388 dtb_filename); 389 exit(EXIT_FAILURE); 390 } 391 #endif 392 if (initrd_filename) { 393 BpMemInfo initrd_location = { 0 }; 394 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, 395 lowmem_end - cur_lowmem); 396 397 if (initrd_size < 0) { 398 initrd_size = load_image_targphys(initrd_filename, 399 cur_lowmem, 400 lowmem_end - cur_lowmem); 401 } 402 if (initrd_size < 0) { 403 error_report("could not load initrd '%s'", initrd_filename); 404 exit(EXIT_FAILURE); 405 } 406 initrd_location.start = tswap32(cur_lowmem); 407 initrd_location.end = tswap32(cur_lowmem + initrd_size); 408 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, 409 sizeof(initrd_location), &initrd_location); 410 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); 411 } 412 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); 413 env->regs[2] = tagptr; 414 415 uint64_t elf_entry; 416 uint64_t elf_lowaddr; 417 int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, 418 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0); 419 if (success > 0) { 420 entry_point = elf_entry; 421 } else { 422 hwaddr ep; 423 int is_linux; 424 success = load_uimage(kernel_filename, &ep, NULL, &is_linux, 425 translate_phys_addr, cpu); 426 if (success > 0 && is_linux) { 427 entry_point = ep; 428 } else { 429 error_report("could not load kernel '%s'", 430 kernel_filename); 431 exit(EXIT_FAILURE); 432 } 433 } 434 if (entry_point != env->pc) { 435 uint8_t boot[] = { 436 #ifdef TARGET_WORDS_BIGENDIAN 437 0x60, 0x00, 0x08, /* j 1f */ 438 0x00, /* .literal_position */ 439 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 440 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 441 /* 1: */ 442 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 443 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 444 0x0a, 0x00, 0x00, /* jx a0 */ 445 #else 446 0x06, 0x02, 0x00, /* j 1f */ 447 0x00, /* .literal_position */ 448 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 449 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 450 /* 1: */ 451 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 452 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 453 0xa0, 0x00, 0x00, /* jx a0 */ 454 #endif 455 }; 456 uint32_t entry_pc = tswap32(entry_point); 457 uint32_t entry_a2 = tswap32(tagptr); 458 459 memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); 460 memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); 461 cpu_physical_memory_write(env->pc, boot, sizeof(boot)); 462 } 463 } else { 464 if (flash) { 465 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); 466 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); 467 uint32_t size = env->config->sysrom.location[0].size; 468 469 if (board->flash->size - board->flash->boot_base < size) { 470 size = board->flash->size - board->flash->boot_base; 471 } 472 473 memory_region_init_alias(flash_io, NULL, "xtfpga.flash", 474 flash_mr, board->flash->boot_base, size); 475 memory_region_add_subregion(system_memory, 476 env->config->sysrom.location[0].addr, 477 flash_io); 478 } else { 479 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 480 system_memory); 481 } 482 } 483 } 484 485 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) 486 487 static const hwaddr xtfpga_mmu_io[2] = { 488 0xf0000000, 489 }; 490 491 static const hwaddr xtfpga_nommu_io[2] = { 492 0x90000000, 493 0x70000000, 494 }; 495 496 static const XtfpgaFlashDesc lx60_flash = { 497 .base = 0x08000000, 498 .size = 0x00400000, 499 .sector_size = 0x10000, 500 }; 501 502 static void xtfpga_lx60_init(MachineState *machine) 503 { 504 static const XtfpgaBoardDesc lx60_board = { 505 .flash = &lx60_flash, 506 .sram_size = 0x20000, 507 .io = xtfpga_mmu_io, 508 }; 509 xtfpga_init(&lx60_board, machine); 510 } 511 512 static void xtfpga_lx60_nommu_init(MachineState *machine) 513 { 514 static const XtfpgaBoardDesc lx60_board = { 515 .flash = &lx60_flash, 516 .sram_size = 0x20000, 517 .io = xtfpga_nommu_io, 518 }; 519 xtfpga_init(&lx60_board, machine); 520 } 521 522 static const XtfpgaFlashDesc lx200_flash = { 523 .base = 0x08000000, 524 .size = 0x01000000, 525 .sector_size = 0x20000, 526 }; 527 528 static void xtfpga_lx200_init(MachineState *machine) 529 { 530 static const XtfpgaBoardDesc lx200_board = { 531 .flash = &lx200_flash, 532 .sram_size = 0x2000000, 533 .io = xtfpga_mmu_io, 534 }; 535 xtfpga_init(&lx200_board, machine); 536 } 537 538 static void xtfpga_lx200_nommu_init(MachineState *machine) 539 { 540 static const XtfpgaBoardDesc lx200_board = { 541 .flash = &lx200_flash, 542 .sram_size = 0x2000000, 543 .io = xtfpga_nommu_io, 544 }; 545 xtfpga_init(&lx200_board, machine); 546 } 547 548 static const XtfpgaFlashDesc ml605_flash = { 549 .base = 0x08000000, 550 .size = 0x01000000, 551 .sector_size = 0x20000, 552 }; 553 554 static void xtfpga_ml605_init(MachineState *machine) 555 { 556 static const XtfpgaBoardDesc ml605_board = { 557 .flash = &ml605_flash, 558 .sram_size = 0x2000000, 559 .io = xtfpga_mmu_io, 560 }; 561 xtfpga_init(&ml605_board, machine); 562 } 563 564 static void xtfpga_ml605_nommu_init(MachineState *machine) 565 { 566 static const XtfpgaBoardDesc ml605_board = { 567 .flash = &ml605_flash, 568 .sram_size = 0x2000000, 569 .io = xtfpga_nommu_io, 570 }; 571 xtfpga_init(&ml605_board, machine); 572 } 573 574 static const XtfpgaFlashDesc kc705_flash = { 575 .base = 0x00000000, 576 .size = 0x08000000, 577 .boot_base = 0x06000000, 578 .sector_size = 0x20000, 579 }; 580 581 static void xtfpga_kc705_init(MachineState *machine) 582 { 583 static const XtfpgaBoardDesc kc705_board = { 584 .flash = &kc705_flash, 585 .sram_size = 0x2000000, 586 .io = xtfpga_mmu_io, 587 }; 588 xtfpga_init(&kc705_board, machine); 589 } 590 591 static void xtfpga_kc705_nommu_init(MachineState *machine) 592 { 593 static const XtfpgaBoardDesc kc705_board = { 594 .flash = &kc705_flash, 595 .sram_size = 0x2000000, 596 .io = xtfpga_nommu_io, 597 }; 598 xtfpga_init(&kc705_board, machine); 599 } 600 601 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) 602 { 603 MachineClass *mc = MACHINE_CLASS(oc); 604 605 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 606 mc->init = xtfpga_lx60_init; 607 mc->max_cpus = 32; 608 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 609 mc->default_ram_size = 64 * MiB; 610 } 611 612 static const TypeInfo xtfpga_lx60_type = { 613 .name = MACHINE_TYPE_NAME("lx60"), 614 .parent = TYPE_MACHINE, 615 .class_init = xtfpga_lx60_class_init, 616 }; 617 618 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) 619 { 620 MachineClass *mc = MACHINE_CLASS(oc); 621 622 mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 623 mc->init = xtfpga_lx60_nommu_init; 624 mc->max_cpus = 32; 625 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 626 mc->default_ram_size = 64 * MiB; 627 } 628 629 static const TypeInfo xtfpga_lx60_nommu_type = { 630 .name = MACHINE_TYPE_NAME("lx60-nommu"), 631 .parent = TYPE_MACHINE, 632 .class_init = xtfpga_lx60_nommu_class_init, 633 }; 634 635 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) 636 { 637 MachineClass *mc = MACHINE_CLASS(oc); 638 639 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 640 mc->init = xtfpga_lx200_init; 641 mc->max_cpus = 32; 642 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 643 mc->default_ram_size = 96 * MiB; 644 } 645 646 static const TypeInfo xtfpga_lx200_type = { 647 .name = MACHINE_TYPE_NAME("lx200"), 648 .parent = TYPE_MACHINE, 649 .class_init = xtfpga_lx200_class_init, 650 }; 651 652 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) 653 { 654 MachineClass *mc = MACHINE_CLASS(oc); 655 656 mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 657 mc->init = xtfpga_lx200_nommu_init; 658 mc->max_cpus = 32; 659 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 660 mc->default_ram_size = 96 * MiB; 661 } 662 663 static const TypeInfo xtfpga_lx200_nommu_type = { 664 .name = MACHINE_TYPE_NAME("lx200-nommu"), 665 .parent = TYPE_MACHINE, 666 .class_init = xtfpga_lx200_nommu_class_init, 667 }; 668 669 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) 670 { 671 MachineClass *mc = MACHINE_CLASS(oc); 672 673 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 674 mc->init = xtfpga_ml605_init; 675 mc->max_cpus = 32; 676 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 677 mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 678 } 679 680 static const TypeInfo xtfpga_ml605_type = { 681 .name = MACHINE_TYPE_NAME("ml605"), 682 .parent = TYPE_MACHINE, 683 .class_init = xtfpga_ml605_class_init, 684 }; 685 686 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) 687 { 688 MachineClass *mc = MACHINE_CLASS(oc); 689 690 mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 691 mc->init = xtfpga_ml605_nommu_init; 692 mc->max_cpus = 32; 693 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 694 mc->default_ram_size = 256 * MiB; 695 } 696 697 static const TypeInfo xtfpga_ml605_nommu_type = { 698 .name = MACHINE_TYPE_NAME("ml605-nommu"), 699 .parent = TYPE_MACHINE, 700 .class_init = xtfpga_ml605_nommu_class_init, 701 }; 702 703 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) 704 { 705 MachineClass *mc = MACHINE_CLASS(oc); 706 707 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 708 mc->init = xtfpga_kc705_init; 709 mc->max_cpus = 32; 710 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 711 mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 712 } 713 714 static const TypeInfo xtfpga_kc705_type = { 715 .name = MACHINE_TYPE_NAME("kc705"), 716 .parent = TYPE_MACHINE, 717 .class_init = xtfpga_kc705_class_init, 718 }; 719 720 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) 721 { 722 MachineClass *mc = MACHINE_CLASS(oc); 723 724 mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 725 mc->init = xtfpga_kc705_nommu_init; 726 mc->max_cpus = 32; 727 mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 728 mc->default_ram_size = 256 * MiB; 729 } 730 731 static const TypeInfo xtfpga_kc705_nommu_type = { 732 .name = MACHINE_TYPE_NAME("kc705-nommu"), 733 .parent = TYPE_MACHINE, 734 .class_init = xtfpga_kc705_nommu_class_init, 735 }; 736 737 static void xtfpga_machines_init(void) 738 { 739 type_register_static(&xtfpga_lx60_type); 740 type_register_static(&xtfpga_lx200_type); 741 type_register_static(&xtfpga_ml605_type); 742 type_register_static(&xtfpga_kc705_type); 743 type_register_static(&xtfpga_lx60_nommu_type); 744 type_register_static(&xtfpga_lx200_nommu_type); 745 type_register_static(&xtfpga_ml605_nommu_type); 746 type_register_static(&xtfpga_kc705_nommu_type); 747 } 748 749 type_init(xtfpga_machines_init) 750