xref: /openbmc/qemu/hw/xtensa/xtfpga.c (revision 10df8ff1)
1 /*
2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *     * Redistributions of source code must retain the above copyright
8  *       notice, this list of conditions and the following disclaimer.
9  *     * Redistributions in binary form must reproduce the above copyright
10  *       notice, this list of conditions and the following disclaimer in the
11  *       documentation and/or other materials provided with the distribution.
12  *     * Neither the name of the Open Source and Linux Lab nor the
13  *       names of its contributors may be used to endorse or promote products
14  *       derived from this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #include "qemu/osdep.h"
29 #include "qemu/units.h"
30 #include "qapi/error.h"
31 #include "cpu.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/boards.h"
34 #include "hw/loader.h"
35 #include "elf.h"
36 #include "exec/memory.h"
37 #include "exec/address-spaces.h"
38 #include "hw/char/serial.h"
39 #include "net/net.h"
40 #include "hw/sysbus.h"
41 #include "hw/block/flash.h"
42 #include "chardev/char.h"
43 #include "sysemu/device_tree.h"
44 #include "qemu/error-report.h"
45 #include "qemu/option.h"
46 #include "bootparam.h"
47 #include "xtensa_memory.h"
48 
49 typedef struct XtfpgaFlashDesc {
50     hwaddr base;
51     size_t size;
52     size_t boot_base;
53     size_t sector_size;
54 } XtfpgaFlashDesc;
55 
56 typedef struct XtfpgaBoardDesc {
57     const XtfpgaFlashDesc *flash;
58     size_t sram_size;
59     const hwaddr *io;
60 } XtfpgaBoardDesc;
61 
62 typedef struct XtfpgaFpgaState {
63     MemoryRegion iomem;
64     uint32_t freq;
65     uint32_t leds;
66     uint32_t switches;
67 } XtfpgaFpgaState;
68 
69 static void xtfpga_fpga_reset(void *opaque)
70 {
71     XtfpgaFpgaState *s = opaque;
72 
73     s->leds = 0;
74     s->switches = 0;
75 }
76 
77 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
78         unsigned size)
79 {
80     XtfpgaFpgaState *s = opaque;
81 
82     switch (addr) {
83     case 0x0: /*build date code*/
84         return 0x09272011;
85 
86     case 0x4: /*processor clock frequency, Hz*/
87         return s->freq;
88 
89     case 0x8: /*LEDs (off = 0, on = 1)*/
90         return s->leds;
91 
92     case 0xc: /*DIP switches (off = 0, on = 1)*/
93         return s->switches;
94     }
95     return 0;
96 }
97 
98 static void xtfpga_fpga_write(void *opaque, hwaddr addr,
99         uint64_t val, unsigned size)
100 {
101     XtfpgaFpgaState *s = opaque;
102 
103     switch (addr) {
104     case 0x8: /*LEDs (off = 0, on = 1)*/
105         s->leds = val;
106         break;
107 
108     case 0x10: /*board reset*/
109         if (val == 0xdead) {
110             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
111         }
112         break;
113     }
114 }
115 
116 static const MemoryRegionOps xtfpga_fpga_ops = {
117     .read = xtfpga_fpga_read,
118     .write = xtfpga_fpga_write,
119     .endianness = DEVICE_NATIVE_ENDIAN,
120 };
121 
122 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
123                                          hwaddr base, uint32_t freq)
124 {
125     XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
126 
127     memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
128                           "xtfpga.fpga", 0x10000);
129     memory_region_add_subregion(address_space, base, &s->iomem);
130     s->freq = freq;
131     xtfpga_fpga_reset(s);
132     qemu_register_reset(xtfpga_fpga_reset, s);
133     return s;
134 }
135 
136 static void xtfpga_net_init(MemoryRegion *address_space,
137         hwaddr base,
138         hwaddr descriptors,
139         hwaddr buffers,
140         qemu_irq irq, NICInfo *nd)
141 {
142     DeviceState *dev;
143     SysBusDevice *s;
144     MemoryRegion *ram;
145 
146     dev = qdev_create(NULL, "open_eth");
147     qdev_set_nic_properties(dev, nd);
148     qdev_init_nofail(dev);
149 
150     s = SYS_BUS_DEVICE(dev);
151     sysbus_connect_irq(s, 0, irq);
152     memory_region_add_subregion(address_space, base,
153             sysbus_mmio_get_region(s, 0));
154     memory_region_add_subregion(address_space, descriptors,
155             sysbus_mmio_get_region(s, 1));
156 
157     ram = g_malloc(sizeof(*ram));
158     memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB,
159                            &error_fatal);
160     vmstate_register_ram_global(ram);
161     memory_region_add_subregion(address_space, buffers, ram);
162 }
163 
164 static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
165                                    const XtfpgaBoardDesc *board,
166                                    DriveInfo *dinfo, int be)
167 {
168     SysBusDevice *s;
169     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
170 
171     qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
172                         &error_abort);
173     qdev_prop_set_uint32(dev, "num-blocks",
174                          board->flash->size / board->flash->sector_size);
175     qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
176     qdev_prop_set_uint8(dev, "width", 2);
177     qdev_prop_set_bit(dev, "big-endian", be);
178     qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
179     qdev_init_nofail(dev);
180     s = SYS_BUS_DEVICE(dev);
181     memory_region_add_subregion(address_space, board->flash->base,
182                                 sysbus_mmio_get_region(s, 0));
183     return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
184 }
185 
186 static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
187 {
188     XtensaCPU *cpu = opaque;
189 
190     return cpu_get_phys_page_debug(CPU(cpu), addr);
191 }
192 
193 static void xtfpga_reset(void *opaque)
194 {
195     XtensaCPU *cpu = opaque;
196 
197     cpu_reset(CPU(cpu));
198 }
199 
200 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
201         unsigned size)
202 {
203     return 0;
204 }
205 
206 static void xtfpga_io_write(void *opaque, hwaddr addr,
207         uint64_t val, unsigned size)
208 {
209 }
210 
211 static const MemoryRegionOps xtfpga_io_ops = {
212     .read = xtfpga_io_read,
213     .write = xtfpga_io_write,
214     .endianness = DEVICE_NATIVE_ENDIAN,
215 };
216 
217 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
218 {
219 #ifdef TARGET_WORDS_BIGENDIAN
220     int be = 1;
221 #else
222     int be = 0;
223 #endif
224     MemoryRegion *system_memory = get_system_memory();
225     XtensaCPU *cpu = NULL;
226     CPUXtensaState *env = NULL;
227     MemoryRegion *system_io;
228     qemu_irq *extints;
229     DriveInfo *dinfo;
230     pflash_t *flash = NULL;
231     QemuOpts *machine_opts = qemu_get_machine_opts();
232     const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
233     const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
234     const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
235     const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
236     const unsigned system_io_size = 224 * MiB;
237     uint32_t freq = 10000000;
238     int n;
239 
240     for (n = 0; n < smp_cpus; n++) {
241         CPUXtensaState *cenv = NULL;
242 
243         cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
244         cenv = &cpu->env;
245         if (!env) {
246             env = cenv;
247             freq = env->config->clock_freq_khz * 1000;
248         }
249 
250         cenv->sregs[PRID] = n;
251         qemu_register_reset(xtfpga_reset, cpu);
252         /* Need MMU initialized prior to ELF loading,
253          * so that ELF gets loaded into virtual addresses
254          */
255         cpu_reset(CPU(cpu));
256     }
257     extints = xtensa_get_extints(env);
258 
259     if (env) {
260         XtensaMemory sysram = env->config->sysram;
261 
262         sysram.location[0].size = machine->ram_size;
263         xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
264                                      system_memory);
265         xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
266                                      system_memory);
267         xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
268                                      system_memory);
269         xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
270                                      system_memory);
271         xtensa_create_memory_regions(&sysram, "xtensa.sysram",
272                                      system_memory);
273     }
274 
275     system_io = g_malloc(sizeof(*system_io));
276     memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
277                           system_io_size);
278     memory_region_add_subregion(system_memory, board->io[0], system_io);
279     if (board->io[1]) {
280         MemoryRegion *io = g_malloc(sizeof(*io));
281 
282         memory_region_init_alias(io, NULL, "xtfpga.io.cached",
283                                  system_io, 0, system_io_size);
284         memory_region_add_subregion(system_memory, board->io[1], io);
285     }
286     xtfpga_fpga_init(system_io, 0x0d020000, freq);
287     if (nd_table[0].used) {
288         xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
289                         extints[1], nd_table);
290     }
291 
292     serial_mm_init(system_io, 0x0d050020, 2, extints[0],
293                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
294 
295     dinfo = drive_get(IF_PFLASH, 0, 0);
296     if (dinfo) {
297         flash = xtfpga_flash_init(system_io, board, dinfo, be);
298     }
299 
300     /* Use presence of kernel file name as 'boot from SRAM' switch. */
301     if (kernel_filename) {
302         uint32_t entry_point = env->pc;
303         size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
304         uint32_t tagptr = env->config->sysrom.location[0].addr +
305             board->sram_size;
306         uint32_t cur_tagptr;
307         BpMemInfo memory_location = {
308             .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
309             .start = tswap32(env->config->sysram.location[0].addr),
310             .end = tswap32(env->config->sysram.location[0].addr +
311                            machine->ram_size),
312         };
313         uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
314             machine->ram_size : 0x08000000;
315         uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
316 
317         lowmem_end += env->config->sysram.location[0].addr;
318         cur_lowmem += env->config->sysram.location[0].addr;
319 
320         xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
321                                      system_memory);
322 
323         if (kernel_cmdline) {
324             bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
325         }
326         if (dtb_filename) {
327             bp_size += get_tag_size(sizeof(uint32_t));
328         }
329         if (initrd_filename) {
330             bp_size += get_tag_size(sizeof(BpMemInfo));
331         }
332 
333         /* Put kernel bootparameters to the end of that SRAM */
334         tagptr = (tagptr - bp_size) & ~0xff;
335         cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
336         cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
337                              sizeof(memory_location), &memory_location);
338 
339         if (kernel_cmdline) {
340             cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
341                                  strlen(kernel_cmdline) + 1, kernel_cmdline);
342         }
343 #ifdef CONFIG_FDT
344         if (dtb_filename) {
345             int fdt_size;
346             void *fdt = load_device_tree(dtb_filename, &fdt_size);
347             uint32_t dtb_addr = tswap32(cur_lowmem);
348 
349             if (!fdt) {
350                 error_report("could not load DTB '%s'", dtb_filename);
351                 exit(EXIT_FAILURE);
352             }
353 
354             cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
355             cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
356                                  sizeof(dtb_addr), &dtb_addr);
357             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB);
358         }
359 #else
360         if (dtb_filename) {
361             error_report("could not load DTB '%s': "
362                          "FDT support is not configured in QEMU",
363                          dtb_filename);
364             exit(EXIT_FAILURE);
365         }
366 #endif
367         if (initrd_filename) {
368             BpMemInfo initrd_location = { 0 };
369             int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
370                                            lowmem_end - cur_lowmem);
371 
372             if (initrd_size < 0) {
373                 initrd_size = load_image_targphys(initrd_filename,
374                                                   cur_lowmem,
375                                                   lowmem_end - cur_lowmem);
376             }
377             if (initrd_size < 0) {
378                 error_report("could not load initrd '%s'", initrd_filename);
379                 exit(EXIT_FAILURE);
380             }
381             initrd_location.start = tswap32(cur_lowmem);
382             initrd_location.end = tswap32(cur_lowmem + initrd_size);
383             cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
384                                  sizeof(initrd_location), &initrd_location);
385             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB);
386         }
387         cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
388         env->regs[2] = tagptr;
389 
390         uint64_t elf_entry;
391         uint64_t elf_lowaddr;
392         int success = load_elf(kernel_filename, translate_phys_addr, cpu,
393                 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
394         if (success > 0) {
395             entry_point = elf_entry;
396         } else {
397             hwaddr ep;
398             int is_linux;
399             success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
400                                   translate_phys_addr, cpu);
401             if (success > 0 && is_linux) {
402                 entry_point = ep;
403             } else {
404                 error_report("could not load kernel '%s'",
405                              kernel_filename);
406                 exit(EXIT_FAILURE);
407             }
408         }
409         if (entry_point != env->pc) {
410             uint8_t boot[] = {
411 #ifdef TARGET_WORDS_BIGENDIAN
412                 0x60, 0x00, 0x08,       /* j    1f */
413                 0x00,                   /* .literal_position */
414                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
415                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
416                                         /* 1: */
417                 0x10, 0xff, 0xfe,       /* l32r a0, entry_pc */
418                 0x12, 0xff, 0xfe,       /* l32r a2, entry_a2 */
419                 0x0a, 0x00, 0x00,       /* jx   a0 */
420 #else
421                 0x06, 0x02, 0x00,       /* j    1f */
422                 0x00,                   /* .literal_position */
423                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
424                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
425                                         /* 1: */
426                 0x01, 0xfe, 0xff,       /* l32r a0, entry_pc */
427                 0x21, 0xfe, 0xff,       /* l32r a2, entry_a2 */
428                 0xa0, 0x00, 0x00,       /* jx   a0 */
429 #endif
430             };
431             uint32_t entry_pc = tswap32(entry_point);
432             uint32_t entry_a2 = tswap32(tagptr);
433 
434             memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
435             memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
436             cpu_physical_memory_write(env->pc, boot, sizeof(boot));
437         }
438     } else {
439         if (flash) {
440             MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
441             MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
442             uint32_t size = env->config->sysrom.location[0].size;
443 
444             if (board->flash->size - board->flash->boot_base < size) {
445                 size = board->flash->size - board->flash->boot_base;
446             }
447 
448             memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
449                                      flash_mr, board->flash->boot_base, size);
450             memory_region_add_subregion(system_memory,
451                                         env->config->sysrom.location[0].addr,
452                                         flash_io);
453         } else {
454             xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
455                                          system_memory);
456         }
457     }
458 }
459 
460 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB)
461 
462 static const hwaddr xtfpga_mmu_io[2] = {
463     0xf0000000,
464 };
465 
466 static const hwaddr xtfpga_nommu_io[2] = {
467     0x90000000,
468     0x70000000,
469 };
470 
471 static const XtfpgaFlashDesc lx60_flash = {
472     .base = 0x08000000,
473     .size = 0x00400000,
474     .sector_size = 0x10000,
475 };
476 
477 static void xtfpga_lx60_init(MachineState *machine)
478 {
479     static const XtfpgaBoardDesc lx60_board = {
480         .flash = &lx60_flash,
481         .sram_size = 0x20000,
482         .io = xtfpga_mmu_io,
483     };
484     xtfpga_init(&lx60_board, machine);
485 }
486 
487 static void xtfpga_lx60_nommu_init(MachineState *machine)
488 {
489     static const XtfpgaBoardDesc lx60_board = {
490         .flash = &lx60_flash,
491         .sram_size = 0x20000,
492         .io = xtfpga_nommu_io,
493     };
494     xtfpga_init(&lx60_board, machine);
495 }
496 
497 static const XtfpgaFlashDesc lx200_flash = {
498     .base = 0x08000000,
499     .size = 0x01000000,
500     .sector_size = 0x20000,
501 };
502 
503 static void xtfpga_lx200_init(MachineState *machine)
504 {
505     static const XtfpgaBoardDesc lx200_board = {
506         .flash = &lx200_flash,
507         .sram_size = 0x2000000,
508         .io = xtfpga_mmu_io,
509     };
510     xtfpga_init(&lx200_board, machine);
511 }
512 
513 static void xtfpga_lx200_nommu_init(MachineState *machine)
514 {
515     static const XtfpgaBoardDesc lx200_board = {
516         .flash = &lx200_flash,
517         .sram_size = 0x2000000,
518         .io = xtfpga_nommu_io,
519     };
520     xtfpga_init(&lx200_board, machine);
521 }
522 
523 static const XtfpgaFlashDesc ml605_flash = {
524     .base = 0x08000000,
525     .size = 0x01000000,
526     .sector_size = 0x20000,
527 };
528 
529 static void xtfpga_ml605_init(MachineState *machine)
530 {
531     static const XtfpgaBoardDesc ml605_board = {
532         .flash = &ml605_flash,
533         .sram_size = 0x2000000,
534         .io = xtfpga_mmu_io,
535     };
536     xtfpga_init(&ml605_board, machine);
537 }
538 
539 static void xtfpga_ml605_nommu_init(MachineState *machine)
540 {
541     static const XtfpgaBoardDesc ml605_board = {
542         .flash = &ml605_flash,
543         .sram_size = 0x2000000,
544         .io = xtfpga_nommu_io,
545     };
546     xtfpga_init(&ml605_board, machine);
547 }
548 
549 static const XtfpgaFlashDesc kc705_flash = {
550     .base = 0x00000000,
551     .size = 0x08000000,
552     .boot_base = 0x06000000,
553     .sector_size = 0x20000,
554 };
555 
556 static void xtfpga_kc705_init(MachineState *machine)
557 {
558     static const XtfpgaBoardDesc kc705_board = {
559         .flash = &kc705_flash,
560         .sram_size = 0x2000000,
561         .io = xtfpga_mmu_io,
562     };
563     xtfpga_init(&kc705_board, machine);
564 }
565 
566 static void xtfpga_kc705_nommu_init(MachineState *machine)
567 {
568     static const XtfpgaBoardDesc kc705_board = {
569         .flash = &kc705_flash,
570         .sram_size = 0x2000000,
571         .io = xtfpga_nommu_io,
572     };
573     xtfpga_init(&kc705_board, machine);
574 }
575 
576 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
577 {
578     MachineClass *mc = MACHINE_CLASS(oc);
579 
580     mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
581     mc->init = xtfpga_lx60_init;
582     mc->max_cpus = 4;
583     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
584     mc->default_ram_size = 64 * MiB;
585 }
586 
587 static const TypeInfo xtfpga_lx60_type = {
588     .name = MACHINE_TYPE_NAME("lx60"),
589     .parent = TYPE_MACHINE,
590     .class_init = xtfpga_lx60_class_init,
591 };
592 
593 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
594 {
595     MachineClass *mc = MACHINE_CLASS(oc);
596 
597     mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
598     mc->init = xtfpga_lx60_nommu_init;
599     mc->max_cpus = 4;
600     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
601     mc->default_ram_size = 64 * MiB;
602 }
603 
604 static const TypeInfo xtfpga_lx60_nommu_type = {
605     .name = MACHINE_TYPE_NAME("lx60-nommu"),
606     .parent = TYPE_MACHINE,
607     .class_init = xtfpga_lx60_nommu_class_init,
608 };
609 
610 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
611 {
612     MachineClass *mc = MACHINE_CLASS(oc);
613 
614     mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
615     mc->init = xtfpga_lx200_init;
616     mc->max_cpus = 4;
617     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
618     mc->default_ram_size = 96 * MiB;
619 }
620 
621 static const TypeInfo xtfpga_lx200_type = {
622     .name = MACHINE_TYPE_NAME("lx200"),
623     .parent = TYPE_MACHINE,
624     .class_init = xtfpga_lx200_class_init,
625 };
626 
627 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
628 {
629     MachineClass *mc = MACHINE_CLASS(oc);
630 
631     mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
632     mc->init = xtfpga_lx200_nommu_init;
633     mc->max_cpus = 4;
634     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
635     mc->default_ram_size = 96 * MiB;
636 }
637 
638 static const TypeInfo xtfpga_lx200_nommu_type = {
639     .name = MACHINE_TYPE_NAME("lx200-nommu"),
640     .parent = TYPE_MACHINE,
641     .class_init = xtfpga_lx200_nommu_class_init,
642 };
643 
644 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
645 {
646     MachineClass *mc = MACHINE_CLASS(oc);
647 
648     mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
649     mc->init = xtfpga_ml605_init;
650     mc->max_cpus = 4;
651     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
652     mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
653 }
654 
655 static const TypeInfo xtfpga_ml605_type = {
656     .name = MACHINE_TYPE_NAME("ml605"),
657     .parent = TYPE_MACHINE,
658     .class_init = xtfpga_ml605_class_init,
659 };
660 
661 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
662 {
663     MachineClass *mc = MACHINE_CLASS(oc);
664 
665     mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
666     mc->init = xtfpga_ml605_nommu_init;
667     mc->max_cpus = 4;
668     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
669     mc->default_ram_size = 256 * MiB;
670 }
671 
672 static const TypeInfo xtfpga_ml605_nommu_type = {
673     .name = MACHINE_TYPE_NAME("ml605-nommu"),
674     .parent = TYPE_MACHINE,
675     .class_init = xtfpga_ml605_nommu_class_init,
676 };
677 
678 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
679 {
680     MachineClass *mc = MACHINE_CLASS(oc);
681 
682     mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
683     mc->init = xtfpga_kc705_init;
684     mc->max_cpus = 4;
685     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
686     mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
687 }
688 
689 static const TypeInfo xtfpga_kc705_type = {
690     .name = MACHINE_TYPE_NAME("kc705"),
691     .parent = TYPE_MACHINE,
692     .class_init = xtfpga_kc705_class_init,
693 };
694 
695 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
696 {
697     MachineClass *mc = MACHINE_CLASS(oc);
698 
699     mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
700     mc->init = xtfpga_kc705_nommu_init;
701     mc->max_cpus = 4;
702     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
703     mc->default_ram_size = 256 * MiB;
704 }
705 
706 static const TypeInfo xtfpga_kc705_nommu_type = {
707     .name = MACHINE_TYPE_NAME("kc705-nommu"),
708     .parent = TYPE_MACHINE,
709     .class_init = xtfpga_kc705_nommu_class_init,
710 };
711 
712 static void xtfpga_machines_init(void)
713 {
714     type_register_static(&xtfpga_lx60_type);
715     type_register_static(&xtfpga_lx200_type);
716     type_register_static(&xtfpga_ml605_type);
717     type_register_static(&xtfpga_kc705_type);
718     type_register_static(&xtfpga_lx60_nommu_type);
719     type_register_static(&xtfpga_lx200_nommu_type);
720     type_register_static(&xtfpga_ml605_nommu_type);
721     type_register_static(&xtfpga_kc705_nommu_type);
722 }
723 
724 type_init(xtfpga_machines_init)
725