1 /* 2 * Copyright (c) 2019, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "sysemu/reset.h" 31 #include "hw/boards.h" 32 #include "hw/loader.h" 33 #include "hw/pci-host/gpex.h" 34 #include "net/net.h" 35 #include "elf.h" 36 #include "exec/memory.h" 37 #include "qemu/error-report.h" 38 #include "xtensa_memory.h" 39 #include "xtensa_sim.h" 40 41 static void create_pcie(MachineState *ms, CPUXtensaState *env, int irq_base, 42 hwaddr addr_base) 43 { 44 hwaddr base_ecam = addr_base + 0x00100000; 45 hwaddr size_ecam = 0x03f00000; 46 hwaddr base_pio = addr_base + 0x00000000; 47 hwaddr size_pio = 0x00010000; 48 hwaddr base_mmio = addr_base + 0x04000000; 49 hwaddr size_mmio = 0x08000000; 50 51 MemoryRegion *ecam_alias; 52 MemoryRegion *ecam_reg; 53 MemoryRegion *pio_alias; 54 MemoryRegion *pio_reg; 55 MemoryRegion *mmio_alias; 56 MemoryRegion *mmio_reg; 57 58 MachineClass *mc = MACHINE_GET_CLASS(ms); 59 DeviceState *dev; 60 PCIHostState *pci; 61 qemu_irq *extints; 62 int i; 63 64 dev = qdev_new(TYPE_GPEX_HOST); 65 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 66 67 /* Map only the first size_ecam bytes of ECAM space. */ 68 ecam_alias = g_new0(MemoryRegion, 1); 69 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 70 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 71 ecam_reg, 0, size_ecam); 72 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias); 73 74 /* 75 * Map the MMIO window into system address space so as to expose 76 * the section of PCI MMIO space which starts at the same base address 77 * (ie 1:1 mapping for that part of PCI MMIO space visible through 78 * the window). 79 */ 80 mmio_alias = g_new0(MemoryRegion, 1); 81 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 82 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 83 mmio_reg, base_mmio, size_mmio); 84 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); 85 86 /* Map IO port space. */ 87 pio_alias = g_new0(MemoryRegion, 1); 88 pio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2); 89 memory_region_init_alias(pio_alias, OBJECT(dev), "pcie-pio", 90 pio_reg, 0, size_pio); 91 memory_region_add_subregion(get_system_memory(), base_pio, pio_alias); 92 93 /* Connect IRQ lines. */ 94 extints = xtensa_get_extints(env); 95 96 for (i = 0; i < GPEX_NUM_IRQS; i++) { 97 void *q = extints[irq_base + i]; 98 99 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, q); 100 gpex_set_irq_num(GPEX_HOST(dev), i, irq_base + i); 101 } 102 103 pci = PCI_HOST_BRIDGE(dev); 104 if (pci->bus) { 105 for (i = 0; i < nb_nics; i++) { 106 NICInfo *nd = &nd_table[i]; 107 108 if (!nd->model) { 109 nd->model = g_strdup(mc->default_nic); 110 } 111 112 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL); 113 } 114 } 115 } 116 117 static void xtensa_virt_init(MachineState *machine) 118 { 119 XtensaCPU *cpu = xtensa_sim_common_init(machine); 120 CPUXtensaState *env = &cpu->env; 121 122 create_pcie(machine, env, 0, 0xf0000000); 123 xtensa_sim_load_kernel(cpu, machine); 124 } 125 126 static void xtensa_virt_machine_init(MachineClass *mc) 127 { 128 mc->desc = "virt machine (" XTENSA_DEFAULT_CPU_MODEL ")"; 129 mc->init = xtensa_virt_init; 130 mc->max_cpus = 32; 131 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 132 mc->default_nic = "virtio-net-pci"; 133 } 134 135 DEFINE_MACHINE("virt", xtensa_virt_machine_init) 136