1 /* 2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * Neither the name of the Open Source and Linux Lab nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "cpu.h" 30 #include "hw/hw.h" 31 #include "hw/irq.h" 32 #include "qemu/log.h" 33 #include "qemu/timer.h" 34 35 void check_interrupts(CPUXtensaState *env) 36 { 37 CPUState *cs = env_cpu(env); 38 int minlevel = xtensa_get_cintlevel(env); 39 uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE]; 40 int level; 41 42 for (level = env->config->nlevel; level > minlevel; --level) { 43 if (env->config->level_mask[level] & int_set_enabled) { 44 env->pending_irq_level = level; 45 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 46 qemu_log_mask(CPU_LOG_INT, 47 "%s level = %d, cintlevel = %d, " 48 "pc = %08x, a0 = %08x, ps = %08x, " 49 "intset = %08x, intenable = %08x, " 50 "ccount = %08x\n", 51 __func__, level, xtensa_get_cintlevel(env), 52 env->pc, env->regs[0], env->sregs[PS], 53 env->sregs[INTSET], env->sregs[INTENABLE], 54 env->sregs[CCOUNT]); 55 return; 56 } 57 } 58 env->pending_irq_level = 0; 59 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 60 } 61 62 static void xtensa_set_irq(void *opaque, int irq, int active) 63 { 64 CPUXtensaState *env = opaque; 65 66 if (irq >= env->config->ninterrupt) { 67 qemu_log("%s: bad IRQ %d\n", __func__, irq); 68 } else { 69 uint32_t irq_bit = 1 << irq; 70 71 if (active) { 72 atomic_or(&env->sregs[INTSET], irq_bit); 73 } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) { 74 atomic_and(&env->sregs[INTSET], ~irq_bit); 75 } 76 77 check_interrupts(env); 78 } 79 } 80 81 static void xtensa_ccompare_cb(void *opaque) 82 { 83 XtensaCcompareTimer *ccompare = opaque; 84 CPUXtensaState *env = ccompare->env; 85 unsigned i = ccompare - env->ccompare; 86 87 qemu_set_irq(env->irq_inputs[env->config->timerint[i]], 1); 88 } 89 90 static void xtensa_set_runstall(void *opaque, int irq, int active) 91 { 92 CPUXtensaState *env = opaque; 93 xtensa_runstall(env, active); 94 } 95 96 void xtensa_irq_init(CPUXtensaState *env) 97 { 98 unsigned i; 99 100 env->irq_inputs = qemu_allocate_irqs(xtensa_set_irq, env, 101 env->config->ninterrupt); 102 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) { 103 env->time_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 104 env->ccount_base = env->sregs[CCOUNT]; 105 for (i = 0; i < env->config->nccompare; ++i) { 106 env->ccompare[i].env = env; 107 env->ccompare[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 108 xtensa_ccompare_cb, env->ccompare + i); 109 } 110 } 111 for (i = 0; i < env->config->nextint; ++i) { 112 unsigned irq = env->config->extint[i]; 113 114 env->ext_irq_inputs[i] = env->irq_inputs[irq]; 115 } 116 env->runstall_irq = qemu_allocate_irq(xtensa_set_runstall, env, 0); 117 } 118 119 qemu_irq *xtensa_get_extints(CPUXtensaState *env) 120 { 121 return env->ext_irq_inputs; 122 } 123 124 qemu_irq xtensa_get_runstall(CPUXtensaState *env) 125 { 126 return env->runstall_irq; 127 } 128