1 /* 2 * Copyright (c) 2007, Neocleus Corporation. 3 * Copyright (c) 2007, Intel Corporation. 4 * 5 * This work is licensed under the terms of the GNU GPL, version 2. See 6 * the COPYING file in the top-level directory. 7 * 8 * Alex Novik <alex@neocleus.com> 9 * Allen Kay <allen.m.kay@intel.com> 10 * Guy Zana <guy@neocleus.com> 11 * 12 * This file implements direct PCI assignment to a HVM guest 13 */ 14 15 #include "qemu/timer.h" 16 #include "hw/xen/xen_backend.h" 17 #include "xen_pt.h" 18 19 #define XEN_PT_MERGE_VALUE(value, data, val_mask) \ 20 (((value) & (val_mask)) | ((data) & ~(val_mask))) 21 22 #define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */ 23 24 /* prototype */ 25 26 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg, 27 uint32_t real_offset, uint32_t *data); 28 29 30 /* helper */ 31 32 /* A return value of 1 means the capability should NOT be exposed to guest. */ 33 static int xen_pt_hide_dev_cap(const XenHostPCIDevice *d, uint8_t grp_id) 34 { 35 switch (grp_id) { 36 case PCI_CAP_ID_EXP: 37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE 38 * Controller looks trivial, e.g., the PCI Express Capabilities 39 * Register is 0. We should not try to expose it to guest. 40 * 41 * The datasheet is available at 42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf 43 * 44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the 45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE 46 * Controller looks trivial, e.g., the PCI Express Capabilities 47 * Register is 0, so the Capability Version is 0 and 48 * xen_pt_pcie_size_init() would fail. 49 */ 50 if (d->vendor_id == PCI_VENDOR_ID_INTEL && 51 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) { 52 return 1; 53 } 54 break; 55 } 56 return 0; 57 } 58 59 /* find emulate register group entry */ 60 XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address) 61 { 62 XenPTRegGroup *entry = NULL; 63 64 /* find register group entry */ 65 QLIST_FOREACH(entry, &s->reg_grps, entries) { 66 /* check address */ 67 if ((entry->base_offset <= address) 68 && ((entry->base_offset + entry->size) > address)) { 69 return entry; 70 } 71 } 72 73 /* group entry not found */ 74 return NULL; 75 } 76 77 /* find emulate register entry */ 78 XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address) 79 { 80 XenPTReg *reg_entry = NULL; 81 XenPTRegInfo *reg = NULL; 82 uint32_t real_offset = 0; 83 84 /* find register entry */ 85 QLIST_FOREACH(reg_entry, ®_grp->reg_tbl_list, entries) { 86 reg = reg_entry->reg; 87 real_offset = reg_grp->base_offset + reg->offset; 88 /* check address */ 89 if ((real_offset <= address) 90 && ((real_offset + reg->size) > address)) { 91 return reg_entry; 92 } 93 } 94 95 return NULL; 96 } 97 98 static uint32_t get_throughable_mask(const XenPCIPassthroughState *s, 99 XenPTRegInfo *reg, uint32_t valid_mask) 100 { 101 uint32_t throughable_mask = ~(reg->emu_mask | reg->ro_mask); 102 103 if (!s->permissive) { 104 throughable_mask &= ~reg->res_mask; 105 } 106 107 return throughable_mask & valid_mask; 108 } 109 110 /**************** 111 * general register functions 112 */ 113 114 /* register initialization function */ 115 116 static int xen_pt_common_reg_init(XenPCIPassthroughState *s, 117 XenPTRegInfo *reg, uint32_t real_offset, 118 uint32_t *data) 119 { 120 *data = reg->init_val; 121 return 0; 122 } 123 124 /* Read register functions */ 125 126 static int xen_pt_byte_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry, 127 uint8_t *value, uint8_t valid_mask) 128 { 129 XenPTRegInfo *reg = cfg_entry->reg; 130 uint8_t valid_emu_mask = 0; 131 132 /* emulate byte register */ 133 valid_emu_mask = reg->emu_mask & valid_mask; 134 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); 135 136 return 0; 137 } 138 static int xen_pt_word_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry, 139 uint16_t *value, uint16_t valid_mask) 140 { 141 XenPTRegInfo *reg = cfg_entry->reg; 142 uint16_t valid_emu_mask = 0; 143 144 /* emulate word register */ 145 valid_emu_mask = reg->emu_mask & valid_mask; 146 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); 147 148 return 0; 149 } 150 static int xen_pt_long_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry, 151 uint32_t *value, uint32_t valid_mask) 152 { 153 XenPTRegInfo *reg = cfg_entry->reg; 154 uint32_t valid_emu_mask = 0; 155 156 /* emulate long register */ 157 valid_emu_mask = reg->emu_mask & valid_mask; 158 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); 159 160 return 0; 161 } 162 163 /* Write register functions */ 164 165 static int xen_pt_byte_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry, 166 uint8_t *val, uint8_t dev_value, 167 uint8_t valid_mask) 168 { 169 XenPTRegInfo *reg = cfg_entry->reg; 170 uint8_t writable_mask = 0; 171 uint8_t throughable_mask = get_throughable_mask(s, reg, valid_mask); 172 173 /* modify emulate register */ 174 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; 175 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 176 177 /* create value for writing to I/O device register */ 178 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); 179 180 return 0; 181 } 182 static int xen_pt_word_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry, 183 uint16_t *val, uint16_t dev_value, 184 uint16_t valid_mask) 185 { 186 XenPTRegInfo *reg = cfg_entry->reg; 187 uint16_t writable_mask = 0; 188 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask); 189 190 /* modify emulate register */ 191 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; 192 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 193 194 /* create value for writing to I/O device register */ 195 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); 196 197 return 0; 198 } 199 static int xen_pt_long_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry, 200 uint32_t *val, uint32_t dev_value, 201 uint32_t valid_mask) 202 { 203 XenPTRegInfo *reg = cfg_entry->reg; 204 uint32_t writable_mask = 0; 205 uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask); 206 207 /* modify emulate register */ 208 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; 209 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 210 211 /* create value for writing to I/O device register */ 212 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); 213 214 return 0; 215 } 216 217 218 /* XenPTRegInfo declaration 219 * - only for emulated register (either a part or whole bit). 220 * - for passthrough register that need special behavior (like interacting with 221 * other component), set emu_mask to all 0 and specify r/w func properly. 222 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered. 223 */ 224 225 /******************** 226 * Header Type0 227 */ 228 229 static int xen_pt_vendor_reg_init(XenPCIPassthroughState *s, 230 XenPTRegInfo *reg, uint32_t real_offset, 231 uint32_t *data) 232 { 233 *data = s->real_device.vendor_id; 234 return 0; 235 } 236 static int xen_pt_device_reg_init(XenPCIPassthroughState *s, 237 XenPTRegInfo *reg, uint32_t real_offset, 238 uint32_t *data) 239 { 240 *data = s->real_device.device_id; 241 return 0; 242 } 243 static int xen_pt_status_reg_init(XenPCIPassthroughState *s, 244 XenPTRegInfo *reg, uint32_t real_offset, 245 uint32_t *data) 246 { 247 XenPTRegGroup *reg_grp_entry = NULL; 248 XenPTReg *reg_entry = NULL; 249 uint32_t reg_field = 0; 250 251 /* find Header register group */ 252 reg_grp_entry = xen_pt_find_reg_grp(s, PCI_CAPABILITY_LIST); 253 if (reg_grp_entry) { 254 /* find Capabilities Pointer register */ 255 reg_entry = xen_pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST); 256 if (reg_entry) { 257 /* check Capabilities Pointer register */ 258 if (reg_entry->data) { 259 reg_field |= PCI_STATUS_CAP_LIST; 260 } else { 261 reg_field &= ~PCI_STATUS_CAP_LIST; 262 } 263 } else { 264 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*" 265 " for Capabilities Pointer register." 266 " (%s)\n", __func__); 267 return -1; 268 } 269 } else { 270 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup" 271 " for Header. (%s)\n", __func__); 272 return -1; 273 } 274 275 *data = reg_field; 276 return 0; 277 } 278 static int xen_pt_header_type_reg_init(XenPCIPassthroughState *s, 279 XenPTRegInfo *reg, uint32_t real_offset, 280 uint32_t *data) 281 { 282 /* read PCI_HEADER_TYPE */ 283 *data = reg->init_val | 0x80; 284 return 0; 285 } 286 287 /* initialize Interrupt Pin register */ 288 static int xen_pt_irqpin_reg_init(XenPCIPassthroughState *s, 289 XenPTRegInfo *reg, uint32_t real_offset, 290 uint32_t *data) 291 { 292 *data = xen_pt_pci_read_intx(s); 293 return 0; 294 } 295 296 /* Command register */ 297 static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry, 298 uint16_t *val, uint16_t dev_value, 299 uint16_t valid_mask) 300 { 301 XenPTRegInfo *reg = cfg_entry->reg; 302 uint16_t writable_mask = 0; 303 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask); 304 305 /* modify emulate register */ 306 writable_mask = ~reg->ro_mask & valid_mask; 307 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 308 309 /* create value for writing to I/O device register */ 310 if (*val & PCI_COMMAND_INTX_DISABLE) { 311 throughable_mask |= PCI_COMMAND_INTX_DISABLE; 312 } else { 313 if (s->machine_irq) { 314 throughable_mask |= PCI_COMMAND_INTX_DISABLE; 315 } 316 } 317 318 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); 319 320 return 0; 321 } 322 323 /* BAR */ 324 #define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */ 325 #define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */ 326 #define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */ 327 #define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */ 328 329 static bool is_64bit_bar(PCIIORegion *r) 330 { 331 return !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 332 } 333 334 static uint64_t xen_pt_get_bar_size(PCIIORegion *r) 335 { 336 if (is_64bit_bar(r)) { 337 uint64_t size64; 338 size64 = (r + 1)->size; 339 size64 <<= 32; 340 size64 += r->size; 341 return size64; 342 } 343 return r->size; 344 } 345 346 static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s, 347 int index) 348 { 349 PCIDevice *d = &s->dev; 350 XenPTRegion *region = NULL; 351 PCIIORegion *r; 352 353 /* check 64bit BAR */ 354 if ((0 < index) && (index < PCI_ROM_SLOT)) { 355 int type = s->real_device.io_regions[index - 1].type; 356 357 if ((type & XEN_HOST_PCI_REGION_TYPE_MEM) 358 && (type & XEN_HOST_PCI_REGION_TYPE_MEM_64)) { 359 region = &s->bases[index - 1]; 360 if (region->bar_flag != XEN_PT_BAR_FLAG_UPPER) { 361 return XEN_PT_BAR_FLAG_UPPER; 362 } 363 } 364 } 365 366 /* check unused BAR */ 367 r = &d->io_regions[index]; 368 if (!xen_pt_get_bar_size(r)) { 369 return XEN_PT_BAR_FLAG_UNUSED; 370 } 371 372 /* for ExpROM BAR */ 373 if (index == PCI_ROM_SLOT) { 374 return XEN_PT_BAR_FLAG_MEM; 375 } 376 377 /* check BAR I/O indicator */ 378 if (s->real_device.io_regions[index].type & XEN_HOST_PCI_REGION_TYPE_IO) { 379 return XEN_PT_BAR_FLAG_IO; 380 } else { 381 return XEN_PT_BAR_FLAG_MEM; 382 } 383 } 384 385 static inline uint32_t base_address_with_flags(XenHostPCIIORegion *hr) 386 { 387 if (hr->type & XEN_HOST_PCI_REGION_TYPE_IO) { 388 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_IO_MASK); 389 } else { 390 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_MEM_MASK); 391 } 392 } 393 394 static int xen_pt_bar_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg, 395 uint32_t real_offset, uint32_t *data) 396 { 397 uint32_t reg_field = 0; 398 int index; 399 400 index = xen_pt_bar_offset_to_index(reg->offset); 401 if (index < 0 || index >= PCI_NUM_REGIONS) { 402 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index); 403 return -1; 404 } 405 406 /* set BAR flag */ 407 s->bases[index].bar_flag = xen_pt_bar_reg_parse(s, index); 408 if (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED) { 409 reg_field = XEN_PT_INVALID_REG; 410 } 411 412 *data = reg_field; 413 return 0; 414 } 415 static int xen_pt_bar_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry, 416 uint32_t *value, uint32_t valid_mask) 417 { 418 XenPTRegInfo *reg = cfg_entry->reg; 419 uint32_t valid_emu_mask = 0; 420 uint32_t bar_emu_mask = 0; 421 int index; 422 423 /* get BAR index */ 424 index = xen_pt_bar_offset_to_index(reg->offset); 425 if (index < 0 || index >= PCI_NUM_REGIONS - 1) { 426 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index); 427 return -1; 428 } 429 430 /* use fixed-up value from kernel sysfs */ 431 *value = base_address_with_flags(&s->real_device.io_regions[index]); 432 433 /* set emulate mask depend on BAR flag */ 434 switch (s->bases[index].bar_flag) { 435 case XEN_PT_BAR_FLAG_MEM: 436 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK; 437 break; 438 case XEN_PT_BAR_FLAG_IO: 439 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK; 440 break; 441 case XEN_PT_BAR_FLAG_UPPER: 442 bar_emu_mask = XEN_PT_BAR_ALLF; 443 break; 444 default: 445 break; 446 } 447 448 /* emulate BAR */ 449 valid_emu_mask = bar_emu_mask & valid_mask; 450 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); 451 452 return 0; 453 } 454 static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry, 455 uint32_t *val, uint32_t dev_value, 456 uint32_t valid_mask) 457 { 458 XenPTRegInfo *reg = cfg_entry->reg; 459 XenPTRegion *base = NULL; 460 PCIDevice *d = &s->dev; 461 const PCIIORegion *r; 462 uint32_t writable_mask = 0; 463 uint32_t bar_emu_mask = 0; 464 uint32_t bar_ro_mask = 0; 465 uint32_t r_size = 0; 466 int index = 0; 467 468 index = xen_pt_bar_offset_to_index(reg->offset); 469 if (index < 0 || index >= PCI_NUM_REGIONS) { 470 XEN_PT_ERR(d, "Internal error: Invalid BAR index [%d].\n", index); 471 return -1; 472 } 473 474 r = &d->io_regions[index]; 475 base = &s->bases[index]; 476 r_size = xen_pt_get_emul_size(base->bar_flag, r->size); 477 478 /* set emulate mask and read-only mask values depend on the BAR flag */ 479 switch (s->bases[index].bar_flag) { 480 case XEN_PT_BAR_FLAG_MEM: 481 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK; 482 if (!r_size) { 483 /* low 32 bits mask for 64 bit bars */ 484 bar_ro_mask = XEN_PT_BAR_ALLF; 485 } else { 486 bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1); 487 } 488 break; 489 case XEN_PT_BAR_FLAG_IO: 490 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK; 491 bar_ro_mask = XEN_PT_BAR_IO_RO_MASK | (r_size - 1); 492 break; 493 case XEN_PT_BAR_FLAG_UPPER: 494 bar_emu_mask = XEN_PT_BAR_ALLF; 495 bar_ro_mask = r_size ? r_size - 1 : 0; 496 break; 497 default: 498 break; 499 } 500 501 /* modify emulate register */ 502 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask; 503 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 504 505 /* check whether we need to update the virtual region address or not */ 506 switch (s->bases[index].bar_flag) { 507 case XEN_PT_BAR_FLAG_UPPER: 508 case XEN_PT_BAR_FLAG_MEM: 509 /* nothing to do */ 510 break; 511 case XEN_PT_BAR_FLAG_IO: 512 /* nothing to do */ 513 break; 514 default: 515 break; 516 } 517 518 /* create value for writing to I/O device register */ 519 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0); 520 521 return 0; 522 } 523 524 /* write Exp ROM BAR */ 525 static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s, 526 XenPTReg *cfg_entry, uint32_t *val, 527 uint32_t dev_value, uint32_t valid_mask) 528 { 529 XenPTRegInfo *reg = cfg_entry->reg; 530 XenPTRegion *base = NULL; 531 PCIDevice *d = (PCIDevice *)&s->dev; 532 uint32_t writable_mask = 0; 533 uint32_t throughable_mask = get_throughable_mask(s, reg, valid_mask); 534 pcibus_t r_size = 0; 535 uint32_t bar_ro_mask = 0; 536 537 r_size = d->io_regions[PCI_ROM_SLOT].size; 538 base = &s->bases[PCI_ROM_SLOT]; 539 /* align memory type resource size */ 540 r_size = xen_pt_get_emul_size(base->bar_flag, r_size); 541 542 /* set emulate mask and read-only mask */ 543 bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE; 544 545 /* modify emulate register */ 546 writable_mask = ~bar_ro_mask & valid_mask; 547 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 548 549 /* create value for writing to I/O device register */ 550 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); 551 552 return 0; 553 } 554 555 /* Header Type0 reg static information table */ 556 static XenPTRegInfo xen_pt_emu_reg_header0[] = { 557 /* Vendor ID reg */ 558 { 559 .offset = PCI_VENDOR_ID, 560 .size = 2, 561 .init_val = 0x0000, 562 .ro_mask = 0xFFFF, 563 .emu_mask = 0xFFFF, 564 .init = xen_pt_vendor_reg_init, 565 .u.w.read = xen_pt_word_reg_read, 566 .u.w.write = xen_pt_word_reg_write, 567 }, 568 /* Device ID reg */ 569 { 570 .offset = PCI_DEVICE_ID, 571 .size = 2, 572 .init_val = 0x0000, 573 .ro_mask = 0xFFFF, 574 .emu_mask = 0xFFFF, 575 .init = xen_pt_device_reg_init, 576 .u.w.read = xen_pt_word_reg_read, 577 .u.w.write = xen_pt_word_reg_write, 578 }, 579 /* Command reg */ 580 { 581 .offset = PCI_COMMAND, 582 .size = 2, 583 .init_val = 0x0000, 584 .res_mask = 0xF880, 585 .emu_mask = 0x0743, 586 .init = xen_pt_common_reg_init, 587 .u.w.read = xen_pt_word_reg_read, 588 .u.w.write = xen_pt_cmd_reg_write, 589 }, 590 /* Capabilities Pointer reg */ 591 { 592 .offset = PCI_CAPABILITY_LIST, 593 .size = 1, 594 .init_val = 0x00, 595 .ro_mask = 0xFF, 596 .emu_mask = 0xFF, 597 .init = xen_pt_ptr_reg_init, 598 .u.b.read = xen_pt_byte_reg_read, 599 .u.b.write = xen_pt_byte_reg_write, 600 }, 601 /* Status reg */ 602 /* use emulated Cap Ptr value to initialize, 603 * so need to be declared after Cap Ptr reg 604 */ 605 { 606 .offset = PCI_STATUS, 607 .size = 2, 608 .init_val = 0x0000, 609 .res_mask = 0x0007, 610 .ro_mask = 0x06F8, 611 .emu_mask = 0x0010, 612 .init = xen_pt_status_reg_init, 613 .u.w.read = xen_pt_word_reg_read, 614 .u.w.write = xen_pt_word_reg_write, 615 }, 616 /* Cache Line Size reg */ 617 { 618 .offset = PCI_CACHE_LINE_SIZE, 619 .size = 1, 620 .init_val = 0x00, 621 .ro_mask = 0x00, 622 .emu_mask = 0xFF, 623 .init = xen_pt_common_reg_init, 624 .u.b.read = xen_pt_byte_reg_read, 625 .u.b.write = xen_pt_byte_reg_write, 626 }, 627 /* Latency Timer reg */ 628 { 629 .offset = PCI_LATENCY_TIMER, 630 .size = 1, 631 .init_val = 0x00, 632 .ro_mask = 0x00, 633 .emu_mask = 0xFF, 634 .init = xen_pt_common_reg_init, 635 .u.b.read = xen_pt_byte_reg_read, 636 .u.b.write = xen_pt_byte_reg_write, 637 }, 638 /* Header Type reg */ 639 { 640 .offset = PCI_HEADER_TYPE, 641 .size = 1, 642 .init_val = 0x00, 643 .ro_mask = 0xFF, 644 .emu_mask = 0x00, 645 .init = xen_pt_header_type_reg_init, 646 .u.b.read = xen_pt_byte_reg_read, 647 .u.b.write = xen_pt_byte_reg_write, 648 }, 649 /* Interrupt Line reg */ 650 { 651 .offset = PCI_INTERRUPT_LINE, 652 .size = 1, 653 .init_val = 0x00, 654 .ro_mask = 0x00, 655 .emu_mask = 0xFF, 656 .init = xen_pt_common_reg_init, 657 .u.b.read = xen_pt_byte_reg_read, 658 .u.b.write = xen_pt_byte_reg_write, 659 }, 660 /* Interrupt Pin reg */ 661 { 662 .offset = PCI_INTERRUPT_PIN, 663 .size = 1, 664 .init_val = 0x00, 665 .ro_mask = 0xFF, 666 .emu_mask = 0xFF, 667 .init = xen_pt_irqpin_reg_init, 668 .u.b.read = xen_pt_byte_reg_read, 669 .u.b.write = xen_pt_byte_reg_write, 670 }, 671 /* BAR 0 reg */ 672 /* mask of BAR need to be decided later, depends on IO/MEM type */ 673 { 674 .offset = PCI_BASE_ADDRESS_0, 675 .size = 4, 676 .init_val = 0x00000000, 677 .init = xen_pt_bar_reg_init, 678 .u.dw.read = xen_pt_bar_reg_read, 679 .u.dw.write = xen_pt_bar_reg_write, 680 }, 681 /* BAR 1 reg */ 682 { 683 .offset = PCI_BASE_ADDRESS_1, 684 .size = 4, 685 .init_val = 0x00000000, 686 .init = xen_pt_bar_reg_init, 687 .u.dw.read = xen_pt_bar_reg_read, 688 .u.dw.write = xen_pt_bar_reg_write, 689 }, 690 /* BAR 2 reg */ 691 { 692 .offset = PCI_BASE_ADDRESS_2, 693 .size = 4, 694 .init_val = 0x00000000, 695 .init = xen_pt_bar_reg_init, 696 .u.dw.read = xen_pt_bar_reg_read, 697 .u.dw.write = xen_pt_bar_reg_write, 698 }, 699 /* BAR 3 reg */ 700 { 701 .offset = PCI_BASE_ADDRESS_3, 702 .size = 4, 703 .init_val = 0x00000000, 704 .init = xen_pt_bar_reg_init, 705 .u.dw.read = xen_pt_bar_reg_read, 706 .u.dw.write = xen_pt_bar_reg_write, 707 }, 708 /* BAR 4 reg */ 709 { 710 .offset = PCI_BASE_ADDRESS_4, 711 .size = 4, 712 .init_val = 0x00000000, 713 .init = xen_pt_bar_reg_init, 714 .u.dw.read = xen_pt_bar_reg_read, 715 .u.dw.write = xen_pt_bar_reg_write, 716 }, 717 /* BAR 5 reg */ 718 { 719 .offset = PCI_BASE_ADDRESS_5, 720 .size = 4, 721 .init_val = 0x00000000, 722 .init = xen_pt_bar_reg_init, 723 .u.dw.read = xen_pt_bar_reg_read, 724 .u.dw.write = xen_pt_bar_reg_write, 725 }, 726 /* Expansion ROM BAR reg */ 727 { 728 .offset = PCI_ROM_ADDRESS, 729 .size = 4, 730 .init_val = 0x00000000, 731 .ro_mask = ~PCI_ROM_ADDRESS_MASK & ~PCI_ROM_ADDRESS_ENABLE, 732 .emu_mask = (uint32_t)PCI_ROM_ADDRESS_MASK, 733 .init = xen_pt_bar_reg_init, 734 .u.dw.read = xen_pt_long_reg_read, 735 .u.dw.write = xen_pt_exp_rom_bar_reg_write, 736 }, 737 { 738 .size = 0, 739 }, 740 }; 741 742 743 /********************************* 744 * Vital Product Data Capability 745 */ 746 747 /* Vital Product Data Capability Structure reg static information table */ 748 static XenPTRegInfo xen_pt_emu_reg_vpd[] = { 749 { 750 .offset = PCI_CAP_LIST_NEXT, 751 .size = 1, 752 .init_val = 0x00, 753 .ro_mask = 0xFF, 754 .emu_mask = 0xFF, 755 .init = xen_pt_ptr_reg_init, 756 .u.b.read = xen_pt_byte_reg_read, 757 .u.b.write = xen_pt_byte_reg_write, 758 }, 759 { 760 .offset = PCI_VPD_ADDR, 761 .size = 2, 762 .ro_mask = 0x0003, 763 .emu_mask = 0x0003, 764 .init = xen_pt_common_reg_init, 765 .u.w.read = xen_pt_word_reg_read, 766 .u.w.write = xen_pt_word_reg_write, 767 }, 768 { 769 .size = 0, 770 }, 771 }; 772 773 774 /************************************** 775 * Vendor Specific Capability 776 */ 777 778 /* Vendor Specific Capability Structure reg static information table */ 779 static XenPTRegInfo xen_pt_emu_reg_vendor[] = { 780 { 781 .offset = PCI_CAP_LIST_NEXT, 782 .size = 1, 783 .init_val = 0x00, 784 .ro_mask = 0xFF, 785 .emu_mask = 0xFF, 786 .init = xen_pt_ptr_reg_init, 787 .u.b.read = xen_pt_byte_reg_read, 788 .u.b.write = xen_pt_byte_reg_write, 789 }, 790 { 791 .size = 0, 792 }, 793 }; 794 795 796 /***************************** 797 * PCI Express Capability 798 */ 799 800 static inline uint8_t get_capability_version(XenPCIPassthroughState *s, 801 uint32_t offset) 802 { 803 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS); 804 return flags & PCI_EXP_FLAGS_VERS; 805 } 806 807 static inline uint8_t get_device_type(XenPCIPassthroughState *s, 808 uint32_t offset) 809 { 810 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS); 811 return (flags & PCI_EXP_FLAGS_TYPE) >> 4; 812 } 813 814 /* initialize Link Control register */ 815 static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState *s, 816 XenPTRegInfo *reg, uint32_t real_offset, 817 uint32_t *data) 818 { 819 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset); 820 uint8_t dev_type = get_device_type(s, real_offset - reg->offset); 821 822 /* no need to initialize in case of Root Complex Integrated Endpoint 823 * with cap_ver 1.x 824 */ 825 if ((dev_type == PCI_EXP_TYPE_RC_END) && (cap_ver == 1)) { 826 *data = XEN_PT_INVALID_REG; 827 } 828 829 *data = reg->init_val; 830 return 0; 831 } 832 /* initialize Device Control 2 register */ 833 static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState *s, 834 XenPTRegInfo *reg, uint32_t real_offset, 835 uint32_t *data) 836 { 837 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset); 838 839 /* no need to initialize in case of cap_ver 1.x */ 840 if (cap_ver == 1) { 841 *data = XEN_PT_INVALID_REG; 842 } 843 844 *data = reg->init_val; 845 return 0; 846 } 847 /* initialize Link Control 2 register */ 848 static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState *s, 849 XenPTRegInfo *reg, uint32_t real_offset, 850 uint32_t *data) 851 { 852 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset); 853 uint32_t reg_field = 0; 854 855 /* no need to initialize in case of cap_ver 1.x */ 856 if (cap_ver == 1) { 857 reg_field = XEN_PT_INVALID_REG; 858 } else { 859 /* set Supported Link Speed */ 860 uint8_t lnkcap = pci_get_byte(s->dev.config + real_offset - reg->offset 861 + PCI_EXP_LNKCAP); 862 reg_field |= PCI_EXP_LNKCAP_SLS & lnkcap; 863 } 864 865 *data = reg_field; 866 return 0; 867 } 868 869 /* PCI Express Capability Structure reg static information table */ 870 static XenPTRegInfo xen_pt_emu_reg_pcie[] = { 871 /* Next Pointer reg */ 872 { 873 .offset = PCI_CAP_LIST_NEXT, 874 .size = 1, 875 .init_val = 0x00, 876 .ro_mask = 0xFF, 877 .emu_mask = 0xFF, 878 .init = xen_pt_ptr_reg_init, 879 .u.b.read = xen_pt_byte_reg_read, 880 .u.b.write = xen_pt_byte_reg_write, 881 }, 882 /* Device Capabilities reg */ 883 { 884 .offset = PCI_EXP_DEVCAP, 885 .size = 4, 886 .init_val = 0x00000000, 887 .ro_mask = 0xFFFFFFFF, 888 .emu_mask = 0x10000000, 889 .init = xen_pt_common_reg_init, 890 .u.dw.read = xen_pt_long_reg_read, 891 .u.dw.write = xen_pt_long_reg_write, 892 }, 893 /* Device Control reg */ 894 { 895 .offset = PCI_EXP_DEVCTL, 896 .size = 2, 897 .init_val = 0x2810, 898 .ro_mask = 0x8400, 899 .emu_mask = 0xFFFF, 900 .init = xen_pt_common_reg_init, 901 .u.w.read = xen_pt_word_reg_read, 902 .u.w.write = xen_pt_word_reg_write, 903 }, 904 /* Device Status reg */ 905 { 906 .offset = PCI_EXP_DEVSTA, 907 .size = 2, 908 .res_mask = 0xFFC0, 909 .ro_mask = 0x0030, 910 .init = xen_pt_common_reg_init, 911 .u.w.read = xen_pt_word_reg_read, 912 .u.w.write = xen_pt_word_reg_write, 913 }, 914 /* Link Control reg */ 915 { 916 .offset = PCI_EXP_LNKCTL, 917 .size = 2, 918 .init_val = 0x0000, 919 .ro_mask = 0xFC34, 920 .emu_mask = 0xFFFF, 921 .init = xen_pt_linkctrl_reg_init, 922 .u.w.read = xen_pt_word_reg_read, 923 .u.w.write = xen_pt_word_reg_write, 924 }, 925 /* Link Status reg */ 926 { 927 .offset = PCI_EXP_LNKSTA, 928 .size = 2, 929 .ro_mask = 0x3FFF, 930 .init = xen_pt_common_reg_init, 931 .u.w.read = xen_pt_word_reg_read, 932 .u.w.write = xen_pt_word_reg_write, 933 }, 934 /* Device Control 2 reg */ 935 { 936 .offset = 0x28, 937 .size = 2, 938 .init_val = 0x0000, 939 .ro_mask = 0xFFE0, 940 .emu_mask = 0xFFFF, 941 .init = xen_pt_devctrl2_reg_init, 942 .u.w.read = xen_pt_word_reg_read, 943 .u.w.write = xen_pt_word_reg_write, 944 }, 945 /* Link Control 2 reg */ 946 { 947 .offset = 0x30, 948 .size = 2, 949 .init_val = 0x0000, 950 .ro_mask = 0xE040, 951 .emu_mask = 0xFFFF, 952 .init = xen_pt_linkctrl2_reg_init, 953 .u.w.read = xen_pt_word_reg_read, 954 .u.w.write = xen_pt_word_reg_write, 955 }, 956 { 957 .size = 0, 958 }, 959 }; 960 961 962 /********************************* 963 * Power Management Capability 964 */ 965 966 /* write Power Management Control/Status register */ 967 static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s, 968 XenPTReg *cfg_entry, uint16_t *val, 969 uint16_t dev_value, uint16_t valid_mask) 970 { 971 XenPTRegInfo *reg = cfg_entry->reg; 972 uint16_t writable_mask = 0; 973 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask); 974 975 /* modify emulate register */ 976 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; 977 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 978 979 /* create value for writing to I/O device register */ 980 *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~PCI_PM_CTRL_PME_STATUS, 981 throughable_mask); 982 983 return 0; 984 } 985 986 /* Power Management Capability reg static information table */ 987 static XenPTRegInfo xen_pt_emu_reg_pm[] = { 988 /* Next Pointer reg */ 989 { 990 .offset = PCI_CAP_LIST_NEXT, 991 .size = 1, 992 .init_val = 0x00, 993 .ro_mask = 0xFF, 994 .emu_mask = 0xFF, 995 .init = xen_pt_ptr_reg_init, 996 .u.b.read = xen_pt_byte_reg_read, 997 .u.b.write = xen_pt_byte_reg_write, 998 }, 999 /* Power Management Capabilities reg */ 1000 { 1001 .offset = PCI_CAP_FLAGS, 1002 .size = 2, 1003 .init_val = 0x0000, 1004 .ro_mask = 0xFFFF, 1005 .emu_mask = 0xF9C8, 1006 .init = xen_pt_common_reg_init, 1007 .u.w.read = xen_pt_word_reg_read, 1008 .u.w.write = xen_pt_word_reg_write, 1009 }, 1010 /* PCI Power Management Control/Status reg */ 1011 { 1012 .offset = PCI_PM_CTRL, 1013 .size = 2, 1014 .init_val = 0x0008, 1015 .res_mask = 0x00F0, 1016 .ro_mask = 0xE10C, 1017 .emu_mask = 0x810B, 1018 .init = xen_pt_common_reg_init, 1019 .u.w.read = xen_pt_word_reg_read, 1020 .u.w.write = xen_pt_pmcsr_reg_write, 1021 }, 1022 { 1023 .size = 0, 1024 }, 1025 }; 1026 1027 1028 /******************************** 1029 * MSI Capability 1030 */ 1031 1032 /* Helper */ 1033 #define xen_pt_msi_check_type(offset, flags, what) \ 1034 ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \ 1035 PCI_MSI_##what##_64 : PCI_MSI_##what##_32)) 1036 1037 /* Message Control register */ 1038 static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState *s, 1039 XenPTRegInfo *reg, uint32_t real_offset, 1040 uint32_t *data) 1041 { 1042 PCIDevice *d = &s->dev; 1043 XenPTMSI *msi = s->msi; 1044 uint16_t reg_field = 0; 1045 1046 /* use I/O device register's value as initial value */ 1047 reg_field = pci_get_word(d->config + real_offset); 1048 1049 if (reg_field & PCI_MSI_FLAGS_ENABLE) { 1050 XEN_PT_LOG(&s->dev, "MSI already enabled, disabling it first\n"); 1051 xen_host_pci_set_word(&s->real_device, real_offset, 1052 reg_field & ~PCI_MSI_FLAGS_ENABLE); 1053 } 1054 msi->flags |= reg_field; 1055 msi->ctrl_offset = real_offset; 1056 msi->initialized = false; 1057 msi->mapped = false; 1058 1059 *data = reg->init_val; 1060 return 0; 1061 } 1062 static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s, 1063 XenPTReg *cfg_entry, uint16_t *val, 1064 uint16_t dev_value, uint16_t valid_mask) 1065 { 1066 XenPTRegInfo *reg = cfg_entry->reg; 1067 XenPTMSI *msi = s->msi; 1068 uint16_t writable_mask = 0; 1069 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask); 1070 1071 /* Currently no support for multi-vector */ 1072 if (*val & PCI_MSI_FLAGS_QSIZE) { 1073 XEN_PT_WARN(&s->dev, "Tries to set more than 1 vector ctrl %x\n", *val); 1074 } 1075 1076 /* modify emulate register */ 1077 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; 1078 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 1079 msi->flags |= cfg_entry->data & ~PCI_MSI_FLAGS_ENABLE; 1080 1081 /* create value for writing to I/O device register */ 1082 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); 1083 1084 /* update MSI */ 1085 if (*val & PCI_MSI_FLAGS_ENABLE) { 1086 /* setup MSI pirq for the first time */ 1087 if (!msi->initialized) { 1088 /* Init physical one */ 1089 XEN_PT_LOG(&s->dev, "setup MSI\n"); 1090 if (xen_pt_msi_setup(s)) { 1091 /* We do not broadcast the error to the framework code, so 1092 * that MSI errors are contained in MSI emulation code and 1093 * QEMU can go on running. 1094 * Guest MSI would be actually not working. 1095 */ 1096 *val &= ~PCI_MSI_FLAGS_ENABLE; 1097 XEN_PT_WARN(&s->dev, "Can not map MSI.\n"); 1098 return 0; 1099 } 1100 if (xen_pt_msi_update(s)) { 1101 *val &= ~PCI_MSI_FLAGS_ENABLE; 1102 XEN_PT_WARN(&s->dev, "Can not bind MSI\n"); 1103 return 0; 1104 } 1105 msi->initialized = true; 1106 msi->mapped = true; 1107 } 1108 msi->flags |= PCI_MSI_FLAGS_ENABLE; 1109 } else if (msi->mapped) { 1110 xen_pt_msi_disable(s); 1111 } 1112 1113 return 0; 1114 } 1115 1116 /* initialize Message Upper Address register */ 1117 static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState *s, 1118 XenPTRegInfo *reg, uint32_t real_offset, 1119 uint32_t *data) 1120 { 1121 /* no need to initialize in case of 32 bit type */ 1122 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) { 1123 *data = XEN_PT_INVALID_REG; 1124 } else { 1125 *data = reg->init_val; 1126 } 1127 1128 return 0; 1129 } 1130 /* this function will be called twice (for 32 bit and 64 bit type) */ 1131 /* initialize Message Data register */ 1132 static int xen_pt_msgdata_reg_init(XenPCIPassthroughState *s, 1133 XenPTRegInfo *reg, uint32_t real_offset, 1134 uint32_t *data) 1135 { 1136 uint32_t flags = s->msi->flags; 1137 uint32_t offset = reg->offset; 1138 1139 /* check the offset whether matches the type or not */ 1140 if (xen_pt_msi_check_type(offset, flags, DATA)) { 1141 *data = reg->init_val; 1142 } else { 1143 *data = XEN_PT_INVALID_REG; 1144 } 1145 return 0; 1146 } 1147 1148 /* this function will be called twice (for 32 bit and 64 bit type) */ 1149 /* initialize Mask register */ 1150 static int xen_pt_mask_reg_init(XenPCIPassthroughState *s, 1151 XenPTRegInfo *reg, uint32_t real_offset, 1152 uint32_t *data) 1153 { 1154 uint32_t flags = s->msi->flags; 1155 1156 /* check the offset whether matches the type or not */ 1157 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) { 1158 *data = XEN_PT_INVALID_REG; 1159 } else if (xen_pt_msi_check_type(reg->offset, flags, MASK)) { 1160 *data = reg->init_val; 1161 } else { 1162 *data = XEN_PT_INVALID_REG; 1163 } 1164 return 0; 1165 } 1166 1167 /* this function will be called twice (for 32 bit and 64 bit type) */ 1168 /* initialize Pending register */ 1169 static int xen_pt_pending_reg_init(XenPCIPassthroughState *s, 1170 XenPTRegInfo *reg, uint32_t real_offset, 1171 uint32_t *data) 1172 { 1173 uint32_t flags = s->msi->flags; 1174 1175 /* check the offset whether matches the type or not */ 1176 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) { 1177 *data = XEN_PT_INVALID_REG; 1178 } else if (xen_pt_msi_check_type(reg->offset, flags, PENDING)) { 1179 *data = reg->init_val; 1180 } else { 1181 *data = XEN_PT_INVALID_REG; 1182 } 1183 return 0; 1184 } 1185 1186 /* write Message Address register */ 1187 static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState *s, 1188 XenPTReg *cfg_entry, uint32_t *val, 1189 uint32_t dev_value, uint32_t valid_mask) 1190 { 1191 XenPTRegInfo *reg = cfg_entry->reg; 1192 uint32_t writable_mask = 0; 1193 uint32_t old_addr = cfg_entry->data; 1194 1195 /* modify emulate register */ 1196 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; 1197 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 1198 s->msi->addr_lo = cfg_entry->data; 1199 1200 /* create value for writing to I/O device register */ 1201 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0); 1202 1203 /* update MSI */ 1204 if (cfg_entry->data != old_addr) { 1205 if (s->msi->mapped) { 1206 xen_pt_msi_update(s); 1207 } 1208 } 1209 1210 return 0; 1211 } 1212 /* write Message Upper Address register */ 1213 static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState *s, 1214 XenPTReg *cfg_entry, uint32_t *val, 1215 uint32_t dev_value, uint32_t valid_mask) 1216 { 1217 XenPTRegInfo *reg = cfg_entry->reg; 1218 uint32_t writable_mask = 0; 1219 uint32_t old_addr = cfg_entry->data; 1220 1221 /* check whether the type is 64 bit or not */ 1222 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) { 1223 XEN_PT_ERR(&s->dev, 1224 "Can't write to the upper address without 64 bit support\n"); 1225 return -1; 1226 } 1227 1228 /* modify emulate register */ 1229 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; 1230 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 1231 /* update the msi_info too */ 1232 s->msi->addr_hi = cfg_entry->data; 1233 1234 /* create value for writing to I/O device register */ 1235 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0); 1236 1237 /* update MSI */ 1238 if (cfg_entry->data != old_addr) { 1239 if (s->msi->mapped) { 1240 xen_pt_msi_update(s); 1241 } 1242 } 1243 1244 return 0; 1245 } 1246 1247 1248 /* this function will be called twice (for 32 bit and 64 bit type) */ 1249 /* write Message Data register */ 1250 static int xen_pt_msgdata_reg_write(XenPCIPassthroughState *s, 1251 XenPTReg *cfg_entry, uint16_t *val, 1252 uint16_t dev_value, uint16_t valid_mask) 1253 { 1254 XenPTRegInfo *reg = cfg_entry->reg; 1255 XenPTMSI *msi = s->msi; 1256 uint16_t writable_mask = 0; 1257 uint16_t old_data = cfg_entry->data; 1258 uint32_t offset = reg->offset; 1259 1260 /* check the offset whether matches the type or not */ 1261 if (!xen_pt_msi_check_type(offset, msi->flags, DATA)) { 1262 /* exit I/O emulator */ 1263 XEN_PT_ERR(&s->dev, "the offset does not match the 32/64 bit type!\n"); 1264 return -1; 1265 } 1266 1267 /* modify emulate register */ 1268 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; 1269 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 1270 /* update the msi_info too */ 1271 msi->data = cfg_entry->data; 1272 1273 /* create value for writing to I/O device register */ 1274 *val = XEN_PT_MERGE_VALUE(*val, dev_value, 0); 1275 1276 /* update MSI */ 1277 if (cfg_entry->data != old_data) { 1278 if (msi->mapped) { 1279 xen_pt_msi_update(s); 1280 } 1281 } 1282 1283 return 0; 1284 } 1285 1286 /* MSI Capability Structure reg static information table */ 1287 static XenPTRegInfo xen_pt_emu_reg_msi[] = { 1288 /* Next Pointer reg */ 1289 { 1290 .offset = PCI_CAP_LIST_NEXT, 1291 .size = 1, 1292 .init_val = 0x00, 1293 .ro_mask = 0xFF, 1294 .emu_mask = 0xFF, 1295 .init = xen_pt_ptr_reg_init, 1296 .u.b.read = xen_pt_byte_reg_read, 1297 .u.b.write = xen_pt_byte_reg_write, 1298 }, 1299 /* Message Control reg */ 1300 { 1301 .offset = PCI_MSI_FLAGS, 1302 .size = 2, 1303 .init_val = 0x0000, 1304 .res_mask = 0xFE00, 1305 .ro_mask = 0x018E, 1306 .emu_mask = 0x017E, 1307 .init = xen_pt_msgctrl_reg_init, 1308 .u.w.read = xen_pt_word_reg_read, 1309 .u.w.write = xen_pt_msgctrl_reg_write, 1310 }, 1311 /* Message Address reg */ 1312 { 1313 .offset = PCI_MSI_ADDRESS_LO, 1314 .size = 4, 1315 .init_val = 0x00000000, 1316 .ro_mask = 0x00000003, 1317 .emu_mask = 0xFFFFFFFF, 1318 .init = xen_pt_common_reg_init, 1319 .u.dw.read = xen_pt_long_reg_read, 1320 .u.dw.write = xen_pt_msgaddr32_reg_write, 1321 }, 1322 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */ 1323 { 1324 .offset = PCI_MSI_ADDRESS_HI, 1325 .size = 4, 1326 .init_val = 0x00000000, 1327 .ro_mask = 0x00000000, 1328 .emu_mask = 0xFFFFFFFF, 1329 .init = xen_pt_msgaddr64_reg_init, 1330 .u.dw.read = xen_pt_long_reg_read, 1331 .u.dw.write = xen_pt_msgaddr64_reg_write, 1332 }, 1333 /* Message Data reg (16 bits of data for 32-bit devices) */ 1334 { 1335 .offset = PCI_MSI_DATA_32, 1336 .size = 2, 1337 .init_val = 0x0000, 1338 .ro_mask = 0x0000, 1339 .emu_mask = 0xFFFF, 1340 .init = xen_pt_msgdata_reg_init, 1341 .u.w.read = xen_pt_word_reg_read, 1342 .u.w.write = xen_pt_msgdata_reg_write, 1343 }, 1344 /* Message Data reg (16 bits of data for 64-bit devices) */ 1345 { 1346 .offset = PCI_MSI_DATA_64, 1347 .size = 2, 1348 .init_val = 0x0000, 1349 .ro_mask = 0x0000, 1350 .emu_mask = 0xFFFF, 1351 .init = xen_pt_msgdata_reg_init, 1352 .u.w.read = xen_pt_word_reg_read, 1353 .u.w.write = xen_pt_msgdata_reg_write, 1354 }, 1355 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */ 1356 { 1357 .offset = PCI_MSI_MASK_32, 1358 .size = 4, 1359 .init_val = 0x00000000, 1360 .ro_mask = 0xFFFFFFFF, 1361 .emu_mask = 0xFFFFFFFF, 1362 .init = xen_pt_mask_reg_init, 1363 .u.dw.read = xen_pt_long_reg_read, 1364 .u.dw.write = xen_pt_long_reg_write, 1365 }, 1366 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */ 1367 { 1368 .offset = PCI_MSI_MASK_64, 1369 .size = 4, 1370 .init_val = 0x00000000, 1371 .ro_mask = 0xFFFFFFFF, 1372 .emu_mask = 0xFFFFFFFF, 1373 .init = xen_pt_mask_reg_init, 1374 .u.dw.read = xen_pt_long_reg_read, 1375 .u.dw.write = xen_pt_long_reg_write, 1376 }, 1377 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */ 1378 { 1379 .offset = PCI_MSI_MASK_32 + 4, 1380 .size = 4, 1381 .init_val = 0x00000000, 1382 .ro_mask = 0xFFFFFFFF, 1383 .emu_mask = 0x00000000, 1384 .init = xen_pt_pending_reg_init, 1385 .u.dw.read = xen_pt_long_reg_read, 1386 .u.dw.write = xen_pt_long_reg_write, 1387 }, 1388 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */ 1389 { 1390 .offset = PCI_MSI_MASK_64 + 4, 1391 .size = 4, 1392 .init_val = 0x00000000, 1393 .ro_mask = 0xFFFFFFFF, 1394 .emu_mask = 0x00000000, 1395 .init = xen_pt_pending_reg_init, 1396 .u.dw.read = xen_pt_long_reg_read, 1397 .u.dw.write = xen_pt_long_reg_write, 1398 }, 1399 { 1400 .size = 0, 1401 }, 1402 }; 1403 1404 1405 /************************************** 1406 * MSI-X Capability 1407 */ 1408 1409 /* Message Control register for MSI-X */ 1410 static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState *s, 1411 XenPTRegInfo *reg, uint32_t real_offset, 1412 uint32_t *data) 1413 { 1414 PCIDevice *d = &s->dev; 1415 uint16_t reg_field = 0; 1416 1417 /* use I/O device register's value as initial value */ 1418 reg_field = pci_get_word(d->config + real_offset); 1419 1420 if (reg_field & PCI_MSIX_FLAGS_ENABLE) { 1421 XEN_PT_LOG(d, "MSIX already enabled, disabling it first\n"); 1422 xen_host_pci_set_word(&s->real_device, real_offset, 1423 reg_field & ~PCI_MSIX_FLAGS_ENABLE); 1424 } 1425 1426 s->msix->ctrl_offset = real_offset; 1427 1428 *data = reg->init_val; 1429 return 0; 1430 } 1431 static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState *s, 1432 XenPTReg *cfg_entry, uint16_t *val, 1433 uint16_t dev_value, uint16_t valid_mask) 1434 { 1435 XenPTRegInfo *reg = cfg_entry->reg; 1436 uint16_t writable_mask = 0; 1437 uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask); 1438 int debug_msix_enabled_old; 1439 1440 /* modify emulate register */ 1441 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; 1442 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); 1443 1444 /* create value for writing to I/O device register */ 1445 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); 1446 1447 /* update MSI-X */ 1448 if ((*val & PCI_MSIX_FLAGS_ENABLE) 1449 && !(*val & PCI_MSIX_FLAGS_MASKALL)) { 1450 xen_pt_msix_update(s); 1451 } else if (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) { 1452 xen_pt_msix_disable(s); 1453 } 1454 1455 debug_msix_enabled_old = s->msix->enabled; 1456 s->msix->enabled = !!(*val & PCI_MSIX_FLAGS_ENABLE); 1457 if (s->msix->enabled != debug_msix_enabled_old) { 1458 XEN_PT_LOG(&s->dev, "%s MSI-X\n", 1459 s->msix->enabled ? "enable" : "disable"); 1460 } 1461 1462 return 0; 1463 } 1464 1465 /* MSI-X Capability Structure reg static information table */ 1466 static XenPTRegInfo xen_pt_emu_reg_msix[] = { 1467 /* Next Pointer reg */ 1468 { 1469 .offset = PCI_CAP_LIST_NEXT, 1470 .size = 1, 1471 .init_val = 0x00, 1472 .ro_mask = 0xFF, 1473 .emu_mask = 0xFF, 1474 .init = xen_pt_ptr_reg_init, 1475 .u.b.read = xen_pt_byte_reg_read, 1476 .u.b.write = xen_pt_byte_reg_write, 1477 }, 1478 /* Message Control reg */ 1479 { 1480 .offset = PCI_MSI_FLAGS, 1481 .size = 2, 1482 .init_val = 0x0000, 1483 .res_mask = 0x3800, 1484 .ro_mask = 0x07FF, 1485 .emu_mask = 0x0000, 1486 .init = xen_pt_msixctrl_reg_init, 1487 .u.w.read = xen_pt_word_reg_read, 1488 .u.w.write = xen_pt_msixctrl_reg_write, 1489 }, 1490 { 1491 .size = 0, 1492 }, 1493 }; 1494 1495 1496 /**************************** 1497 * Capabilities 1498 */ 1499 1500 /* capability structure register group size functions */ 1501 1502 static int xen_pt_reg_grp_size_init(XenPCIPassthroughState *s, 1503 const XenPTRegGroupInfo *grp_reg, 1504 uint32_t base_offset, uint8_t *size) 1505 { 1506 *size = grp_reg->grp_size; 1507 return 0; 1508 } 1509 /* get Vendor Specific Capability Structure register group size */ 1510 static int xen_pt_vendor_size_init(XenPCIPassthroughState *s, 1511 const XenPTRegGroupInfo *grp_reg, 1512 uint32_t base_offset, uint8_t *size) 1513 { 1514 *size = pci_get_byte(s->dev.config + base_offset + 0x02); 1515 return 0; 1516 } 1517 /* get PCI Express Capability Structure register group size */ 1518 static int xen_pt_pcie_size_init(XenPCIPassthroughState *s, 1519 const XenPTRegGroupInfo *grp_reg, 1520 uint32_t base_offset, uint8_t *size) 1521 { 1522 PCIDevice *d = &s->dev; 1523 uint8_t version = get_capability_version(s, base_offset); 1524 uint8_t type = get_device_type(s, base_offset); 1525 uint8_t pcie_size = 0; 1526 1527 1528 /* calculate size depend on capability version and device/port type */ 1529 /* in case of PCI Express Base Specification Rev 1.x */ 1530 if (version == 1) { 1531 /* The PCI Express Capabilities, Device Capabilities, and Device 1532 * Status/Control registers are required for all PCI Express devices. 1533 * The Link Capabilities and Link Status/Control are required for all 1534 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints 1535 * are not required to implement registers other than those listed 1536 * above and terminate the capability structure. 1537 */ 1538 switch (type) { 1539 case PCI_EXP_TYPE_ENDPOINT: 1540 case PCI_EXP_TYPE_LEG_END: 1541 pcie_size = 0x14; 1542 break; 1543 case PCI_EXP_TYPE_RC_END: 1544 /* has no link */ 1545 pcie_size = 0x0C; 1546 break; 1547 /* only EndPoint passthrough is supported */ 1548 case PCI_EXP_TYPE_ROOT_PORT: 1549 case PCI_EXP_TYPE_UPSTREAM: 1550 case PCI_EXP_TYPE_DOWNSTREAM: 1551 case PCI_EXP_TYPE_PCI_BRIDGE: 1552 case PCI_EXP_TYPE_PCIE_BRIDGE: 1553 case PCI_EXP_TYPE_RC_EC: 1554 default: 1555 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type); 1556 return -1; 1557 } 1558 } 1559 /* in case of PCI Express Base Specification Rev 2.0 */ 1560 else if (version == 2) { 1561 switch (type) { 1562 case PCI_EXP_TYPE_ENDPOINT: 1563 case PCI_EXP_TYPE_LEG_END: 1564 case PCI_EXP_TYPE_RC_END: 1565 /* For Functions that do not implement the registers, 1566 * these spaces must be hardwired to 0b. 1567 */ 1568 pcie_size = 0x3C; 1569 break; 1570 /* only EndPoint passthrough is supported */ 1571 case PCI_EXP_TYPE_ROOT_PORT: 1572 case PCI_EXP_TYPE_UPSTREAM: 1573 case PCI_EXP_TYPE_DOWNSTREAM: 1574 case PCI_EXP_TYPE_PCI_BRIDGE: 1575 case PCI_EXP_TYPE_PCIE_BRIDGE: 1576 case PCI_EXP_TYPE_RC_EC: 1577 default: 1578 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type); 1579 return -1; 1580 } 1581 } else { 1582 XEN_PT_ERR(d, "Unsupported capability version %#x.\n", version); 1583 return -1; 1584 } 1585 1586 *size = pcie_size; 1587 return 0; 1588 } 1589 /* get MSI Capability Structure register group size */ 1590 static int xen_pt_msi_size_init(XenPCIPassthroughState *s, 1591 const XenPTRegGroupInfo *grp_reg, 1592 uint32_t base_offset, uint8_t *size) 1593 { 1594 PCIDevice *d = &s->dev; 1595 uint16_t msg_ctrl = 0; 1596 uint8_t msi_size = 0xa; 1597 1598 msg_ctrl = pci_get_word(d->config + (base_offset + PCI_MSI_FLAGS)); 1599 1600 /* check if 64-bit address is capable of per-vector masking */ 1601 if (msg_ctrl & PCI_MSI_FLAGS_64BIT) { 1602 msi_size += 4; 1603 } 1604 if (msg_ctrl & PCI_MSI_FLAGS_MASKBIT) { 1605 msi_size += 10; 1606 } 1607 1608 s->msi = g_new0(XenPTMSI, 1); 1609 s->msi->pirq = XEN_PT_UNASSIGNED_PIRQ; 1610 1611 *size = msi_size; 1612 return 0; 1613 } 1614 /* get MSI-X Capability Structure register group size */ 1615 static int xen_pt_msix_size_init(XenPCIPassthroughState *s, 1616 const XenPTRegGroupInfo *grp_reg, 1617 uint32_t base_offset, uint8_t *size) 1618 { 1619 int rc = 0; 1620 1621 rc = xen_pt_msix_init(s, base_offset); 1622 1623 if (rc < 0) { 1624 XEN_PT_ERR(&s->dev, "Internal error: Invalid xen_pt_msix_init.\n"); 1625 return rc; 1626 } 1627 1628 *size = grp_reg->grp_size; 1629 return 0; 1630 } 1631 1632 1633 static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = { 1634 /* Header Type0 reg group */ 1635 { 1636 .grp_id = 0xFF, 1637 .grp_type = XEN_PT_GRP_TYPE_EMU, 1638 .grp_size = 0x40, 1639 .size_init = xen_pt_reg_grp_size_init, 1640 .emu_regs = xen_pt_emu_reg_header0, 1641 }, 1642 /* PCI PowerManagement Capability reg group */ 1643 { 1644 .grp_id = PCI_CAP_ID_PM, 1645 .grp_type = XEN_PT_GRP_TYPE_EMU, 1646 .grp_size = PCI_PM_SIZEOF, 1647 .size_init = xen_pt_reg_grp_size_init, 1648 .emu_regs = xen_pt_emu_reg_pm, 1649 }, 1650 /* AGP Capability Structure reg group */ 1651 { 1652 .grp_id = PCI_CAP_ID_AGP, 1653 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED, 1654 .grp_size = 0x30, 1655 .size_init = xen_pt_reg_grp_size_init, 1656 }, 1657 /* Vital Product Data Capability Structure reg group */ 1658 { 1659 .grp_id = PCI_CAP_ID_VPD, 1660 .grp_type = XEN_PT_GRP_TYPE_EMU, 1661 .grp_size = 0x08, 1662 .size_init = xen_pt_reg_grp_size_init, 1663 .emu_regs = xen_pt_emu_reg_vpd, 1664 }, 1665 /* Slot Identification reg group */ 1666 { 1667 .grp_id = PCI_CAP_ID_SLOTID, 1668 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED, 1669 .grp_size = 0x04, 1670 .size_init = xen_pt_reg_grp_size_init, 1671 }, 1672 /* MSI Capability Structure reg group */ 1673 { 1674 .grp_id = PCI_CAP_ID_MSI, 1675 .grp_type = XEN_PT_GRP_TYPE_EMU, 1676 .grp_size = 0xFF, 1677 .size_init = xen_pt_msi_size_init, 1678 .emu_regs = xen_pt_emu_reg_msi, 1679 }, 1680 /* PCI-X Capabilities List Item reg group */ 1681 { 1682 .grp_id = PCI_CAP_ID_PCIX, 1683 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED, 1684 .grp_size = 0x18, 1685 .size_init = xen_pt_reg_grp_size_init, 1686 }, 1687 /* Vendor Specific Capability Structure reg group */ 1688 { 1689 .grp_id = PCI_CAP_ID_VNDR, 1690 .grp_type = XEN_PT_GRP_TYPE_EMU, 1691 .grp_size = 0xFF, 1692 .size_init = xen_pt_vendor_size_init, 1693 .emu_regs = xen_pt_emu_reg_vendor, 1694 }, 1695 /* SHPC Capability List Item reg group */ 1696 { 1697 .grp_id = PCI_CAP_ID_SHPC, 1698 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED, 1699 .grp_size = 0x08, 1700 .size_init = xen_pt_reg_grp_size_init, 1701 }, 1702 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */ 1703 { 1704 .grp_id = PCI_CAP_ID_SSVID, 1705 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED, 1706 .grp_size = 0x08, 1707 .size_init = xen_pt_reg_grp_size_init, 1708 }, 1709 /* AGP 8x Capability Structure reg group */ 1710 { 1711 .grp_id = PCI_CAP_ID_AGP3, 1712 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED, 1713 .grp_size = 0x30, 1714 .size_init = xen_pt_reg_grp_size_init, 1715 }, 1716 /* PCI Express Capability Structure reg group */ 1717 { 1718 .grp_id = PCI_CAP_ID_EXP, 1719 .grp_type = XEN_PT_GRP_TYPE_EMU, 1720 .grp_size = 0xFF, 1721 .size_init = xen_pt_pcie_size_init, 1722 .emu_regs = xen_pt_emu_reg_pcie, 1723 }, 1724 /* MSI-X Capability Structure reg group */ 1725 { 1726 .grp_id = PCI_CAP_ID_MSIX, 1727 .grp_type = XEN_PT_GRP_TYPE_EMU, 1728 .grp_size = 0x0C, 1729 .size_init = xen_pt_msix_size_init, 1730 .emu_regs = xen_pt_emu_reg_msix, 1731 }, 1732 { 1733 .grp_size = 0, 1734 }, 1735 }; 1736 1737 /* initialize Capabilities Pointer or Next Pointer register */ 1738 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, 1739 XenPTRegInfo *reg, uint32_t real_offset, 1740 uint32_t *data) 1741 { 1742 int i; 1743 uint8_t *config = s->dev.config; 1744 uint32_t reg_field = pci_get_byte(config + real_offset); 1745 uint8_t cap_id = 0; 1746 1747 /* find capability offset */ 1748 while (reg_field) { 1749 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) { 1750 if (xen_pt_hide_dev_cap(&s->real_device, 1751 xen_pt_emu_reg_grps[i].grp_id)) { 1752 continue; 1753 } 1754 1755 cap_id = pci_get_byte(config + reg_field + PCI_CAP_LIST_ID); 1756 if (xen_pt_emu_reg_grps[i].grp_id == cap_id) { 1757 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) { 1758 goto out; 1759 } 1760 /* ignore the 0 hardwired capability, find next one */ 1761 break; 1762 } 1763 } 1764 1765 /* next capability */ 1766 reg_field = pci_get_byte(config + reg_field + PCI_CAP_LIST_NEXT); 1767 } 1768 1769 out: 1770 *data = reg_field; 1771 return 0; 1772 } 1773 1774 1775 /************* 1776 * Main 1777 */ 1778 1779 static uint8_t find_cap_offset(XenPCIPassthroughState *s, uint8_t cap) 1780 { 1781 uint8_t id; 1782 unsigned max_cap = PCI_CAP_MAX; 1783 uint8_t pos = PCI_CAPABILITY_LIST; 1784 uint8_t status = 0; 1785 1786 if (xen_host_pci_get_byte(&s->real_device, PCI_STATUS, &status)) { 1787 return 0; 1788 } 1789 if ((status & PCI_STATUS_CAP_LIST) == 0) { 1790 return 0; 1791 } 1792 1793 while (max_cap--) { 1794 if (xen_host_pci_get_byte(&s->real_device, pos, &pos)) { 1795 break; 1796 } 1797 if (pos < PCI_CONFIG_HEADER_SIZE) { 1798 break; 1799 } 1800 1801 pos &= ~3; 1802 if (xen_host_pci_get_byte(&s->real_device, 1803 pos + PCI_CAP_LIST_ID, &id)) { 1804 break; 1805 } 1806 1807 if (id == 0xff) { 1808 break; 1809 } 1810 if (id == cap) { 1811 return pos; 1812 } 1813 1814 pos += PCI_CAP_LIST_NEXT; 1815 } 1816 return 0; 1817 } 1818 1819 static int xen_pt_config_reg_init(XenPCIPassthroughState *s, 1820 XenPTRegGroup *reg_grp, XenPTRegInfo *reg) 1821 { 1822 XenPTReg *reg_entry; 1823 uint32_t data = 0; 1824 int rc = 0; 1825 1826 reg_entry = g_new0(XenPTReg, 1); 1827 reg_entry->reg = reg; 1828 1829 if (reg->init) { 1830 /* initialize emulate register */ 1831 rc = reg->init(s, reg_entry->reg, 1832 reg_grp->base_offset + reg->offset, &data); 1833 if (rc < 0) { 1834 g_free(reg_entry); 1835 return rc; 1836 } 1837 if (data == XEN_PT_INVALID_REG) { 1838 /* free unused BAR register entry */ 1839 g_free(reg_entry); 1840 return 0; 1841 } 1842 /* set register value */ 1843 reg_entry->data = data; 1844 } 1845 /* list add register entry */ 1846 QLIST_INSERT_HEAD(®_grp->reg_tbl_list, reg_entry, entries); 1847 1848 return 0; 1849 } 1850 1851 int xen_pt_config_init(XenPCIPassthroughState *s) 1852 { 1853 int i, rc; 1854 1855 QLIST_INIT(&s->reg_grps); 1856 1857 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) { 1858 uint32_t reg_grp_offset = 0; 1859 XenPTRegGroup *reg_grp_entry = NULL; 1860 1861 if (xen_pt_emu_reg_grps[i].grp_id != 0xFF) { 1862 if (xen_pt_hide_dev_cap(&s->real_device, 1863 xen_pt_emu_reg_grps[i].grp_id)) { 1864 continue; 1865 } 1866 1867 reg_grp_offset = find_cap_offset(s, xen_pt_emu_reg_grps[i].grp_id); 1868 1869 if (!reg_grp_offset) { 1870 continue; 1871 } 1872 } 1873 1874 reg_grp_entry = g_new0(XenPTRegGroup, 1); 1875 QLIST_INIT(®_grp_entry->reg_tbl_list); 1876 QLIST_INSERT_HEAD(&s->reg_grps, reg_grp_entry, entries); 1877 1878 reg_grp_entry->base_offset = reg_grp_offset; 1879 reg_grp_entry->reg_grp = xen_pt_emu_reg_grps + i; 1880 if (xen_pt_emu_reg_grps[i].size_init) { 1881 /* get register group size */ 1882 rc = xen_pt_emu_reg_grps[i].size_init(s, reg_grp_entry->reg_grp, 1883 reg_grp_offset, 1884 ®_grp_entry->size); 1885 if (rc < 0) { 1886 xen_pt_config_delete(s); 1887 return rc; 1888 } 1889 } 1890 1891 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) { 1892 if (xen_pt_emu_reg_grps[i].emu_regs) { 1893 int j = 0; 1894 XenPTRegInfo *regs = xen_pt_emu_reg_grps[i].emu_regs; 1895 /* initialize capability register */ 1896 for (j = 0; regs->size != 0; j++, regs++) { 1897 /* initialize capability register */ 1898 rc = xen_pt_config_reg_init(s, reg_grp_entry, regs); 1899 if (rc < 0) { 1900 xen_pt_config_delete(s); 1901 return rc; 1902 } 1903 } 1904 } 1905 } 1906 } 1907 1908 return 0; 1909 } 1910 1911 /* delete all emulate register */ 1912 void xen_pt_config_delete(XenPCIPassthroughState *s) 1913 { 1914 struct XenPTRegGroup *reg_group, *next_grp; 1915 struct XenPTReg *reg, *next_reg; 1916 1917 /* free MSI/MSI-X info table */ 1918 if (s->msix) { 1919 xen_pt_msix_delete(s); 1920 } 1921 if (s->msi) { 1922 g_free(s->msi); 1923 } 1924 1925 /* free all register group entry */ 1926 QLIST_FOREACH_SAFE(reg_group, &s->reg_grps, entries, next_grp) { 1927 /* free all register entry */ 1928 QLIST_FOREACH_SAFE(reg, ®_group->reg_tbl_list, entries, next_reg) { 1929 QLIST_REMOVE(reg, entries); 1930 g_free(reg); 1931 } 1932 1933 QLIST_REMOVE(reg_group, entries); 1934 g_free(reg_group); 1935 } 1936 } 1937