1 /* 2 * Copyright (c) 2007, Neocleus Corporation. 3 * Copyright (c) 2007, Intel Corporation. 4 * 5 * This work is licensed under the terms of the GNU GPL, version 2. See 6 * the COPYING file in the top-level directory. 7 * 8 * Alex Novik <alex@neocleus.com> 9 * Allen Kay <allen.m.kay@intel.com> 10 * Guy Zana <guy@neocleus.com> 11 * 12 * This file implements direct PCI assignment to a HVM guest 13 */ 14 15 /* 16 * Interrupt Disable policy: 17 * 18 * INTx interrupt: 19 * Initialize(register_real_device) 20 * Map INTx(xc_physdev_map_pirq): 21 * <fail> 22 * - Set real Interrupt Disable bit to '1'. 23 * - Set machine_irq and assigned_device->machine_irq to '0'. 24 * * Don't bind INTx. 25 * 26 * Bind INTx(xc_domain_bind_pt_pci_irq): 27 * <fail> 28 * - Set real Interrupt Disable bit to '1'. 29 * - Unmap INTx. 30 * - Decrement xen_pt_mapped_machine_irq[machine_irq] 31 * - Set assigned_device->machine_irq to '0'. 32 * 33 * Write to Interrupt Disable bit by guest software(xen_pt_cmd_reg_write) 34 * Write '0' 35 * - Set real bit to '0' if assigned_device->machine_irq isn't '0'. 36 * 37 * Write '1' 38 * - Set real bit to '1'. 39 * 40 * MSI interrupt: 41 * Initialize MSI register(xen_pt_msi_setup, xen_pt_msi_update) 42 * Bind MSI(xc_domain_update_msi_irq) 43 * <fail> 44 * - Unmap MSI. 45 * - Set dev->msi->pirq to '-1'. 46 * 47 * MSI-X interrupt: 48 * Initialize MSI-X register(xen_pt_msix_update_one) 49 * Bind MSI-X(xc_domain_update_msi_irq) 50 * <fail> 51 * - Unmap MSI-X. 52 * - Set entry->pirq to '-1'. 53 */ 54 55 #include <sys/ioctl.h> 56 57 #include "hw/pci/pci.h" 58 #include "hw/xen/xen.h" 59 #include "hw/xen/xen_backend.h" 60 #include "xen_pt.h" 61 #include "qemu/range.h" 62 #include "exec/address-spaces.h" 63 64 #define XEN_PT_NR_IRQS (256) 65 static uint8_t xen_pt_mapped_machine_irq[XEN_PT_NR_IRQS] = {0}; 66 67 void xen_pt_log(const PCIDevice *d, const char *f, ...) 68 { 69 va_list ap; 70 71 va_start(ap, f); 72 if (d) { 73 fprintf(stderr, "[%02x:%02x.%d] ", pci_bus_num(d->bus), 74 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn)); 75 } 76 vfprintf(stderr, f, ap); 77 va_end(ap); 78 } 79 80 /* Config Space */ 81 82 static int xen_pt_pci_config_access_check(PCIDevice *d, uint32_t addr, int len) 83 { 84 /* check offset range */ 85 if (addr >= 0xFF) { 86 XEN_PT_ERR(d, "Failed to access register with offset exceeding 0xFF. " 87 "(addr: 0x%02x, len: %d)\n", addr, len); 88 return -1; 89 } 90 91 /* check read size */ 92 if ((len != 1) && (len != 2) && (len != 4)) { 93 XEN_PT_ERR(d, "Failed to access register with invalid access length. " 94 "(addr: 0x%02x, len: %d)\n", addr, len); 95 return -1; 96 } 97 98 /* check offset alignment */ 99 if (addr & (len - 1)) { 100 XEN_PT_ERR(d, "Failed to access register with invalid access size " 101 "alignment. (addr: 0x%02x, len: %d)\n", addr, len); 102 return -1; 103 } 104 105 return 0; 106 } 107 108 int xen_pt_bar_offset_to_index(uint32_t offset) 109 { 110 int index = 0; 111 112 /* check Exp ROM BAR */ 113 if (offset == PCI_ROM_ADDRESS) { 114 return PCI_ROM_SLOT; 115 } 116 117 /* calculate BAR index */ 118 index = (offset - PCI_BASE_ADDRESS_0) >> 2; 119 if (index >= PCI_NUM_REGIONS) { 120 return -1; 121 } 122 123 return index; 124 } 125 126 static uint32_t xen_pt_pci_read_config(PCIDevice *d, uint32_t addr, int len) 127 { 128 XenPCIPassthroughState *s = XEN_PT_DEVICE(d); 129 uint32_t val = 0; 130 XenPTRegGroup *reg_grp_entry = NULL; 131 XenPTReg *reg_entry = NULL; 132 int rc = 0; 133 int emul_len = 0; 134 uint32_t find_addr = addr; 135 136 if (xen_pt_pci_config_access_check(d, addr, len)) { 137 goto exit; 138 } 139 140 /* find register group entry */ 141 reg_grp_entry = xen_pt_find_reg_grp(s, addr); 142 if (reg_grp_entry) { 143 /* check 0-Hardwired register group */ 144 if (reg_grp_entry->reg_grp->grp_type == XEN_PT_GRP_TYPE_HARDWIRED) { 145 /* no need to emulate, just return 0 */ 146 val = 0; 147 goto exit; 148 } 149 } 150 151 /* read I/O device register value */ 152 rc = xen_host_pci_get_block(&s->real_device, addr, (uint8_t *)&val, len); 153 if (rc < 0) { 154 XEN_PT_ERR(d, "pci_read_block failed. return value: %d.\n", rc); 155 memset(&val, 0xff, len); 156 } 157 158 /* just return the I/O device register value for 159 * passthrough type register group */ 160 if (reg_grp_entry == NULL) { 161 goto exit; 162 } 163 164 /* adjust the read value to appropriate CFC-CFF window */ 165 val <<= (addr & 3) << 3; 166 emul_len = len; 167 168 /* loop around the guest requested size */ 169 while (emul_len > 0) { 170 /* find register entry to be emulated */ 171 reg_entry = xen_pt_find_reg(reg_grp_entry, find_addr); 172 if (reg_entry) { 173 XenPTRegInfo *reg = reg_entry->reg; 174 uint32_t real_offset = reg_grp_entry->base_offset + reg->offset; 175 uint32_t valid_mask = 0xFFFFFFFF >> ((4 - emul_len) << 3); 176 uint8_t *ptr_val = NULL; 177 178 valid_mask <<= (find_addr - real_offset) << 3; 179 ptr_val = (uint8_t *)&val + (real_offset & 3); 180 181 /* do emulation based on register size */ 182 switch (reg->size) { 183 case 1: 184 if (reg->u.b.read) { 185 rc = reg->u.b.read(s, reg_entry, ptr_val, valid_mask); 186 } 187 break; 188 case 2: 189 if (reg->u.w.read) { 190 rc = reg->u.w.read(s, reg_entry, 191 (uint16_t *)ptr_val, valid_mask); 192 } 193 break; 194 case 4: 195 if (reg->u.dw.read) { 196 rc = reg->u.dw.read(s, reg_entry, 197 (uint32_t *)ptr_val, valid_mask); 198 } 199 break; 200 } 201 202 if (rc < 0) { 203 xen_shutdown_fatal_error("Internal error: Invalid read " 204 "emulation. (%s, rc: %d)\n", 205 __func__, rc); 206 return 0; 207 } 208 209 /* calculate next address to find */ 210 emul_len -= reg->size; 211 if (emul_len > 0) { 212 find_addr = real_offset + reg->size; 213 } 214 } else { 215 /* nothing to do with passthrough type register, 216 * continue to find next byte */ 217 emul_len--; 218 find_addr++; 219 } 220 } 221 222 /* need to shift back before returning them to pci bus emulator */ 223 val >>= ((addr & 3) << 3); 224 225 exit: 226 XEN_PT_LOG_CONFIG(d, addr, val, len); 227 return val; 228 } 229 230 static void xen_pt_pci_write_config(PCIDevice *d, uint32_t addr, 231 uint32_t val, int len) 232 { 233 XenPCIPassthroughState *s = XEN_PT_DEVICE(d); 234 int index = 0; 235 XenPTRegGroup *reg_grp_entry = NULL; 236 int rc = 0; 237 uint32_t read_val = 0, wb_mask; 238 int emul_len = 0; 239 XenPTReg *reg_entry = NULL; 240 uint32_t find_addr = addr; 241 XenPTRegInfo *reg = NULL; 242 bool wp_flag = false; 243 244 if (xen_pt_pci_config_access_check(d, addr, len)) { 245 return; 246 } 247 248 XEN_PT_LOG_CONFIG(d, addr, val, len); 249 250 /* check unused BAR register */ 251 index = xen_pt_bar_offset_to_index(addr); 252 if ((index >= 0) && (val != 0)) { 253 uint32_t chk = val; 254 255 if (index == PCI_ROM_SLOT) 256 chk |= (uint32_t)~PCI_ROM_ADDRESS_MASK; 257 258 if ((chk != XEN_PT_BAR_ALLF) && 259 (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED)) { 260 XEN_PT_WARN(d, "Guest attempt to set address to unused " 261 "Base Address Register. (addr: 0x%02x, len: %d)\n", 262 addr, len); 263 } 264 } 265 266 /* find register group entry */ 267 reg_grp_entry = xen_pt_find_reg_grp(s, addr); 268 if (reg_grp_entry) { 269 /* check 0-Hardwired register group */ 270 if (reg_grp_entry->reg_grp->grp_type == XEN_PT_GRP_TYPE_HARDWIRED) { 271 /* ignore silently */ 272 XEN_PT_WARN(d, "Access to 0-Hardwired register. " 273 "(addr: 0x%02x, len: %d)\n", addr, len); 274 return; 275 } 276 } 277 278 rc = xen_host_pci_get_block(&s->real_device, addr, 279 (uint8_t *)&read_val, len); 280 if (rc < 0) { 281 XEN_PT_ERR(d, "pci_read_block failed. return value: %d.\n", rc); 282 memset(&read_val, 0xff, len); 283 wb_mask = 0; 284 } else { 285 wb_mask = 0xFFFFFFFF >> ((4 - len) << 3); 286 } 287 288 /* pass directly to the real device for passthrough type register group */ 289 if (reg_grp_entry == NULL) { 290 if (!s->permissive) { 291 wb_mask = 0; 292 wp_flag = true; 293 } 294 goto out; 295 } 296 297 memory_region_transaction_begin(); 298 pci_default_write_config(d, addr, val, len); 299 300 /* adjust the read and write value to appropriate CFC-CFF window */ 301 read_val <<= (addr & 3) << 3; 302 val <<= (addr & 3) << 3; 303 emul_len = len; 304 305 /* loop around the guest requested size */ 306 while (emul_len > 0) { 307 /* find register entry to be emulated */ 308 reg_entry = xen_pt_find_reg(reg_grp_entry, find_addr); 309 if (reg_entry) { 310 reg = reg_entry->reg; 311 uint32_t real_offset = reg_grp_entry->base_offset + reg->offset; 312 uint32_t valid_mask = 0xFFFFFFFF >> ((4 - emul_len) << 3); 313 uint8_t *ptr_val = NULL; 314 uint32_t wp_mask = reg->emu_mask | reg->ro_mask; 315 316 valid_mask <<= (find_addr - real_offset) << 3; 317 ptr_val = (uint8_t *)&val + (real_offset & 3); 318 if (!s->permissive) { 319 wp_mask |= reg->res_mask; 320 } 321 if (wp_mask == (0xFFFFFFFF >> ((4 - reg->size) << 3))) { 322 wb_mask &= ~((wp_mask >> ((find_addr - real_offset) << 3)) 323 << ((len - emul_len) << 3)); 324 } 325 326 /* do emulation based on register size */ 327 switch (reg->size) { 328 case 1: 329 if (reg->u.b.write) { 330 rc = reg->u.b.write(s, reg_entry, ptr_val, 331 read_val >> ((real_offset & 3) << 3), 332 valid_mask); 333 } 334 break; 335 case 2: 336 if (reg->u.w.write) { 337 rc = reg->u.w.write(s, reg_entry, (uint16_t *)ptr_val, 338 (read_val >> ((real_offset & 3) << 3)), 339 valid_mask); 340 } 341 break; 342 case 4: 343 if (reg->u.dw.write) { 344 rc = reg->u.dw.write(s, reg_entry, (uint32_t *)ptr_val, 345 (read_val >> ((real_offset & 3) << 3)), 346 valid_mask); 347 } 348 break; 349 } 350 351 if (rc < 0) { 352 xen_shutdown_fatal_error("Internal error: Invalid write" 353 " emulation. (%s, rc: %d)\n", 354 __func__, rc); 355 return; 356 } 357 358 /* calculate next address to find */ 359 emul_len -= reg->size; 360 if (emul_len > 0) { 361 find_addr = real_offset + reg->size; 362 } 363 } else { 364 /* nothing to do with passthrough type register, 365 * continue to find next byte */ 366 if (!s->permissive) { 367 wb_mask &= ~(0xff << ((len - emul_len) << 3)); 368 /* Unused BARs will make it here, but we don't want to issue 369 * warnings for writes to them (bogus writes get dealt with 370 * above). 371 */ 372 if (index < 0) { 373 wp_flag = true; 374 } 375 } 376 emul_len--; 377 find_addr++; 378 } 379 } 380 381 /* need to shift back before passing them to xen_host_pci_device */ 382 val >>= (addr & 3) << 3; 383 384 memory_region_transaction_commit(); 385 386 out: 387 if (wp_flag && !s->permissive_warned) { 388 s->permissive_warned = true; 389 xen_pt_log(d, "Write-back to unknown field 0x%02x (partially) inhibited (0x%0*x)\n", 390 addr, len * 2, wb_mask); 391 xen_pt_log(d, "If the device doesn't work, try enabling permissive mode\n"); 392 xen_pt_log(d, "(unsafe) and if it helps report the problem to xen-devel\n"); 393 } 394 for (index = 0; wb_mask; index += len) { 395 /* unknown regs are passed through */ 396 while (!(wb_mask & 0xff)) { 397 index++; 398 wb_mask >>= 8; 399 } 400 len = 0; 401 do { 402 len++; 403 wb_mask >>= 8; 404 } while (wb_mask & 0xff); 405 rc = xen_host_pci_set_block(&s->real_device, addr + index, 406 (uint8_t *)&val + index, len); 407 408 if (rc < 0) { 409 XEN_PT_ERR(d, "pci_write_block failed. return value: %d.\n", rc); 410 } 411 } 412 } 413 414 /* register regions */ 415 416 static uint64_t xen_pt_bar_read(void *o, hwaddr addr, 417 unsigned size) 418 { 419 PCIDevice *d = o; 420 /* if this function is called, that probably means that there is a 421 * misconfiguration of the IOMMU. */ 422 XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"TARGET_FMT_plx"\n", 423 addr); 424 return 0; 425 } 426 static void xen_pt_bar_write(void *o, hwaddr addr, uint64_t val, 427 unsigned size) 428 { 429 PCIDevice *d = o; 430 /* Same comment as xen_pt_bar_read function */ 431 XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"TARGET_FMT_plx"\n", 432 addr); 433 } 434 435 static const MemoryRegionOps ops = { 436 .endianness = DEVICE_NATIVE_ENDIAN, 437 .read = xen_pt_bar_read, 438 .write = xen_pt_bar_write, 439 }; 440 441 static int xen_pt_register_regions(XenPCIPassthroughState *s, uint16_t *cmd) 442 { 443 int i = 0; 444 XenHostPCIDevice *d = &s->real_device; 445 446 /* Register PIO/MMIO BARs */ 447 for (i = 0; i < PCI_ROM_SLOT; i++) { 448 XenHostPCIIORegion *r = &d->io_regions[i]; 449 uint8_t type; 450 451 if (r->base_addr == 0 || r->size == 0) { 452 continue; 453 } 454 455 s->bases[i].access.u = r->base_addr; 456 457 if (r->type & XEN_HOST_PCI_REGION_TYPE_IO) { 458 type = PCI_BASE_ADDRESS_SPACE_IO; 459 *cmd |= PCI_COMMAND_IO; 460 } else { 461 type = PCI_BASE_ADDRESS_SPACE_MEMORY; 462 if (r->type & XEN_HOST_PCI_REGION_TYPE_PREFETCH) { 463 type |= PCI_BASE_ADDRESS_MEM_PREFETCH; 464 } 465 if (r->type & XEN_HOST_PCI_REGION_TYPE_MEM_64) { 466 type |= PCI_BASE_ADDRESS_MEM_TYPE_64; 467 } 468 *cmd |= PCI_COMMAND_MEMORY; 469 } 470 471 memory_region_init_io(&s->bar[i], OBJECT(s), &ops, &s->dev, 472 "xen-pci-pt-bar", r->size); 473 pci_register_bar(&s->dev, i, type, &s->bar[i]); 474 475 XEN_PT_LOG(&s->dev, "IO region %i registered (size=0x%08"PRIx64 476 " base_addr=0x%08"PRIx64" type: %#x)\n", 477 i, r->size, r->base_addr, type); 478 } 479 480 /* Register expansion ROM address */ 481 if (d->rom.base_addr && d->rom.size) { 482 uint32_t bar_data = 0; 483 484 /* Re-set BAR reported by OS, otherwise ROM can't be read. */ 485 if (xen_host_pci_get_long(d, PCI_ROM_ADDRESS, &bar_data)) { 486 return 0; 487 } 488 if ((bar_data & PCI_ROM_ADDRESS_MASK) == 0) { 489 bar_data |= d->rom.base_addr & PCI_ROM_ADDRESS_MASK; 490 xen_host_pci_set_long(d, PCI_ROM_ADDRESS, bar_data); 491 } 492 493 s->bases[PCI_ROM_SLOT].access.maddr = d->rom.base_addr; 494 495 memory_region_init_io(&s->rom, OBJECT(s), &ops, &s->dev, 496 "xen-pci-pt-rom", d->rom.size); 497 pci_register_bar(&s->dev, PCI_ROM_SLOT, PCI_BASE_ADDRESS_MEM_PREFETCH, 498 &s->rom); 499 500 XEN_PT_LOG(&s->dev, "Expansion ROM registered (size=0x%08"PRIx64 501 " base_addr=0x%08"PRIx64")\n", 502 d->rom.size, d->rom.base_addr); 503 } 504 505 return 0; 506 } 507 508 /* region mapping */ 509 510 static int xen_pt_bar_from_region(XenPCIPassthroughState *s, MemoryRegion *mr) 511 { 512 int i = 0; 513 514 for (i = 0; i < PCI_NUM_REGIONS - 1; i++) { 515 if (mr == &s->bar[i]) { 516 return i; 517 } 518 } 519 if (mr == &s->rom) { 520 return PCI_ROM_SLOT; 521 } 522 return -1; 523 } 524 525 /* 526 * This function checks if an io_region overlaps an io_region from another 527 * device. The io_region to check is provided with (addr, size and type) 528 * A callback can be provided and will be called for every region that is 529 * overlapped. 530 * The return value indicates if the region is overlappsed */ 531 struct CheckBarArgs { 532 XenPCIPassthroughState *s; 533 pcibus_t addr; 534 pcibus_t size; 535 uint8_t type; 536 bool rc; 537 }; 538 static void xen_pt_check_bar_overlap(PCIBus *bus, PCIDevice *d, void *opaque) 539 { 540 struct CheckBarArgs *arg = opaque; 541 XenPCIPassthroughState *s = arg->s; 542 uint8_t type = arg->type; 543 int i; 544 545 if (d->devfn == s->dev.devfn) { 546 return; 547 } 548 549 /* xxx: This ignores bridges. */ 550 for (i = 0; i < PCI_NUM_REGIONS; i++) { 551 const PCIIORegion *r = &d->io_regions[i]; 552 553 if (!r->size) { 554 continue; 555 } 556 if ((type & PCI_BASE_ADDRESS_SPACE_IO) 557 != (r->type & PCI_BASE_ADDRESS_SPACE_IO)) { 558 continue; 559 } 560 561 if (ranges_overlap(arg->addr, arg->size, r->addr, r->size)) { 562 XEN_PT_WARN(&s->dev, 563 "Overlapped to device [%02x:%02x.%d] Region: %i" 564 " (addr: %#"FMT_PCIBUS", len: %#"FMT_PCIBUS")\n", 565 pci_bus_num(bus), PCI_SLOT(d->devfn), 566 PCI_FUNC(d->devfn), i, r->addr, r->size); 567 arg->rc = true; 568 } 569 } 570 } 571 572 static void xen_pt_region_update(XenPCIPassthroughState *s, 573 MemoryRegionSection *sec, bool adding) 574 { 575 PCIDevice *d = &s->dev; 576 MemoryRegion *mr = sec->mr; 577 int bar = -1; 578 int rc; 579 int op = adding ? DPCI_ADD_MAPPING : DPCI_REMOVE_MAPPING; 580 struct CheckBarArgs args = { 581 .s = s, 582 .addr = sec->offset_within_address_space, 583 .size = int128_get64(sec->size), 584 .rc = false, 585 }; 586 587 bar = xen_pt_bar_from_region(s, mr); 588 if (bar == -1 && (!s->msix || &s->msix->mmio != mr)) { 589 return; 590 } 591 592 if (s->msix && &s->msix->mmio == mr) { 593 if (adding) { 594 s->msix->mmio_base_addr = sec->offset_within_address_space; 595 rc = xen_pt_msix_update_remap(s, s->msix->bar_index); 596 } 597 return; 598 } 599 600 args.type = d->io_regions[bar].type; 601 pci_for_each_device(d->bus, pci_bus_num(d->bus), 602 xen_pt_check_bar_overlap, &args); 603 if (args.rc) { 604 XEN_PT_WARN(d, "Region: %d (addr: %#"FMT_PCIBUS 605 ", len: %#"FMT_PCIBUS") is overlapped.\n", 606 bar, sec->offset_within_address_space, 607 int128_get64(sec->size)); 608 } 609 610 if (d->io_regions[bar].type & PCI_BASE_ADDRESS_SPACE_IO) { 611 uint32_t guest_port = sec->offset_within_address_space; 612 uint32_t machine_port = s->bases[bar].access.pio_base; 613 uint32_t size = int128_get64(sec->size); 614 rc = xc_domain_ioport_mapping(xen_xc, xen_domid, 615 guest_port, machine_port, size, 616 op); 617 if (rc) { 618 XEN_PT_ERR(d, "%s ioport mapping failed! (err: %i)\n", 619 adding ? "create new" : "remove old", errno); 620 } 621 } else { 622 pcibus_t guest_addr = sec->offset_within_address_space; 623 pcibus_t machine_addr = s->bases[bar].access.maddr 624 + sec->offset_within_region; 625 pcibus_t size = int128_get64(sec->size); 626 rc = xc_domain_memory_mapping(xen_xc, xen_domid, 627 XEN_PFN(guest_addr + XC_PAGE_SIZE - 1), 628 XEN_PFN(machine_addr + XC_PAGE_SIZE - 1), 629 XEN_PFN(size + XC_PAGE_SIZE - 1), 630 op); 631 if (rc) { 632 XEN_PT_ERR(d, "%s mem mapping failed! (err: %i)\n", 633 adding ? "create new" : "remove old", errno); 634 } 635 } 636 } 637 638 static void xen_pt_region_add(MemoryListener *l, MemoryRegionSection *sec) 639 { 640 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState, 641 memory_listener); 642 643 memory_region_ref(sec->mr); 644 xen_pt_region_update(s, sec, true); 645 } 646 647 static void xen_pt_region_del(MemoryListener *l, MemoryRegionSection *sec) 648 { 649 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState, 650 memory_listener); 651 652 xen_pt_region_update(s, sec, false); 653 memory_region_unref(sec->mr); 654 } 655 656 static void xen_pt_io_region_add(MemoryListener *l, MemoryRegionSection *sec) 657 { 658 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState, 659 io_listener); 660 661 memory_region_ref(sec->mr); 662 xen_pt_region_update(s, sec, true); 663 } 664 665 static void xen_pt_io_region_del(MemoryListener *l, MemoryRegionSection *sec) 666 { 667 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState, 668 io_listener); 669 670 xen_pt_region_update(s, sec, false); 671 memory_region_unref(sec->mr); 672 } 673 674 static const MemoryListener xen_pt_memory_listener = { 675 .region_add = xen_pt_region_add, 676 .region_del = xen_pt_region_del, 677 .priority = 10, 678 }; 679 680 static const MemoryListener xen_pt_io_listener = { 681 .region_add = xen_pt_io_region_add, 682 .region_del = xen_pt_io_region_del, 683 .priority = 10, 684 }; 685 686 /* init */ 687 688 static int xen_pt_initfn(PCIDevice *d) 689 { 690 XenPCIPassthroughState *s = XEN_PT_DEVICE(d); 691 int rc = 0; 692 uint8_t machine_irq = 0; 693 uint16_t cmd = 0; 694 int pirq = XEN_PT_UNASSIGNED_PIRQ; 695 696 /* register real device */ 697 XEN_PT_LOG(d, "Assigning real physical device %02x:%02x.%d" 698 " to devfn %#x\n", 699 s->hostaddr.bus, s->hostaddr.slot, s->hostaddr.function, 700 s->dev.devfn); 701 702 rc = xen_host_pci_device_get(&s->real_device, 703 s->hostaddr.domain, s->hostaddr.bus, 704 s->hostaddr.slot, s->hostaddr.function); 705 if (rc) { 706 XEN_PT_ERR(d, "Failed to \"open\" the real pci device. rc: %i\n", rc); 707 return -1; 708 } 709 710 s->is_virtfn = s->real_device.is_virtfn; 711 if (s->is_virtfn) { 712 XEN_PT_LOG(d, "%04x:%02x:%02x.%d is a SR-IOV Virtual Function\n", 713 s->real_device.domain, s->real_device.bus, 714 s->real_device.dev, s->real_device.func); 715 } 716 717 /* Initialize virtualized PCI configuration (Extended 256 Bytes) */ 718 if (xen_host_pci_get_block(&s->real_device, 0, d->config, 719 PCI_CONFIG_SPACE_SIZE) == -1) { 720 xen_host_pci_device_put(&s->real_device); 721 return -1; 722 } 723 724 s->memory_listener = xen_pt_memory_listener; 725 s->io_listener = xen_pt_io_listener; 726 727 /* Handle real device's MMIO/PIO BARs */ 728 xen_pt_register_regions(s, &cmd); 729 730 /* reinitialize each config register to be emulated */ 731 if (xen_pt_config_init(s)) { 732 XEN_PT_ERR(d, "PCI Config space initialisation failed.\n"); 733 xen_host_pci_device_put(&s->real_device); 734 return -1; 735 } 736 737 /* Bind interrupt */ 738 if (!s->dev.config[PCI_INTERRUPT_PIN]) { 739 XEN_PT_LOG(d, "no pin interrupt\n"); 740 goto out; 741 } 742 743 machine_irq = s->real_device.irq; 744 rc = xc_physdev_map_pirq(xen_xc, xen_domid, machine_irq, &pirq); 745 746 if (rc < 0) { 747 XEN_PT_ERR(d, "Mapping machine irq %u to pirq %i failed, (err: %d)\n", 748 machine_irq, pirq, errno); 749 750 /* Disable PCI intx assertion (turn on bit10 of devctl) */ 751 cmd |= PCI_COMMAND_INTX_DISABLE; 752 machine_irq = 0; 753 s->machine_irq = 0; 754 } else { 755 machine_irq = pirq; 756 s->machine_irq = pirq; 757 xen_pt_mapped_machine_irq[machine_irq]++; 758 } 759 760 /* bind machine_irq to device */ 761 if (machine_irq != 0) { 762 uint8_t e_intx = xen_pt_pci_intx(s); 763 764 rc = xc_domain_bind_pt_pci_irq(xen_xc, xen_domid, machine_irq, 765 pci_bus_num(d->bus), 766 PCI_SLOT(d->devfn), 767 e_intx); 768 if (rc < 0) { 769 XEN_PT_ERR(d, "Binding of interrupt %i failed! (err: %d)\n", 770 e_intx, errno); 771 772 /* Disable PCI intx assertion (turn on bit10 of devctl) */ 773 cmd |= PCI_COMMAND_INTX_DISABLE; 774 xen_pt_mapped_machine_irq[machine_irq]--; 775 776 if (xen_pt_mapped_machine_irq[machine_irq] == 0) { 777 if (xc_physdev_unmap_pirq(xen_xc, xen_domid, machine_irq)) { 778 XEN_PT_ERR(d, "Unmapping of machine interrupt %i failed!" 779 " (err: %d)\n", machine_irq, errno); 780 } 781 } 782 s->machine_irq = 0; 783 } 784 } 785 786 out: 787 if (cmd) { 788 xen_host_pci_set_word(&s->real_device, PCI_COMMAND, 789 pci_get_word(d->config + PCI_COMMAND) | cmd); 790 } 791 792 memory_listener_register(&s->memory_listener, &s->dev.bus_master_as); 793 memory_listener_register(&s->io_listener, &address_space_io); 794 XEN_PT_LOG(d, 795 "Real physical device %02x:%02x.%d registered successfully!\n", 796 s->hostaddr.bus, s->hostaddr.slot, s->hostaddr.function); 797 798 return 0; 799 } 800 801 static void xen_pt_unregister_device(PCIDevice *d) 802 { 803 XenPCIPassthroughState *s = XEN_PT_DEVICE(d); 804 uint8_t machine_irq = s->machine_irq; 805 uint8_t intx = xen_pt_pci_intx(s); 806 int rc; 807 808 if (machine_irq) { 809 rc = xc_domain_unbind_pt_irq(xen_xc, xen_domid, machine_irq, 810 PT_IRQ_TYPE_PCI, 811 pci_bus_num(d->bus), 812 PCI_SLOT(s->dev.devfn), 813 intx, 814 0 /* isa_irq */); 815 if (rc < 0) { 816 XEN_PT_ERR(d, "unbinding of interrupt INT%c failed." 817 " (machine irq: %i, err: %d)" 818 " But bravely continuing on..\n", 819 'a' + intx, machine_irq, errno); 820 } 821 } 822 823 if (s->msi) { 824 xen_pt_msi_disable(s); 825 } 826 if (s->msix) { 827 xen_pt_msix_disable(s); 828 } 829 830 if (machine_irq) { 831 xen_pt_mapped_machine_irq[machine_irq]--; 832 833 if (xen_pt_mapped_machine_irq[machine_irq] == 0) { 834 rc = xc_physdev_unmap_pirq(xen_xc, xen_domid, machine_irq); 835 836 if (rc < 0) { 837 XEN_PT_ERR(d, "unmapping of interrupt %i failed. (err: %d)" 838 " But bravely continuing on..\n", 839 machine_irq, errno); 840 } 841 } 842 } 843 844 /* delete all emulated config registers */ 845 xen_pt_config_delete(s); 846 847 memory_listener_unregister(&s->memory_listener); 848 memory_listener_unregister(&s->io_listener); 849 850 xen_host_pci_device_put(&s->real_device); 851 } 852 853 static Property xen_pci_passthrough_properties[] = { 854 DEFINE_PROP_PCI_HOST_DEVADDR("hostaddr", XenPCIPassthroughState, hostaddr), 855 DEFINE_PROP_BOOL("permissive", XenPCIPassthroughState, permissive, false), 856 DEFINE_PROP_END_OF_LIST(), 857 }; 858 859 static void xen_pci_passthrough_class_init(ObjectClass *klass, void *data) 860 { 861 DeviceClass *dc = DEVICE_CLASS(klass); 862 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 863 864 k->init = xen_pt_initfn; 865 k->exit = xen_pt_unregister_device; 866 k->config_read = xen_pt_pci_read_config; 867 k->config_write = xen_pt_pci_write_config; 868 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 869 dc->desc = "Assign an host PCI device with Xen"; 870 dc->props = xen_pci_passthrough_properties; 871 }; 872 873 static const TypeInfo xen_pci_passthrough_info = { 874 .name = TYPE_XEN_PT_DEVICE, 875 .parent = TYPE_PCI_DEVICE, 876 .instance_size = sizeof(XenPCIPassthroughState), 877 .class_init = xen_pci_passthrough_class_init, 878 }; 879 880 static void xen_pci_passthrough_register_types(void) 881 { 882 type_register_static(&xen_pci_passthrough_info); 883 } 884 885 type_init(xen_pci_passthrough_register_types) 886