1 /* 2 * Copyright (c) 2007, Neocleus Corporation. 3 * Copyright (c) 2007, Intel Corporation. 4 * 5 * This work is licensed under the terms of the GNU GPL, version 2. See 6 * the COPYING file in the top-level directory. 7 * 8 * Alex Novik <alex@neocleus.com> 9 * Allen Kay <allen.m.kay@intel.com> 10 * Guy Zana <guy@neocleus.com> 11 * 12 * This file implements direct PCI assignment to a HVM guest 13 */ 14 15 /* 16 * Interrupt Disable policy: 17 * 18 * INTx interrupt: 19 * Initialize(register_real_device) 20 * Map INTx(xc_physdev_map_pirq): 21 * <fail> 22 * - Set real Interrupt Disable bit to '1'. 23 * - Set machine_irq and assigned_device->machine_irq to '0'. 24 * * Don't bind INTx. 25 * 26 * Bind INTx(xc_domain_bind_pt_pci_irq): 27 * <fail> 28 * - Set real Interrupt Disable bit to '1'. 29 * - Unmap INTx. 30 * - Decrement xen_pt_mapped_machine_irq[machine_irq] 31 * - Set assigned_device->machine_irq to '0'. 32 * 33 * Write to Interrupt Disable bit by guest software(xen_pt_cmd_reg_write) 34 * Write '0' 35 * - Set real bit to '0' if assigned_device->machine_irq isn't '0'. 36 * 37 * Write '1' 38 * - Set real bit to '1'. 39 * 40 * MSI interrupt: 41 * Initialize MSI register(xen_pt_msi_setup, xen_pt_msi_update) 42 * Bind MSI(xc_domain_update_msi_irq) 43 * <fail> 44 * - Unmap MSI. 45 * - Set dev->msi->pirq to '-1'. 46 * 47 * MSI-X interrupt: 48 * Initialize MSI-X register(xen_pt_msix_update_one) 49 * Bind MSI-X(xc_domain_update_msi_irq) 50 * <fail> 51 * - Unmap MSI-X. 52 * - Set entry->pirq to '-1'. 53 */ 54 55 #include <sys/ioctl.h> 56 57 #include "hw/pci/pci.h" 58 #include "hw/xen/xen.h" 59 #include "hw/xen/xen_backend.h" 60 #include "xen_pt.h" 61 #include "qemu/range.h" 62 #include "exec/address-spaces.h" 63 64 #define XEN_PT_NR_IRQS (256) 65 static uint8_t xen_pt_mapped_machine_irq[XEN_PT_NR_IRQS] = {0}; 66 67 void xen_pt_log(const PCIDevice *d, const char *f, ...) 68 { 69 va_list ap; 70 71 va_start(ap, f); 72 if (d) { 73 fprintf(stderr, "[%02x:%02x.%d] ", pci_bus_num(d->bus), 74 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn)); 75 } 76 vfprintf(stderr, f, ap); 77 va_end(ap); 78 } 79 80 /* Config Space */ 81 82 static int xen_pt_pci_config_access_check(PCIDevice *d, uint32_t addr, int len) 83 { 84 /* check offset range */ 85 if (addr >= 0xFF) { 86 XEN_PT_ERR(d, "Failed to access register with offset exceeding 0xFF. " 87 "(addr: 0x%02x, len: %d)\n", addr, len); 88 return -1; 89 } 90 91 /* check read size */ 92 if ((len != 1) && (len != 2) && (len != 4)) { 93 XEN_PT_ERR(d, "Failed to access register with invalid access length. " 94 "(addr: 0x%02x, len: %d)\n", addr, len); 95 return -1; 96 } 97 98 /* check offset alignment */ 99 if (addr & (len - 1)) { 100 XEN_PT_ERR(d, "Failed to access register with invalid access size " 101 "alignment. (addr: 0x%02x, len: %d)\n", addr, len); 102 return -1; 103 } 104 105 return 0; 106 } 107 108 int xen_pt_bar_offset_to_index(uint32_t offset) 109 { 110 int index = 0; 111 112 /* check Exp ROM BAR */ 113 if (offset == PCI_ROM_ADDRESS) { 114 return PCI_ROM_SLOT; 115 } 116 117 /* calculate BAR index */ 118 index = (offset - PCI_BASE_ADDRESS_0) >> 2; 119 if (index >= PCI_NUM_REGIONS) { 120 return -1; 121 } 122 123 return index; 124 } 125 126 static uint32_t xen_pt_pci_read_config(PCIDevice *d, uint32_t addr, int len) 127 { 128 XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, d); 129 uint32_t val = 0; 130 XenPTRegGroup *reg_grp_entry = NULL; 131 XenPTReg *reg_entry = NULL; 132 int rc = 0; 133 int emul_len = 0; 134 uint32_t find_addr = addr; 135 136 if (xen_pt_pci_config_access_check(d, addr, len)) { 137 goto exit; 138 } 139 140 /* find register group entry */ 141 reg_grp_entry = xen_pt_find_reg_grp(s, addr); 142 if (reg_grp_entry) { 143 /* check 0-Hardwired register group */ 144 if (reg_grp_entry->reg_grp->grp_type == XEN_PT_GRP_TYPE_HARDWIRED) { 145 /* no need to emulate, just return 0 */ 146 val = 0; 147 goto exit; 148 } 149 } 150 151 /* read I/O device register value */ 152 rc = xen_host_pci_get_block(&s->real_device, addr, (uint8_t *)&val, len); 153 if (rc < 0) { 154 XEN_PT_ERR(d, "pci_read_block failed. return value: %d.\n", rc); 155 memset(&val, 0xff, len); 156 } 157 158 /* just return the I/O device register value for 159 * passthrough type register group */ 160 if (reg_grp_entry == NULL) { 161 goto exit; 162 } 163 164 /* adjust the read value to appropriate CFC-CFF window */ 165 val <<= (addr & 3) << 3; 166 emul_len = len; 167 168 /* loop around the guest requested size */ 169 while (emul_len > 0) { 170 /* find register entry to be emulated */ 171 reg_entry = xen_pt_find_reg(reg_grp_entry, find_addr); 172 if (reg_entry) { 173 XenPTRegInfo *reg = reg_entry->reg; 174 uint32_t real_offset = reg_grp_entry->base_offset + reg->offset; 175 uint32_t valid_mask = 0xFFFFFFFF >> ((4 - emul_len) << 3); 176 uint8_t *ptr_val = NULL; 177 178 valid_mask <<= (find_addr - real_offset) << 3; 179 ptr_val = (uint8_t *)&val + (real_offset & 3); 180 181 /* do emulation based on register size */ 182 switch (reg->size) { 183 case 1: 184 if (reg->u.b.read) { 185 rc = reg->u.b.read(s, reg_entry, ptr_val, valid_mask); 186 } 187 break; 188 case 2: 189 if (reg->u.w.read) { 190 rc = reg->u.w.read(s, reg_entry, 191 (uint16_t *)ptr_val, valid_mask); 192 } 193 break; 194 case 4: 195 if (reg->u.dw.read) { 196 rc = reg->u.dw.read(s, reg_entry, 197 (uint32_t *)ptr_val, valid_mask); 198 } 199 break; 200 } 201 202 if (rc < 0) { 203 xen_shutdown_fatal_error("Internal error: Invalid read " 204 "emulation. (%s, rc: %d)\n", 205 __func__, rc); 206 return 0; 207 } 208 209 /* calculate next address to find */ 210 emul_len -= reg->size; 211 if (emul_len > 0) { 212 find_addr = real_offset + reg->size; 213 } 214 } else { 215 /* nothing to do with passthrough type register, 216 * continue to find next byte */ 217 emul_len--; 218 find_addr++; 219 } 220 } 221 222 /* need to shift back before returning them to pci bus emulator */ 223 val >>= ((addr & 3) << 3); 224 225 exit: 226 XEN_PT_LOG_CONFIG(d, addr, val, len); 227 return val; 228 } 229 230 static void xen_pt_pci_write_config(PCIDevice *d, uint32_t addr, 231 uint32_t val, int len) 232 { 233 XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, d); 234 int index = 0; 235 XenPTRegGroup *reg_grp_entry = NULL; 236 int rc = 0; 237 uint32_t read_val = 0; 238 int emul_len = 0; 239 XenPTReg *reg_entry = NULL; 240 uint32_t find_addr = addr; 241 XenPTRegInfo *reg = NULL; 242 243 if (xen_pt_pci_config_access_check(d, addr, len)) { 244 return; 245 } 246 247 XEN_PT_LOG_CONFIG(d, addr, val, len); 248 249 /* check unused BAR register */ 250 index = xen_pt_bar_offset_to_index(addr); 251 if ((index >= 0) && (val > 0 && val < XEN_PT_BAR_ALLF) && 252 (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED)) { 253 XEN_PT_WARN(d, "Guest attempt to set address to unused Base Address " 254 "Register. (addr: 0x%02x, len: %d)\n", addr, len); 255 } 256 257 /* find register group entry */ 258 reg_grp_entry = xen_pt_find_reg_grp(s, addr); 259 if (reg_grp_entry) { 260 /* check 0-Hardwired register group */ 261 if (reg_grp_entry->reg_grp->grp_type == XEN_PT_GRP_TYPE_HARDWIRED) { 262 /* ignore silently */ 263 XEN_PT_WARN(d, "Access to 0-Hardwired register. " 264 "(addr: 0x%02x, len: %d)\n", addr, len); 265 return; 266 } 267 } 268 269 rc = xen_host_pci_get_block(&s->real_device, addr, 270 (uint8_t *)&read_val, len); 271 if (rc < 0) { 272 XEN_PT_ERR(d, "pci_read_block failed. return value: %d.\n", rc); 273 memset(&read_val, 0xff, len); 274 } 275 276 /* pass directly to the real device for passthrough type register group */ 277 if (reg_grp_entry == NULL) { 278 goto out; 279 } 280 281 memory_region_transaction_begin(); 282 pci_default_write_config(d, addr, val, len); 283 284 /* adjust the read and write value to appropriate CFC-CFF window */ 285 read_val <<= (addr & 3) << 3; 286 val <<= (addr & 3) << 3; 287 emul_len = len; 288 289 /* loop around the guest requested size */ 290 while (emul_len > 0) { 291 /* find register entry to be emulated */ 292 reg_entry = xen_pt_find_reg(reg_grp_entry, find_addr); 293 if (reg_entry) { 294 reg = reg_entry->reg; 295 uint32_t real_offset = reg_grp_entry->base_offset + reg->offset; 296 uint32_t valid_mask = 0xFFFFFFFF >> ((4 - emul_len) << 3); 297 uint8_t *ptr_val = NULL; 298 299 valid_mask <<= (find_addr - real_offset) << 3; 300 ptr_val = (uint8_t *)&val + (real_offset & 3); 301 302 /* do emulation based on register size */ 303 switch (reg->size) { 304 case 1: 305 if (reg->u.b.write) { 306 rc = reg->u.b.write(s, reg_entry, ptr_val, 307 read_val >> ((real_offset & 3) << 3), 308 valid_mask); 309 } 310 break; 311 case 2: 312 if (reg->u.w.write) { 313 rc = reg->u.w.write(s, reg_entry, (uint16_t *)ptr_val, 314 (read_val >> ((real_offset & 3) << 3)), 315 valid_mask); 316 } 317 break; 318 case 4: 319 if (reg->u.dw.write) { 320 rc = reg->u.dw.write(s, reg_entry, (uint32_t *)ptr_val, 321 (read_val >> ((real_offset & 3) << 3)), 322 valid_mask); 323 } 324 break; 325 } 326 327 if (rc < 0) { 328 xen_shutdown_fatal_error("Internal error: Invalid write" 329 " emulation. (%s, rc: %d)\n", 330 __func__, rc); 331 return; 332 } 333 334 /* calculate next address to find */ 335 emul_len -= reg->size; 336 if (emul_len > 0) { 337 find_addr = real_offset + reg->size; 338 } 339 } else { 340 /* nothing to do with passthrough type register, 341 * continue to find next byte */ 342 emul_len--; 343 find_addr++; 344 } 345 } 346 347 /* need to shift back before passing them to xen_host_pci_device */ 348 val >>= (addr & 3) << 3; 349 350 memory_region_transaction_commit(); 351 352 out: 353 if (!(reg && reg->no_wb)) { 354 /* unknown regs are passed through */ 355 rc = xen_host_pci_set_block(&s->real_device, addr, 356 (uint8_t *)&val, len); 357 358 if (rc < 0) { 359 XEN_PT_ERR(d, "pci_write_block failed. return value: %d.\n", rc); 360 } 361 } 362 } 363 364 /* register regions */ 365 366 static uint64_t xen_pt_bar_read(void *o, hwaddr addr, 367 unsigned size) 368 { 369 PCIDevice *d = o; 370 /* if this function is called, that probably means that there is a 371 * misconfiguration of the IOMMU. */ 372 XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"TARGET_FMT_plx"\n", 373 addr); 374 return 0; 375 } 376 static void xen_pt_bar_write(void *o, hwaddr addr, uint64_t val, 377 unsigned size) 378 { 379 PCIDevice *d = o; 380 /* Same comment as xen_pt_bar_read function */ 381 XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"TARGET_FMT_plx"\n", 382 addr); 383 } 384 385 static const MemoryRegionOps ops = { 386 .endianness = DEVICE_NATIVE_ENDIAN, 387 .read = xen_pt_bar_read, 388 .write = xen_pt_bar_write, 389 }; 390 391 static int xen_pt_register_regions(XenPCIPassthroughState *s) 392 { 393 int i = 0; 394 XenHostPCIDevice *d = &s->real_device; 395 396 /* Register PIO/MMIO BARs */ 397 for (i = 0; i < PCI_ROM_SLOT; i++) { 398 XenHostPCIIORegion *r = &d->io_regions[i]; 399 uint8_t type; 400 401 if (r->base_addr == 0 || r->size == 0) { 402 continue; 403 } 404 405 s->bases[i].access.u = r->base_addr; 406 407 if (r->type & XEN_HOST_PCI_REGION_TYPE_IO) { 408 type = PCI_BASE_ADDRESS_SPACE_IO; 409 } else { 410 type = PCI_BASE_ADDRESS_SPACE_MEMORY; 411 if (r->type & XEN_HOST_PCI_REGION_TYPE_PREFETCH) { 412 type |= PCI_BASE_ADDRESS_MEM_PREFETCH; 413 } 414 if (r->type & XEN_HOST_PCI_REGION_TYPE_MEM_64) { 415 type |= PCI_BASE_ADDRESS_MEM_TYPE_64; 416 } 417 } 418 419 memory_region_init_io(&s->bar[i], OBJECT(s), &ops, &s->dev, 420 "xen-pci-pt-bar", r->size); 421 pci_register_bar(&s->dev, i, type, &s->bar[i]); 422 423 XEN_PT_LOG(&s->dev, "IO region %i registered (size=0x%08"PRIx64 424 " base_addr=0x%08"PRIx64" type: %#x)\n", 425 i, r->size, r->base_addr, type); 426 } 427 428 /* Register expansion ROM address */ 429 if (d->rom.base_addr && d->rom.size) { 430 uint32_t bar_data = 0; 431 432 /* Re-set BAR reported by OS, otherwise ROM can't be read. */ 433 if (xen_host_pci_get_long(d, PCI_ROM_ADDRESS, &bar_data)) { 434 return 0; 435 } 436 if ((bar_data & PCI_ROM_ADDRESS_MASK) == 0) { 437 bar_data |= d->rom.base_addr & PCI_ROM_ADDRESS_MASK; 438 xen_host_pci_set_long(d, PCI_ROM_ADDRESS, bar_data); 439 } 440 441 s->bases[PCI_ROM_SLOT].access.maddr = d->rom.base_addr; 442 443 memory_region_init_io(&s->rom, OBJECT(s), &ops, &s->dev, 444 "xen-pci-pt-rom", d->rom.size); 445 pci_register_bar(&s->dev, PCI_ROM_SLOT, PCI_BASE_ADDRESS_MEM_PREFETCH, 446 &s->rom); 447 448 XEN_PT_LOG(&s->dev, "Expansion ROM registered (size=0x%08"PRIx64 449 " base_addr=0x%08"PRIx64")\n", 450 d->rom.size, d->rom.base_addr); 451 } 452 453 return 0; 454 } 455 456 /* region mapping */ 457 458 static int xen_pt_bar_from_region(XenPCIPassthroughState *s, MemoryRegion *mr) 459 { 460 int i = 0; 461 462 for (i = 0; i < PCI_NUM_REGIONS - 1; i++) { 463 if (mr == &s->bar[i]) { 464 return i; 465 } 466 } 467 if (mr == &s->rom) { 468 return PCI_ROM_SLOT; 469 } 470 return -1; 471 } 472 473 /* 474 * This function checks if an io_region overlaps an io_region from another 475 * device. The io_region to check is provided with (addr, size and type) 476 * A callback can be provided and will be called for every region that is 477 * overlapped. 478 * The return value indicates if the region is overlappsed */ 479 struct CheckBarArgs { 480 XenPCIPassthroughState *s; 481 pcibus_t addr; 482 pcibus_t size; 483 uint8_t type; 484 bool rc; 485 }; 486 static void xen_pt_check_bar_overlap(PCIBus *bus, PCIDevice *d, void *opaque) 487 { 488 struct CheckBarArgs *arg = opaque; 489 XenPCIPassthroughState *s = arg->s; 490 uint8_t type = arg->type; 491 int i; 492 493 if (d->devfn == s->dev.devfn) { 494 return; 495 } 496 497 /* xxx: This ignores bridges. */ 498 for (i = 0; i < PCI_NUM_REGIONS; i++) { 499 const PCIIORegion *r = &d->io_regions[i]; 500 501 if (!r->size) { 502 continue; 503 } 504 if ((type & PCI_BASE_ADDRESS_SPACE_IO) 505 != (r->type & PCI_BASE_ADDRESS_SPACE_IO)) { 506 continue; 507 } 508 509 if (ranges_overlap(arg->addr, arg->size, r->addr, r->size)) { 510 XEN_PT_WARN(&s->dev, 511 "Overlapped to device [%02x:%02x.%d] Region: %i" 512 " (addr: %#"FMT_PCIBUS", len: %#"FMT_PCIBUS")\n", 513 pci_bus_num(bus), PCI_SLOT(d->devfn), 514 PCI_FUNC(d->devfn), i, r->addr, r->size); 515 arg->rc = true; 516 } 517 } 518 } 519 520 static void xen_pt_region_update(XenPCIPassthroughState *s, 521 MemoryRegionSection *sec, bool adding) 522 { 523 PCIDevice *d = &s->dev; 524 MemoryRegion *mr = sec->mr; 525 int bar = -1; 526 int rc; 527 int op = adding ? DPCI_ADD_MAPPING : DPCI_REMOVE_MAPPING; 528 struct CheckBarArgs args = { 529 .s = s, 530 .addr = sec->offset_within_address_space, 531 .size = int128_get64(sec->size), 532 .rc = false, 533 }; 534 535 bar = xen_pt_bar_from_region(s, mr); 536 if (bar == -1 && (!s->msix || &s->msix->mmio != mr)) { 537 return; 538 } 539 540 if (s->msix && &s->msix->mmio == mr) { 541 if (adding) { 542 s->msix->mmio_base_addr = sec->offset_within_address_space; 543 rc = xen_pt_msix_update_remap(s, s->msix->bar_index); 544 } 545 return; 546 } 547 548 args.type = d->io_regions[bar].type; 549 pci_for_each_device(d->bus, pci_bus_num(d->bus), 550 xen_pt_check_bar_overlap, &args); 551 if (args.rc) { 552 XEN_PT_WARN(d, "Region: %d (addr: %#"FMT_PCIBUS 553 ", len: %#"FMT_PCIBUS") is overlapped.\n", 554 bar, sec->offset_within_address_space, 555 int128_get64(sec->size)); 556 } 557 558 if (d->io_regions[bar].type & PCI_BASE_ADDRESS_SPACE_IO) { 559 uint32_t guest_port = sec->offset_within_address_space; 560 uint32_t machine_port = s->bases[bar].access.pio_base; 561 uint32_t size = int128_get64(sec->size); 562 rc = xc_domain_ioport_mapping(xen_xc, xen_domid, 563 guest_port, machine_port, size, 564 op); 565 if (rc) { 566 XEN_PT_ERR(d, "%s ioport mapping failed! (rc: %i)\n", 567 adding ? "create new" : "remove old", rc); 568 } 569 } else { 570 pcibus_t guest_addr = sec->offset_within_address_space; 571 pcibus_t machine_addr = s->bases[bar].access.maddr 572 + sec->offset_within_region; 573 pcibus_t size = int128_get64(sec->size); 574 rc = xc_domain_memory_mapping(xen_xc, xen_domid, 575 XEN_PFN(guest_addr + XC_PAGE_SIZE - 1), 576 XEN_PFN(machine_addr + XC_PAGE_SIZE - 1), 577 XEN_PFN(size + XC_PAGE_SIZE - 1), 578 op); 579 if (rc) { 580 XEN_PT_ERR(d, "%s mem mapping failed! (rc: %i)\n", 581 adding ? "create new" : "remove old", rc); 582 } 583 } 584 } 585 586 static void xen_pt_region_add(MemoryListener *l, MemoryRegionSection *sec) 587 { 588 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState, 589 memory_listener); 590 591 memory_region_ref(sec->mr); 592 xen_pt_region_update(s, sec, true); 593 } 594 595 static void xen_pt_region_del(MemoryListener *l, MemoryRegionSection *sec) 596 { 597 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState, 598 memory_listener); 599 600 xen_pt_region_update(s, sec, false); 601 memory_region_unref(sec->mr); 602 } 603 604 static void xen_pt_io_region_add(MemoryListener *l, MemoryRegionSection *sec) 605 { 606 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState, 607 io_listener); 608 609 memory_region_ref(sec->mr); 610 xen_pt_region_update(s, sec, true); 611 } 612 613 static void xen_pt_io_region_del(MemoryListener *l, MemoryRegionSection *sec) 614 { 615 XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState, 616 io_listener); 617 618 xen_pt_region_update(s, sec, false); 619 memory_region_unref(sec->mr); 620 } 621 622 static const MemoryListener xen_pt_memory_listener = { 623 .region_add = xen_pt_region_add, 624 .region_del = xen_pt_region_del, 625 .priority = 10, 626 }; 627 628 static const MemoryListener xen_pt_io_listener = { 629 .region_add = xen_pt_io_region_add, 630 .region_del = xen_pt_io_region_del, 631 .priority = 10, 632 }; 633 634 /* init */ 635 636 static int xen_pt_initfn(PCIDevice *d) 637 { 638 XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, d); 639 int rc = 0; 640 uint8_t machine_irq = 0; 641 int pirq = XEN_PT_UNASSIGNED_PIRQ; 642 643 /* register real device */ 644 XEN_PT_LOG(d, "Assigning real physical device %02x:%02x.%d" 645 " to devfn %#x\n", 646 s->hostaddr.bus, s->hostaddr.slot, s->hostaddr.function, 647 s->dev.devfn); 648 649 rc = xen_host_pci_device_get(&s->real_device, 650 s->hostaddr.domain, s->hostaddr.bus, 651 s->hostaddr.slot, s->hostaddr.function); 652 if (rc) { 653 XEN_PT_ERR(d, "Failed to \"open\" the real pci device. rc: %i\n", rc); 654 return -1; 655 } 656 657 s->is_virtfn = s->real_device.is_virtfn; 658 if (s->is_virtfn) { 659 XEN_PT_LOG(d, "%04x:%02x:%02x.%d is a SR-IOV Virtual Function\n", 660 s->real_device.domain, s->real_device.bus, 661 s->real_device.dev, s->real_device.func); 662 } 663 664 /* Initialize virtualized PCI configuration (Extended 256 Bytes) */ 665 if (xen_host_pci_get_block(&s->real_device, 0, d->config, 666 PCI_CONFIG_SPACE_SIZE) == -1) { 667 xen_host_pci_device_put(&s->real_device); 668 return -1; 669 } 670 671 s->memory_listener = xen_pt_memory_listener; 672 s->io_listener = xen_pt_io_listener; 673 674 /* Handle real device's MMIO/PIO BARs */ 675 xen_pt_register_regions(s); 676 677 /* reinitialize each config register to be emulated */ 678 if (xen_pt_config_init(s)) { 679 XEN_PT_ERR(d, "PCI Config space initialisation failed.\n"); 680 xen_host_pci_device_put(&s->real_device); 681 return -1; 682 } 683 684 /* Bind interrupt */ 685 if (!s->dev.config[PCI_INTERRUPT_PIN]) { 686 XEN_PT_LOG(d, "no pin interrupt\n"); 687 goto out; 688 } 689 690 machine_irq = s->real_device.irq; 691 rc = xc_physdev_map_pirq(xen_xc, xen_domid, machine_irq, &pirq); 692 693 if (rc < 0) { 694 XEN_PT_ERR(d, "Mapping machine irq %u to pirq %i failed, (rc: %d)\n", 695 machine_irq, pirq, rc); 696 697 /* Disable PCI intx assertion (turn on bit10 of devctl) */ 698 xen_host_pci_set_word(&s->real_device, 699 PCI_COMMAND, 700 pci_get_word(s->dev.config + PCI_COMMAND) 701 | PCI_COMMAND_INTX_DISABLE); 702 machine_irq = 0; 703 s->machine_irq = 0; 704 } else { 705 machine_irq = pirq; 706 s->machine_irq = pirq; 707 xen_pt_mapped_machine_irq[machine_irq]++; 708 } 709 710 /* bind machine_irq to device */ 711 if (machine_irq != 0) { 712 uint8_t e_intx = xen_pt_pci_intx(s); 713 714 rc = xc_domain_bind_pt_pci_irq(xen_xc, xen_domid, machine_irq, 715 pci_bus_num(d->bus), 716 PCI_SLOT(d->devfn), 717 e_intx); 718 if (rc < 0) { 719 XEN_PT_ERR(d, "Binding of interrupt %i failed! (rc: %d)\n", 720 e_intx, rc); 721 722 /* Disable PCI intx assertion (turn on bit10 of devctl) */ 723 xen_host_pci_set_word(&s->real_device, PCI_COMMAND, 724 *(uint16_t *)(&s->dev.config[PCI_COMMAND]) 725 | PCI_COMMAND_INTX_DISABLE); 726 xen_pt_mapped_machine_irq[machine_irq]--; 727 728 if (xen_pt_mapped_machine_irq[machine_irq] == 0) { 729 if (xc_physdev_unmap_pirq(xen_xc, xen_domid, machine_irq)) { 730 XEN_PT_ERR(d, "Unmapping of machine interrupt %i failed!" 731 " (rc: %d)\n", machine_irq, rc); 732 } 733 } 734 s->machine_irq = 0; 735 } 736 } 737 738 out: 739 memory_listener_register(&s->memory_listener, &s->dev.bus_master_as); 740 memory_listener_register(&s->io_listener, &address_space_io); 741 XEN_PT_LOG(d, 742 "Real physical device %02x:%02x.%d registered successfully!\n", 743 s->hostaddr.bus, s->hostaddr.slot, s->hostaddr.function); 744 745 return 0; 746 } 747 748 static void xen_pt_unregister_device(PCIDevice *d) 749 { 750 XenPCIPassthroughState *s = DO_UPCAST(XenPCIPassthroughState, dev, d); 751 uint8_t machine_irq = s->machine_irq; 752 uint8_t intx = xen_pt_pci_intx(s); 753 int rc; 754 755 if (machine_irq) { 756 rc = xc_domain_unbind_pt_irq(xen_xc, xen_domid, machine_irq, 757 PT_IRQ_TYPE_PCI, 758 pci_bus_num(d->bus), 759 PCI_SLOT(s->dev.devfn), 760 intx, 761 0 /* isa_irq */); 762 if (rc < 0) { 763 XEN_PT_ERR(d, "unbinding of interrupt INT%c failed." 764 " (machine irq: %i, rc: %d)" 765 " But bravely continuing on..\n", 766 'a' + intx, machine_irq, rc); 767 } 768 } 769 770 if (s->msi) { 771 xen_pt_msi_disable(s); 772 } 773 if (s->msix) { 774 xen_pt_msix_disable(s); 775 } 776 777 if (machine_irq) { 778 xen_pt_mapped_machine_irq[machine_irq]--; 779 780 if (xen_pt_mapped_machine_irq[machine_irq] == 0) { 781 rc = xc_physdev_unmap_pirq(xen_xc, xen_domid, machine_irq); 782 783 if (rc < 0) { 784 XEN_PT_ERR(d, "unmapping of interrupt %i failed. (rc: %d)" 785 " But bravely continuing on..\n", 786 machine_irq, rc); 787 } 788 } 789 } 790 791 /* delete all emulated config registers */ 792 xen_pt_config_delete(s); 793 794 memory_listener_unregister(&s->memory_listener); 795 memory_listener_unregister(&s->io_listener); 796 797 xen_host_pci_device_put(&s->real_device); 798 } 799 800 static Property xen_pci_passthrough_properties[] = { 801 DEFINE_PROP_PCI_HOST_DEVADDR("hostaddr", XenPCIPassthroughState, hostaddr), 802 DEFINE_PROP_END_OF_LIST(), 803 }; 804 805 static void xen_pci_passthrough_class_init(ObjectClass *klass, void *data) 806 { 807 DeviceClass *dc = DEVICE_CLASS(klass); 808 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 809 810 k->init = xen_pt_initfn; 811 k->exit = xen_pt_unregister_device; 812 k->config_read = xen_pt_pci_read_config; 813 k->config_write = xen_pt_pci_write_config; 814 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 815 dc->desc = "Assign an host PCI device with Xen"; 816 dc->props = xen_pci_passthrough_properties; 817 }; 818 819 static const TypeInfo xen_pci_passthrough_info = { 820 .name = "xen-pci-passthrough", 821 .parent = TYPE_PCI_DEVICE, 822 .instance_size = sizeof(XenPCIPassthroughState), 823 .class_init = xen_pci_passthrough_class_init, 824 }; 825 826 static void xen_pci_passthrough_register_types(void) 827 { 828 type_register_static(&xen_pci_passthrough_info); 829 } 830 831 type_init(xen_pci_passthrough_register_types) 832