1258b2a40SEdgar E. Iglesias /* 2258b2a40SEdgar E. Iglesias * QEMU Xen PVH machine - common code. 3258b2a40SEdgar E. Iglesias * 4258b2a40SEdgar E. Iglesias * Copyright (c) 2024 Advanced Micro Devices, Inc. 5258b2a40SEdgar E. Iglesias * 6258b2a40SEdgar E. Iglesias * SPDX-License-Identifier: GPL-2.0-or-later 7258b2a40SEdgar E. Iglesias */ 8258b2a40SEdgar E. Iglesias 9258b2a40SEdgar E. Iglesias #include "qemu/osdep.h" 10258b2a40SEdgar E. Iglesias #include "qemu/error-report.h" 11258b2a40SEdgar E. Iglesias #include "qapi/error.h" 12258b2a40SEdgar E. Iglesias #include "qapi/visitor.h" 13258b2a40SEdgar E. Iglesias #include "hw/boards.h" 14258b2a40SEdgar E. Iglesias #include "hw/irq.h" 15258b2a40SEdgar E. Iglesias #include "hw/sysbus.h" 16258b2a40SEdgar E. Iglesias #include "sysemu/sysemu.h" 17258b2a40SEdgar E. Iglesias #include "sysemu/tpm.h" 18258b2a40SEdgar E. Iglesias #include "sysemu/tpm_backend.h" 19258b2a40SEdgar E. Iglesias #include "hw/xen/xen-pvh-common.h" 20258b2a40SEdgar E. Iglesias #include "trace.h" 21258b2a40SEdgar E. Iglesias 22258b2a40SEdgar E. Iglesias static const MemoryListener xen_memory_listener = { 23258b2a40SEdgar E. Iglesias .region_add = xen_region_add, 24258b2a40SEdgar E. Iglesias .region_del = xen_region_del, 25258b2a40SEdgar E. Iglesias .log_start = NULL, 26258b2a40SEdgar E. Iglesias .log_stop = NULL, 27258b2a40SEdgar E. Iglesias .log_sync = NULL, 28258b2a40SEdgar E. Iglesias .log_global_start = NULL, 29258b2a40SEdgar E. Iglesias .log_global_stop = NULL, 30258b2a40SEdgar E. Iglesias .priority = MEMORY_LISTENER_PRIORITY_ACCEL, 31258b2a40SEdgar E. Iglesias }; 32258b2a40SEdgar E. Iglesias 33258b2a40SEdgar E. Iglesias static void xen_pvh_init_ram(XenPVHMachineState *s, 34258b2a40SEdgar E. Iglesias MemoryRegion *sysmem) 35258b2a40SEdgar E. Iglesias { 36258b2a40SEdgar E. Iglesias MachineState *ms = MACHINE(s); 37258b2a40SEdgar E. Iglesias ram_addr_t block_len, ram_size[2]; 38258b2a40SEdgar E. Iglesias 39258b2a40SEdgar E. Iglesias if (ms->ram_size <= s->cfg.ram_low.size) { 40258b2a40SEdgar E. Iglesias ram_size[0] = ms->ram_size; 41258b2a40SEdgar E. Iglesias ram_size[1] = 0; 42258b2a40SEdgar E. Iglesias block_len = s->cfg.ram_low.base + ram_size[0]; 43258b2a40SEdgar E. Iglesias } else { 44258b2a40SEdgar E. Iglesias ram_size[0] = s->cfg.ram_low.size; 45258b2a40SEdgar E. Iglesias ram_size[1] = ms->ram_size - s->cfg.ram_low.size; 46258b2a40SEdgar E. Iglesias block_len = s->cfg.ram_high.base + ram_size[1]; 47258b2a40SEdgar E. Iglesias } 48258b2a40SEdgar E. Iglesias 49258b2a40SEdgar E. Iglesias memory_region_init_ram(&xen_memory, NULL, "xen.ram", block_len, 50258b2a40SEdgar E. Iglesias &error_fatal); 51258b2a40SEdgar E. Iglesias 52258b2a40SEdgar E. Iglesias memory_region_init_alias(&s->ram.low, NULL, "xen.ram.lo", &xen_memory, 53258b2a40SEdgar E. Iglesias s->cfg.ram_low.base, ram_size[0]); 54258b2a40SEdgar E. Iglesias memory_region_add_subregion(sysmem, s->cfg.ram_low.base, &s->ram.low); 55258b2a40SEdgar E. Iglesias if (ram_size[1] > 0) { 56258b2a40SEdgar E. Iglesias memory_region_init_alias(&s->ram.high, NULL, "xen.ram.hi", &xen_memory, 57258b2a40SEdgar E. Iglesias s->cfg.ram_high.base, ram_size[1]); 58258b2a40SEdgar E. Iglesias memory_region_add_subregion(sysmem, s->cfg.ram_high.base, &s->ram.high); 59258b2a40SEdgar E. Iglesias } 60258b2a40SEdgar E. Iglesias 61258b2a40SEdgar E. Iglesias /* Setup support for grants. */ 62258b2a40SEdgar E. Iglesias memory_region_init_ram(&xen_grants, NULL, "xen.grants", block_len, 63258b2a40SEdgar E. Iglesias &error_fatal); 64258b2a40SEdgar E. Iglesias memory_region_add_subregion(sysmem, XEN_GRANT_ADDR_OFF, &xen_grants); 65258b2a40SEdgar E. Iglesias } 66258b2a40SEdgar E. Iglesias 67258b2a40SEdgar E. Iglesias static void xen_set_irq(void *opaque, int irq, int level) 68258b2a40SEdgar E. Iglesias { 69258b2a40SEdgar E. Iglesias if (xendevicemodel_set_irq_level(xen_dmod, xen_domid, irq, level)) { 70258b2a40SEdgar E. Iglesias error_report("xendevicemodel_set_irq_level failed"); 71258b2a40SEdgar E. Iglesias } 72258b2a40SEdgar E. Iglesias } 73258b2a40SEdgar E. Iglesias 74258b2a40SEdgar E. Iglesias static void xen_create_virtio_mmio_devices(XenPVHMachineState *s) 75258b2a40SEdgar E. Iglesias { 76258b2a40SEdgar E. Iglesias int i; 77258b2a40SEdgar E. Iglesias 78692ec933SEdgar E. Iglesias /* 79692ec933SEdgar E. Iglesias * We create the transports in reverse order. Since qbus_realize() 80692ec933SEdgar E. Iglesias * prepends (not appends) new child buses, the decrementing loop below will 81692ec933SEdgar E. Iglesias * create a list of virtio-mmio buses with increasing base addresses. 82692ec933SEdgar E. Iglesias * 83692ec933SEdgar E. Iglesias * When a -device option is processed from the command line, 84692ec933SEdgar E. Iglesias * qbus_find_recursive() picks the next free virtio-mmio bus in forwards 85692ec933SEdgar E. Iglesias * order. 86692ec933SEdgar E. Iglesias * 87692ec933SEdgar E. Iglesias * This is what the Xen tools expect. 88692ec933SEdgar E. Iglesias */ 89692ec933SEdgar E. Iglesias for (i = s->cfg.virtio_mmio_num - 1; i >= 0; i--) { 90258b2a40SEdgar E. Iglesias hwaddr base = s->cfg.virtio_mmio.base + i * s->cfg.virtio_mmio.size; 91258b2a40SEdgar E. Iglesias qemu_irq irq = qemu_allocate_irq(xen_set_irq, NULL, 92258b2a40SEdgar E. Iglesias s->cfg.virtio_mmio_irq_base + i); 93258b2a40SEdgar E. Iglesias 94258b2a40SEdgar E. Iglesias sysbus_create_simple("virtio-mmio", base, irq); 95258b2a40SEdgar E. Iglesias 96258b2a40SEdgar E. Iglesias trace_xen_create_virtio_mmio_devices(i, 97258b2a40SEdgar E. Iglesias s->cfg.virtio_mmio_irq_base + i, 98258b2a40SEdgar E. Iglesias base); 99258b2a40SEdgar E. Iglesias } 100258b2a40SEdgar E. Iglesias } 101258b2a40SEdgar E. Iglesias 102258b2a40SEdgar E. Iglesias #ifdef CONFIG_TPM 103258b2a40SEdgar E. Iglesias static void xen_enable_tpm(XenPVHMachineState *s) 104258b2a40SEdgar E. Iglesias { 105258b2a40SEdgar E. Iglesias Error *errp = NULL; 106258b2a40SEdgar E. Iglesias DeviceState *dev; 107258b2a40SEdgar E. Iglesias SysBusDevice *busdev; 108258b2a40SEdgar E. Iglesias 109258b2a40SEdgar E. Iglesias TPMBackend *be = qemu_find_tpm_be("tpm0"); 110258b2a40SEdgar E. Iglesias if (be == NULL) { 111258b2a40SEdgar E. Iglesias error_report("Couldn't find tmp0 backend"); 112258b2a40SEdgar E. Iglesias return; 113258b2a40SEdgar E. Iglesias } 114258b2a40SEdgar E. Iglesias dev = qdev_new(TYPE_TPM_TIS_SYSBUS); 115258b2a40SEdgar E. Iglesias object_property_set_link(OBJECT(dev), "tpmdev", OBJECT(be), &errp); 116258b2a40SEdgar E. Iglesias object_property_set_str(OBJECT(dev), "tpmdev", be->id, &errp); 117258b2a40SEdgar E. Iglesias busdev = SYS_BUS_DEVICE(dev); 118258b2a40SEdgar E. Iglesias sysbus_realize_and_unref(busdev, &error_fatal); 119258b2a40SEdgar E. Iglesias sysbus_mmio_map(busdev, 0, s->cfg.tpm.base); 120258b2a40SEdgar E. Iglesias 121258b2a40SEdgar E. Iglesias trace_xen_enable_tpm(s->cfg.tpm.base); 122258b2a40SEdgar E. Iglesias } 123258b2a40SEdgar E. Iglesias #endif 124258b2a40SEdgar E. Iglesias 125f22e598aSEdgar E. Iglesias /* 126f22e598aSEdgar E. Iglesias * We use the GPEX PCIe controller with its internal INTX PCI interrupt 127f22e598aSEdgar E. Iglesias * swizzling. This swizzling is emulated in QEMU and routes all INTX 128f22e598aSEdgar E. Iglesias * interrupts from endpoints down to only 4 INTX interrupts. 129f22e598aSEdgar E. Iglesias * See include/hw/pci/pci.h : pci_swizzle() 130f22e598aSEdgar E. Iglesias */ 131f22e598aSEdgar E. Iglesias static inline void xenpvh_gpex_init(XenPVHMachineState *s, 132f22e598aSEdgar E. Iglesias XenPVHMachineClass *xpc, 133f22e598aSEdgar E. Iglesias MemoryRegion *sysmem) 134f22e598aSEdgar E. Iglesias { 135f22e598aSEdgar E. Iglesias MemoryRegion *ecam_reg; 136f22e598aSEdgar E. Iglesias MemoryRegion *mmio_reg; 137f22e598aSEdgar E. Iglesias DeviceState *dev; 138f22e598aSEdgar E. Iglesias int i; 139f22e598aSEdgar E. Iglesias 140f22e598aSEdgar E. Iglesias object_initialize_child(OBJECT(s), "gpex", &s->pci.gpex, 141f22e598aSEdgar E. Iglesias TYPE_GPEX_HOST); 142f22e598aSEdgar E. Iglesias dev = DEVICE(&s->pci.gpex); 143f22e598aSEdgar E. Iglesias sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 144f22e598aSEdgar E. Iglesias 145f22e598aSEdgar E. Iglesias ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 146f22e598aSEdgar E. Iglesias memory_region_add_subregion(sysmem, s->cfg.pci_ecam.base, ecam_reg); 147f22e598aSEdgar E. Iglesias 148f22e598aSEdgar E. Iglesias mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 149f22e598aSEdgar E. Iglesias 150f22e598aSEdgar E. Iglesias if (s->cfg.pci_mmio.size) { 151f22e598aSEdgar E. Iglesias memory_region_init_alias(&s->pci.mmio_alias, OBJECT(dev), "pcie-mmio", 152f22e598aSEdgar E. Iglesias mmio_reg, 153f22e598aSEdgar E. Iglesias s->cfg.pci_mmio.base, s->cfg.pci_mmio.size); 154f22e598aSEdgar E. Iglesias memory_region_add_subregion(sysmem, s->cfg.pci_mmio.base, 155f22e598aSEdgar E. Iglesias &s->pci.mmio_alias); 156f22e598aSEdgar E. Iglesias } 157f22e598aSEdgar E. Iglesias 158f22e598aSEdgar E. Iglesias if (s->cfg.pci_mmio_high.size) { 159f22e598aSEdgar E. Iglesias memory_region_init_alias(&s->pci.mmio_high_alias, OBJECT(dev), 160f22e598aSEdgar E. Iglesias "pcie-mmio-high", 161f22e598aSEdgar E. Iglesias mmio_reg, s->cfg.pci_mmio_high.base, s->cfg.pci_mmio_high.size); 162f22e598aSEdgar E. Iglesias memory_region_add_subregion(sysmem, s->cfg.pci_mmio_high.base, 163f22e598aSEdgar E. Iglesias &s->pci.mmio_high_alias); 164f22e598aSEdgar E. Iglesias } 165f22e598aSEdgar E. Iglesias 166f22e598aSEdgar E. Iglesias /* 167f22e598aSEdgar E. Iglesias * PVH implementations with PCI enabled must provide set_pci_intx_irq() 168f22e598aSEdgar E. Iglesias * and optionally an implementation of set_pci_link_route(). 169f22e598aSEdgar E. Iglesias */ 170f22e598aSEdgar E. Iglesias assert(xpc->set_pci_intx_irq); 171f22e598aSEdgar E. Iglesias 172f22e598aSEdgar E. Iglesias for (i = 0; i < GPEX_NUM_IRQS; i++) { 173f22e598aSEdgar E. Iglesias qemu_irq irq = qemu_allocate_irq(xpc->set_pci_intx_irq, s, i); 174f22e598aSEdgar E. Iglesias 175f22e598aSEdgar E. Iglesias sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 176f22e598aSEdgar E. Iglesias gpex_set_irq_num(GPEX_HOST(dev), i, s->cfg.pci_intx_irq_base + i); 177f22e598aSEdgar E. Iglesias if (xpc->set_pci_link_route) { 178f22e598aSEdgar E. Iglesias xpc->set_pci_link_route(i, s->cfg.pci_intx_irq_base + i); 179f22e598aSEdgar E. Iglesias } 180f22e598aSEdgar E. Iglesias } 181f22e598aSEdgar E. Iglesias } 182f22e598aSEdgar E. Iglesias 183258b2a40SEdgar E. Iglesias static void xen_pvh_init(MachineState *ms) 184258b2a40SEdgar E. Iglesias { 185258b2a40SEdgar E. Iglesias XenPVHMachineState *s = XEN_PVH_MACHINE(ms); 186258b2a40SEdgar E. Iglesias XenPVHMachineClass *xpc = XEN_PVH_MACHINE_GET_CLASS(s); 187258b2a40SEdgar E. Iglesias MemoryRegion *sysmem = get_system_memory(); 188258b2a40SEdgar E. Iglesias 189258b2a40SEdgar E. Iglesias if (ms->ram_size == 0) { 190258b2a40SEdgar E. Iglesias warn_report("%s: ram size not specified. QEMU machine started" 191258b2a40SEdgar E. Iglesias " without IOREQ (no emulated devices including virtio)", 192258b2a40SEdgar E. Iglesias MACHINE_CLASS(object_get_class(OBJECT(ms)))->desc); 193258b2a40SEdgar E. Iglesias return; 194258b2a40SEdgar E. Iglesias } 195258b2a40SEdgar E. Iglesias 196258b2a40SEdgar E. Iglesias xen_pvh_init_ram(s, sysmem); 197b2150e40SEdgar E. Iglesias xen_register_ioreq(&s->ioreq, ms->smp.max_cpus, 198cb988a10SEdgar E. Iglesias xpc->handle_bufioreq, 199b2150e40SEdgar E. Iglesias &xen_memory_listener); 200258b2a40SEdgar E. Iglesias 201258b2a40SEdgar E. Iglesias if (s->cfg.virtio_mmio_num) { 202258b2a40SEdgar E. Iglesias xen_create_virtio_mmio_devices(s); 203258b2a40SEdgar E. Iglesias } 204258b2a40SEdgar E. Iglesias 205258b2a40SEdgar E. Iglesias #ifdef CONFIG_TPM 206258b2a40SEdgar E. Iglesias if (xpc->has_tpm) { 207258b2a40SEdgar E. Iglesias if (s->cfg.tpm.base) { 208258b2a40SEdgar E. Iglesias xen_enable_tpm(s); 209258b2a40SEdgar E. Iglesias } else { 210258b2a40SEdgar E. Iglesias warn_report("tpm-base-addr is not set. TPM will not be enabled"); 211258b2a40SEdgar E. Iglesias } 212258b2a40SEdgar E. Iglesias } 213258b2a40SEdgar E. Iglesias #endif 214258b2a40SEdgar E. Iglesias 215f22e598aSEdgar E. Iglesias /* Non-zero pci-ecam-size enables PCI. */ 216f22e598aSEdgar E. Iglesias if (s->cfg.pci_ecam.size) { 217f22e598aSEdgar E. Iglesias if (s->cfg.pci_ecam.size != 256 * MiB) { 218f22e598aSEdgar E. Iglesias error_report("pci-ecam-size only supports values 0 or 0x10000000"); 219f22e598aSEdgar E. Iglesias exit(EXIT_FAILURE); 220f22e598aSEdgar E. Iglesias } 221*3bcdba25SEdgar E. Iglesias if (!s->cfg.pci_intx_irq_base) { 222*3bcdba25SEdgar E. Iglesias error_report("PCI enabled but pci-intx-irq-base not set"); 223*3bcdba25SEdgar E. Iglesias exit(EXIT_FAILURE); 224*3bcdba25SEdgar E. Iglesias } 225*3bcdba25SEdgar E. Iglesias 226f22e598aSEdgar E. Iglesias xenpvh_gpex_init(s, xpc, sysmem); 227f22e598aSEdgar E. Iglesias } 228f22e598aSEdgar E. Iglesias 229258b2a40SEdgar E. Iglesias /* Call the implementation specific init. */ 230258b2a40SEdgar E. Iglesias if (xpc->init) { 231258b2a40SEdgar E. Iglesias xpc->init(ms); 232258b2a40SEdgar E. Iglesias } 233258b2a40SEdgar E. Iglesias } 234258b2a40SEdgar E. Iglesias 235258b2a40SEdgar E. Iglesias #define XEN_PVH_PROP_MEMMAP_SETTER(n, f) \ 236258b2a40SEdgar E. Iglesias static void xen_pvh_set_ ## n ## _ ## f(Object *obj, Visitor *v, \ 237258b2a40SEdgar E. Iglesias const char *name, void *opaque, \ 238258b2a40SEdgar E. Iglesias Error **errp) \ 239258b2a40SEdgar E. Iglesias { \ 240258b2a40SEdgar E. Iglesias XenPVHMachineState *xp = XEN_PVH_MACHINE(obj); \ 241258b2a40SEdgar E. Iglesias uint64_t value; \ 242258b2a40SEdgar E. Iglesias \ 243258b2a40SEdgar E. Iglesias if (!visit_type_size(v, name, &value, errp)) { \ 244258b2a40SEdgar E. Iglesias return; \ 245258b2a40SEdgar E. Iglesias } \ 246258b2a40SEdgar E. Iglesias xp->cfg.n.f = value; \ 247258b2a40SEdgar E. Iglesias } 248258b2a40SEdgar E. Iglesias 249258b2a40SEdgar E. Iglesias #define XEN_PVH_PROP_MEMMAP_GETTER(n, f) \ 250258b2a40SEdgar E. Iglesias static void xen_pvh_get_ ## n ## _ ## f(Object *obj, Visitor *v, \ 251258b2a40SEdgar E. Iglesias const char *name, void *opaque, \ 252258b2a40SEdgar E. Iglesias Error **errp) \ 253258b2a40SEdgar E. Iglesias { \ 254258b2a40SEdgar E. Iglesias XenPVHMachineState *xp = XEN_PVH_MACHINE(obj); \ 255258b2a40SEdgar E. Iglesias uint64_t value = xp->cfg.n.f; \ 256258b2a40SEdgar E. Iglesias \ 257258b2a40SEdgar E. Iglesias visit_type_uint64(v, name, &value, errp); \ 258258b2a40SEdgar E. Iglesias } 259258b2a40SEdgar E. Iglesias 260258b2a40SEdgar E. Iglesias #define XEN_PVH_PROP_MEMMAP_BASE(n) \ 261258b2a40SEdgar E. Iglesias XEN_PVH_PROP_MEMMAP_SETTER(n, base) \ 262258b2a40SEdgar E. Iglesias XEN_PVH_PROP_MEMMAP_GETTER(n, base) \ 263258b2a40SEdgar E. Iglesias 264258b2a40SEdgar E. Iglesias #define XEN_PVH_PROP_MEMMAP_SIZE(n) \ 265258b2a40SEdgar E. Iglesias XEN_PVH_PROP_MEMMAP_SETTER(n, size) \ 266258b2a40SEdgar E. Iglesias XEN_PVH_PROP_MEMMAP_GETTER(n, size) 267258b2a40SEdgar E. Iglesias 268258b2a40SEdgar E. Iglesias #define XEN_PVH_PROP_MEMMAP(n) \ 269258b2a40SEdgar E. Iglesias XEN_PVH_PROP_MEMMAP_BASE(n) \ 270258b2a40SEdgar E. Iglesias XEN_PVH_PROP_MEMMAP_SIZE(n) 271258b2a40SEdgar E. Iglesias 272258b2a40SEdgar E. Iglesias XEN_PVH_PROP_MEMMAP(ram_low) 273258b2a40SEdgar E. Iglesias XEN_PVH_PROP_MEMMAP(ram_high) 274258b2a40SEdgar E. Iglesias /* TPM only has a base-addr option. */ 275258b2a40SEdgar E. Iglesias XEN_PVH_PROP_MEMMAP_BASE(tpm) 276258b2a40SEdgar E. Iglesias XEN_PVH_PROP_MEMMAP(virtio_mmio) 277f22e598aSEdgar E. Iglesias XEN_PVH_PROP_MEMMAP(pci_ecam) 278f22e598aSEdgar E. Iglesias XEN_PVH_PROP_MEMMAP(pci_mmio) 279f22e598aSEdgar E. Iglesias XEN_PVH_PROP_MEMMAP(pci_mmio_high) 280258b2a40SEdgar E. Iglesias 281*3bcdba25SEdgar E. Iglesias static void xen_pvh_set_pci_intx_irq_base(Object *obj, Visitor *v, 282*3bcdba25SEdgar E. Iglesias const char *name, void *opaque, 283*3bcdba25SEdgar E. Iglesias Error **errp) 284*3bcdba25SEdgar E. Iglesias { 285*3bcdba25SEdgar E. Iglesias XenPVHMachineState *xp = XEN_PVH_MACHINE(obj); 286*3bcdba25SEdgar E. Iglesias uint32_t value; 287*3bcdba25SEdgar E. Iglesias 288*3bcdba25SEdgar E. Iglesias if (!visit_type_uint32(v, name, &value, errp)) { 289*3bcdba25SEdgar E. Iglesias return; 290*3bcdba25SEdgar E. Iglesias } 291*3bcdba25SEdgar E. Iglesias 292*3bcdba25SEdgar E. Iglesias xp->cfg.pci_intx_irq_base = value; 293*3bcdba25SEdgar E. Iglesias } 294*3bcdba25SEdgar E. Iglesias 295*3bcdba25SEdgar E. Iglesias static void xen_pvh_get_pci_intx_irq_base(Object *obj, Visitor *v, 296*3bcdba25SEdgar E. Iglesias const char *name, void *opaque, 297*3bcdba25SEdgar E. Iglesias Error **errp) 298*3bcdba25SEdgar E. Iglesias { 299*3bcdba25SEdgar E. Iglesias XenPVHMachineState *xp = XEN_PVH_MACHINE(obj); 300*3bcdba25SEdgar E. Iglesias uint32_t value = xp->cfg.pci_intx_irq_base; 301*3bcdba25SEdgar E. Iglesias 302*3bcdba25SEdgar E. Iglesias visit_type_uint32(v, name, &value, errp); 303*3bcdba25SEdgar E. Iglesias } 304*3bcdba25SEdgar E. Iglesias 305258b2a40SEdgar E. Iglesias void xen_pvh_class_setup_common_props(XenPVHMachineClass *xpc) 306258b2a40SEdgar E. Iglesias { 307258b2a40SEdgar E. Iglesias ObjectClass *oc = OBJECT_CLASS(xpc); 308258b2a40SEdgar E. Iglesias MachineClass *mc = MACHINE_CLASS(xpc); 309258b2a40SEdgar E. Iglesias 310258b2a40SEdgar E. Iglesias #define OC_MEMMAP_PROP_BASE(c, prop_name, name) \ 311258b2a40SEdgar E. Iglesias do { \ 312258b2a40SEdgar E. Iglesias object_class_property_add(c, prop_name "-base", "uint64_t", \ 313258b2a40SEdgar E. Iglesias xen_pvh_get_ ## name ## _base, \ 314258b2a40SEdgar E. Iglesias xen_pvh_set_ ## name ## _base, NULL, NULL); \ 315258b2a40SEdgar E. Iglesias object_class_property_set_description(oc, prop_name "-base", \ 316258b2a40SEdgar E. Iglesias "Set base address for " prop_name); \ 317258b2a40SEdgar E. Iglesias } while (0) 318258b2a40SEdgar E. Iglesias 319258b2a40SEdgar E. Iglesias #define OC_MEMMAP_PROP_SIZE(c, prop_name, name) \ 320258b2a40SEdgar E. Iglesias do { \ 321258b2a40SEdgar E. Iglesias object_class_property_add(c, prop_name "-size", "uint64_t", \ 322258b2a40SEdgar E. Iglesias xen_pvh_get_ ## name ## _size, \ 323258b2a40SEdgar E. Iglesias xen_pvh_set_ ## name ## _size, NULL, NULL); \ 324258b2a40SEdgar E. Iglesias object_class_property_set_description(oc, prop_name "-size", \ 325258b2a40SEdgar E. Iglesias "Set memory range size for " prop_name); \ 326258b2a40SEdgar E. Iglesias } while (0) 327258b2a40SEdgar E. Iglesias 328258b2a40SEdgar E. Iglesias #define OC_MEMMAP_PROP(c, prop_name, name) \ 329258b2a40SEdgar E. Iglesias do { \ 330258b2a40SEdgar E. Iglesias OC_MEMMAP_PROP_BASE(c, prop_name, name); \ 331258b2a40SEdgar E. Iglesias OC_MEMMAP_PROP_SIZE(c, prop_name, name); \ 332258b2a40SEdgar E. Iglesias } while (0) 333258b2a40SEdgar E. Iglesias 334258b2a40SEdgar E. Iglesias /* 335258b2a40SEdgar E. Iglesias * We provide memmap properties to allow Xen to move things to other 336258b2a40SEdgar E. Iglesias * addresses for example when users need to accomodate the memory-map 337258b2a40SEdgar E. Iglesias * for 1:1 mapped devices/memory. 338258b2a40SEdgar E. Iglesias */ 339258b2a40SEdgar E. Iglesias OC_MEMMAP_PROP(oc, "ram-low", ram_low); 340258b2a40SEdgar E. Iglesias OC_MEMMAP_PROP(oc, "ram-high", ram_high); 341258b2a40SEdgar E. Iglesias 342258b2a40SEdgar E. Iglesias if (xpc->has_virtio_mmio) { 343258b2a40SEdgar E. Iglesias OC_MEMMAP_PROP(oc, "virtio-mmio", virtio_mmio); 344258b2a40SEdgar E. Iglesias } 345258b2a40SEdgar E. Iglesias 346f22e598aSEdgar E. Iglesias if (xpc->has_pci) { 347f22e598aSEdgar E. Iglesias OC_MEMMAP_PROP(oc, "pci-ecam", pci_ecam); 348f22e598aSEdgar E. Iglesias OC_MEMMAP_PROP(oc, "pci-mmio", pci_mmio); 349f22e598aSEdgar E. Iglesias OC_MEMMAP_PROP(oc, "pci-mmio-high", pci_mmio_high); 350*3bcdba25SEdgar E. Iglesias 351*3bcdba25SEdgar E. Iglesias object_class_property_add(oc, "pci-intx-irq-base", "uint32_t", 352*3bcdba25SEdgar E. Iglesias xen_pvh_get_pci_intx_irq_base, 353*3bcdba25SEdgar E. Iglesias xen_pvh_set_pci_intx_irq_base, 354*3bcdba25SEdgar E. Iglesias NULL, NULL); 355*3bcdba25SEdgar E. Iglesias object_class_property_set_description(oc, "pci-intx-irq-base", 356*3bcdba25SEdgar E. Iglesias "Set PCI INTX interrupt base line."); 357f22e598aSEdgar E. Iglesias } 358f22e598aSEdgar E. Iglesias 359258b2a40SEdgar E. Iglesias #ifdef CONFIG_TPM 360258b2a40SEdgar E. Iglesias if (xpc->has_tpm) { 361258b2a40SEdgar E. Iglesias object_class_property_add(oc, "tpm-base-addr", "uint64_t", 362258b2a40SEdgar E. Iglesias xen_pvh_get_tpm_base, 363258b2a40SEdgar E. Iglesias xen_pvh_set_tpm_base, 364258b2a40SEdgar E. Iglesias NULL, NULL); 365258b2a40SEdgar E. Iglesias object_class_property_set_description(oc, "tpm-base-addr", 366258b2a40SEdgar E. Iglesias "Set Base address for TPM device."); 367258b2a40SEdgar E. Iglesias 368258b2a40SEdgar E. Iglesias machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 369258b2a40SEdgar E. Iglesias } 370258b2a40SEdgar E. Iglesias #endif 371258b2a40SEdgar E. Iglesias } 372258b2a40SEdgar E. Iglesias 373258b2a40SEdgar E. Iglesias static void xen_pvh_class_init(ObjectClass *oc, void *data) 374258b2a40SEdgar E. Iglesias { 375258b2a40SEdgar E. Iglesias MachineClass *mc = MACHINE_CLASS(oc); 376258b2a40SEdgar E. Iglesias 377258b2a40SEdgar E. Iglesias mc->init = xen_pvh_init; 378258b2a40SEdgar E. Iglesias 379258b2a40SEdgar E. Iglesias mc->desc = "Xen PVH machine"; 380258b2a40SEdgar E. Iglesias mc->max_cpus = 1; 381258b2a40SEdgar E. Iglesias mc->default_machine_opts = "accel=xen"; 382258b2a40SEdgar E. Iglesias /* Set to zero to make sure that the real ram size is passed. */ 383258b2a40SEdgar E. Iglesias mc->default_ram_size = 0; 384258b2a40SEdgar E. Iglesias } 385258b2a40SEdgar E. Iglesias 386258b2a40SEdgar E. Iglesias static const TypeInfo xen_pvh_info = { 387258b2a40SEdgar E. Iglesias .name = TYPE_XEN_PVH_MACHINE, 388258b2a40SEdgar E. Iglesias .parent = TYPE_MACHINE, 389258b2a40SEdgar E. Iglesias .abstract = true, 390258b2a40SEdgar E. Iglesias .instance_size = sizeof(XenPVHMachineState), 391258b2a40SEdgar E. Iglesias .class_size = sizeof(XenPVHMachineClass), 392258b2a40SEdgar E. Iglesias .class_init = xen_pvh_class_init, 393258b2a40SEdgar E. Iglesias }; 394258b2a40SEdgar E. Iglesias 395258b2a40SEdgar E. Iglesias static void xen_pvh_register_types(void) 396258b2a40SEdgar E. Iglesias { 397258b2a40SEdgar E. Iglesias type_register_static(&xen_pvh_info); 398258b2a40SEdgar E. Iglesias } 399258b2a40SEdgar E. Iglesias 400258b2a40SEdgar E. Iglesias type_init(xen_pvh_register_types); 401