1 /* 2 * ASPEED Watchdog Controller 3 * 4 * Copyright (C) 2016-2017 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 12 #include "qapi/error.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/timer.h" 16 #include "sysemu/watchdog.h" 17 #include "hw/misc/aspeed_scu.h" 18 #include "hw/qdev-properties.h" 19 #include "hw/sysbus.h" 20 #include "hw/watchdog/wdt_aspeed.h" 21 #include "migration/vmstate.h" 22 23 #define WDT_STATUS (0x00 / 4) 24 #define WDT_RELOAD_VALUE (0x04 / 4) 25 #define WDT_RESTART (0x08 / 4) 26 #define WDT_CTRL (0x0C / 4) 27 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) 28 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) 29 #define WDT_CTRL_1MHZ_CLK BIT(4) 30 #define WDT_CTRL_WDT_EXT BIT(3) 31 #define WDT_CTRL_WDT_INTR BIT(2) 32 #define WDT_CTRL_RESET_SYSTEM BIT(1) 33 #define WDT_CTRL_ENABLE BIT(0) 34 #define WDT_RESET_WIDTH (0x18 / 4) 35 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) 36 #define WDT_POLARITY_MASK (0xFF << 24) 37 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) 38 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) 39 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30) 40 #define WDT_DRIVE_TYPE_MASK (0xFF << 24) 41 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) 42 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) 43 #define WDT_RESET_MASK1 (0x1c / 4) 44 45 #define WDT_TIMEOUT_STATUS (0x10 / 4) 46 #define WDT_TIMEOUT_CLEAR (0x14 / 4) 47 48 #define WDT_RESTART_MAGIC 0x4755 49 50 #define AST2600_SCU_RESET_CONTROL1 (0x40 / 4) 51 #define SCU_RESET_CONTROL1 (0x04 / 4) 52 #define SCU_RESET_SDRAM BIT(0) 53 54 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) 55 { 56 return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; 57 } 58 59 static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) 60 { 61 AspeedWDTState *s = ASPEED_WDT(opaque); 62 63 offset >>= 2; 64 65 switch (offset) { 66 case WDT_STATUS: 67 return s->regs[WDT_STATUS]; 68 case WDT_RELOAD_VALUE: 69 return s->regs[WDT_RELOAD_VALUE]; 70 case WDT_RESTART: 71 qemu_log_mask(LOG_GUEST_ERROR, 72 "%s: read from write-only reg at offset 0x%" 73 HWADDR_PRIx "\n", __func__, offset); 74 return 0; 75 case WDT_CTRL: 76 return s->regs[WDT_CTRL]; 77 case WDT_RESET_WIDTH: 78 return s->regs[WDT_RESET_WIDTH]; 79 case WDT_RESET_MASK1: 80 return s->regs[WDT_RESET_MASK1]; 81 case WDT_TIMEOUT_STATUS: 82 case WDT_TIMEOUT_CLEAR: 83 qemu_log_mask(LOG_UNIMP, 84 "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", 85 __func__, offset); 86 return 0; 87 default: 88 qemu_log_mask(LOG_GUEST_ERROR, 89 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 90 __func__, offset); 91 return 0; 92 } 93 94 } 95 96 static void aspeed_wdt_reload(AspeedWDTState *s) 97 { 98 uint64_t reload; 99 100 if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) { 101 reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, 102 s->pclk_freq); 103 } else { 104 reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; 105 } 106 107 if (aspeed_wdt_is_enabled(s)) { 108 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); 109 } 110 } 111 112 static void aspeed_wdt_reload_1mhz(AspeedWDTState *s) 113 { 114 uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; 115 116 if (aspeed_wdt_is_enabled(s)) { 117 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); 118 } 119 } 120 121 122 static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, 123 unsigned size) 124 { 125 AspeedWDTState *s = ASPEED_WDT(opaque); 126 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s); 127 bool enable = data & WDT_CTRL_ENABLE; 128 129 offset >>= 2; 130 131 switch (offset) { 132 case WDT_STATUS: 133 qemu_log_mask(LOG_GUEST_ERROR, 134 "%s: write to read-only reg at offset 0x%" 135 HWADDR_PRIx "\n", __func__, offset); 136 break; 137 case WDT_RELOAD_VALUE: 138 s->regs[WDT_RELOAD_VALUE] = data; 139 break; 140 case WDT_RESTART: 141 if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { 142 s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; 143 awc->wdt_reload(s); 144 } 145 break; 146 case WDT_CTRL: 147 if (enable && !aspeed_wdt_is_enabled(s)) { 148 s->regs[WDT_CTRL] = data; 149 awc->wdt_reload(s); 150 } else if (!enable && aspeed_wdt_is_enabled(s)) { 151 s->regs[WDT_CTRL] = data; 152 timer_del(s->timer); 153 } 154 break; 155 case WDT_RESET_WIDTH: 156 if (awc->reset_pulse) { 157 awc->reset_pulse(s, data & WDT_POLARITY_MASK); 158 } 159 s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask; 160 s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; 161 break; 162 163 case WDT_RESET_MASK1: 164 /* TODO: implement */ 165 s->regs[WDT_RESET_MASK1] = data; 166 break; 167 168 case WDT_TIMEOUT_STATUS: 169 case WDT_TIMEOUT_CLEAR: 170 qemu_log_mask(LOG_UNIMP, 171 "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", 172 __func__, offset); 173 break; 174 default: 175 qemu_log_mask(LOG_GUEST_ERROR, 176 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 177 __func__, offset); 178 } 179 return; 180 } 181 182 static WatchdogTimerModel model = { 183 .wdt_name = TYPE_ASPEED_WDT, 184 .wdt_description = "Aspeed watchdog device", 185 }; 186 187 static const VMStateDescription vmstate_aspeed_wdt = { 188 .name = "vmstate_aspeed_wdt", 189 .version_id = 0, 190 .minimum_version_id = 0, 191 .fields = (VMStateField[]) { 192 VMSTATE_TIMER_PTR(timer, AspeedWDTState), 193 VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX), 194 VMSTATE_END_OF_LIST() 195 } 196 }; 197 198 static const MemoryRegionOps aspeed_wdt_ops = { 199 .read = aspeed_wdt_read, 200 .write = aspeed_wdt_write, 201 .endianness = DEVICE_LITTLE_ENDIAN, 202 .valid.min_access_size = 4, 203 .valid.max_access_size = 4, 204 .valid.unaligned = false, 205 }; 206 207 static void aspeed_wdt_reset(DeviceState *dev) 208 { 209 AspeedWDTState *s = ASPEED_WDT(dev); 210 211 s->regs[WDT_STATUS] = 0x3EF1480; 212 s->regs[WDT_RELOAD_VALUE] = 0x03EF1480; 213 s->regs[WDT_RESTART] = 0; 214 s->regs[WDT_CTRL] = 0; 215 s->regs[WDT_RESET_WIDTH] = 0xFF; 216 217 timer_del(s->timer); 218 } 219 220 static void aspeed_wdt_timer_expired(void *dev) 221 { 222 AspeedWDTState *s = ASPEED_WDT(dev); 223 uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg; 224 225 /* Do not reset on SDRAM controller reset */ 226 if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) { 227 timer_del(s->timer); 228 s->regs[WDT_CTRL] = 0; 229 return; 230 } 231 232 qemu_log_mask(CPU_LOG_RESET, "Watchdog timer %" HWADDR_PRIx " expired.\n", 233 s->iomem.addr); 234 watchdog_perform_action(); 235 timer_del(s->timer); 236 } 237 238 #define PCLK_HZ 24000000 239 240 static void aspeed_wdt_realize(DeviceState *dev, Error **errp) 241 { 242 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 243 AspeedWDTState *s = ASPEED_WDT(dev); 244 245 assert(s->scu); 246 247 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); 248 249 /* FIXME: This setting should be derived from the SCU hw strapping 250 * register SCU70 251 */ 252 s->pclk_freq = PCLK_HZ; 253 254 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, 255 TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4); 256 sysbus_init_mmio(sbd, &s->iomem); 257 } 258 259 static Property aspeed_wdt_properties[] = { 260 DEFINE_PROP_LINK("scu", AspeedWDTState, scu, TYPE_ASPEED_SCU, 261 AspeedSCUState *), 262 DEFINE_PROP_END_OF_LIST(), 263 }; 264 265 static void aspeed_wdt_class_init(ObjectClass *klass, void *data) 266 { 267 DeviceClass *dc = DEVICE_CLASS(klass); 268 269 dc->desc = "ASPEED Watchdog Controller"; 270 dc->realize = aspeed_wdt_realize; 271 dc->reset = aspeed_wdt_reset; 272 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 273 dc->vmsd = &vmstate_aspeed_wdt; 274 device_class_set_props(dc, aspeed_wdt_properties); 275 } 276 277 static const TypeInfo aspeed_wdt_info = { 278 .parent = TYPE_SYS_BUS_DEVICE, 279 .name = TYPE_ASPEED_WDT, 280 .instance_size = sizeof(AspeedWDTState), 281 .class_init = aspeed_wdt_class_init, 282 .class_size = sizeof(AspeedWDTClass), 283 .abstract = true, 284 }; 285 286 static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data) 287 { 288 DeviceClass *dc = DEVICE_CLASS(klass); 289 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 290 291 dc->desc = "ASPEED 2400 Watchdog Controller"; 292 awc->offset = 0x20; 293 awc->ext_pulse_width_mask = 0xff; 294 awc->reset_ctrl_reg = SCU_RESET_CONTROL1; 295 awc->wdt_reload = aspeed_wdt_reload; 296 } 297 298 static const TypeInfo aspeed_2400_wdt_info = { 299 .name = TYPE_ASPEED_2400_WDT, 300 .parent = TYPE_ASPEED_WDT, 301 .instance_size = sizeof(AspeedWDTState), 302 .class_init = aspeed_2400_wdt_class_init, 303 }; 304 305 static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property) 306 { 307 if (property) { 308 if (property == WDT_ACTIVE_HIGH_MAGIC) { 309 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; 310 } else if (property == WDT_ACTIVE_LOW_MAGIC) { 311 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; 312 } else if (property == WDT_PUSH_PULL_MAGIC) { 313 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; 314 } else if (property == WDT_OPEN_DRAIN_MAGIC) { 315 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; 316 } 317 } 318 } 319 320 static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data) 321 { 322 DeviceClass *dc = DEVICE_CLASS(klass); 323 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 324 325 dc->desc = "ASPEED 2500 Watchdog Controller"; 326 awc->offset = 0x20; 327 awc->ext_pulse_width_mask = 0xfffff; 328 awc->reset_ctrl_reg = SCU_RESET_CONTROL1; 329 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; 330 awc->wdt_reload = aspeed_wdt_reload_1mhz; 331 } 332 333 static const TypeInfo aspeed_2500_wdt_info = { 334 .name = TYPE_ASPEED_2500_WDT, 335 .parent = TYPE_ASPEED_WDT, 336 .instance_size = sizeof(AspeedWDTState), 337 .class_init = aspeed_2500_wdt_class_init, 338 }; 339 340 static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) 341 { 342 DeviceClass *dc = DEVICE_CLASS(klass); 343 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 344 345 dc->desc = "ASPEED 2600 Watchdog Controller"; 346 awc->offset = 0x40; 347 awc->ext_pulse_width_mask = 0xfffff; /* TODO */ 348 awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; 349 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; 350 awc->wdt_reload = aspeed_wdt_reload_1mhz; 351 } 352 353 static const TypeInfo aspeed_2600_wdt_info = { 354 .name = TYPE_ASPEED_2600_WDT, 355 .parent = TYPE_ASPEED_WDT, 356 .instance_size = sizeof(AspeedWDTState), 357 .class_init = aspeed_2600_wdt_class_init, 358 }; 359 360 static void wdt_aspeed_register_types(void) 361 { 362 watchdog_add_model(&model); 363 type_register_static(&aspeed_wdt_info); 364 type_register_static(&aspeed_2400_wdt_info); 365 type_register_static(&aspeed_2500_wdt_info); 366 type_register_static(&aspeed_2600_wdt_info); 367 } 368 369 type_init(wdt_aspeed_register_types) 370