1 /* 2 * ASPEED Watchdog Controller 3 * 4 * Copyright (C) 2016-2017 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 12 #include "qapi/error.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/timer.h" 16 #include "sysemu/watchdog.h" 17 #include "hw/misc/aspeed_scu.h" 18 #include "hw/qdev-properties.h" 19 #include "hw/sysbus.h" 20 #include "hw/watchdog/wdt_aspeed.h" 21 #include "migration/vmstate.h" 22 23 #define WDT_STATUS (0x00 / 4) 24 #define WDT_RELOAD_VALUE (0x04 / 4) 25 #define WDT_RESTART (0x08 / 4) 26 #define WDT_CTRL (0x0C / 4) 27 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) 28 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) 29 #define WDT_CTRL_1MHZ_CLK BIT(4) 30 #define WDT_CTRL_WDT_EXT BIT(3) 31 #define WDT_CTRL_WDT_INTR BIT(2) 32 #define WDT_CTRL_RESET_SYSTEM BIT(1) 33 #define WDT_CTRL_ENABLE BIT(0) 34 #define WDT_RESET_WIDTH (0x18 / 4) 35 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) 36 #define WDT_POLARITY_MASK (0xFF << 24) 37 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) 38 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) 39 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30) 40 #define WDT_DRIVE_TYPE_MASK (0xFF << 24) 41 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) 42 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) 43 #define WDT_RESET_MASK1 (0x1c / 4) 44 45 #define WDT_TIMEOUT_STATUS (0x10 / 4) 46 #define WDT_TIMEOUT_CLEAR (0x14 / 4) 47 48 #define WDT_RESTART_MAGIC 0x4755 49 50 #define AST2600_SCU_RESET_CONTROL1 (0x40 / 4) 51 #define SCU_RESET_CONTROL1 (0x04 / 4) 52 #define SCU_RESET_SDRAM BIT(0) 53 54 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) 55 { 56 return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; 57 } 58 59 static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) 60 { 61 AspeedWDTState *s = ASPEED_WDT(opaque); 62 63 offset >>= 2; 64 65 switch (offset) { 66 case WDT_STATUS: 67 return s->regs[WDT_STATUS]; 68 case WDT_RELOAD_VALUE: 69 return s->regs[WDT_RELOAD_VALUE]; 70 case WDT_RESTART: 71 qemu_log_mask(LOG_GUEST_ERROR, 72 "%s: read from write-only reg at offset 0x%" 73 HWADDR_PRIx "\n", __func__, offset); 74 return 0; 75 case WDT_CTRL: 76 return s->regs[WDT_CTRL]; 77 case WDT_RESET_WIDTH: 78 return s->regs[WDT_RESET_WIDTH]; 79 case WDT_RESET_MASK1: 80 return s->regs[WDT_RESET_MASK1]; 81 case WDT_TIMEOUT_STATUS: 82 case WDT_TIMEOUT_CLEAR: 83 qemu_log_mask(LOG_UNIMP, 84 "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", 85 __func__, offset); 86 return 0; 87 default: 88 qemu_log_mask(LOG_GUEST_ERROR, 89 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 90 __func__, offset); 91 return 0; 92 } 93 94 } 95 96 static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk) 97 { 98 uint64_t reload; 99 100 if (pclk) { 101 reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, 102 s->pclk_freq); 103 } else { 104 reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; 105 } 106 107 if (aspeed_wdt_is_enabled(s)) { 108 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); 109 } 110 } 111 112 static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, 113 unsigned size) 114 { 115 AspeedWDTState *s = ASPEED_WDT(opaque); 116 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s); 117 bool enable = data & WDT_CTRL_ENABLE; 118 119 offset >>= 2; 120 121 switch (offset) { 122 case WDT_STATUS: 123 qemu_log_mask(LOG_GUEST_ERROR, 124 "%s: write to read-only reg at offset 0x%" 125 HWADDR_PRIx "\n", __func__, offset); 126 break; 127 case WDT_RELOAD_VALUE: 128 s->regs[WDT_RELOAD_VALUE] = data; 129 break; 130 case WDT_RESTART: 131 if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { 132 s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; 133 aspeed_wdt_reload(s, !(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)); 134 } 135 break; 136 case WDT_CTRL: 137 if (enable && !aspeed_wdt_is_enabled(s)) { 138 s->regs[WDT_CTRL] = data; 139 aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); 140 } else if (!enable && aspeed_wdt_is_enabled(s)) { 141 s->regs[WDT_CTRL] = data; 142 timer_del(s->timer); 143 } 144 break; 145 case WDT_RESET_WIDTH: 146 if (awc->reset_pulse) { 147 awc->reset_pulse(s, data & WDT_POLARITY_MASK); 148 } 149 s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask; 150 s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; 151 break; 152 153 case WDT_RESET_MASK1: 154 /* TODO: implement */ 155 s->regs[WDT_RESET_MASK1] = data; 156 break; 157 158 case WDT_TIMEOUT_STATUS: 159 case WDT_TIMEOUT_CLEAR: 160 qemu_log_mask(LOG_UNIMP, 161 "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", 162 __func__, offset); 163 break; 164 default: 165 qemu_log_mask(LOG_GUEST_ERROR, 166 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 167 __func__, offset); 168 } 169 return; 170 } 171 172 static WatchdogTimerModel model = { 173 .wdt_name = TYPE_ASPEED_WDT, 174 .wdt_description = "Aspeed watchdog device", 175 }; 176 177 static const VMStateDescription vmstate_aspeed_wdt = { 178 .name = "vmstate_aspeed_wdt", 179 .version_id = 0, 180 .minimum_version_id = 0, 181 .fields = (VMStateField[]) { 182 VMSTATE_TIMER_PTR(timer, AspeedWDTState), 183 VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX), 184 VMSTATE_END_OF_LIST() 185 } 186 }; 187 188 static const MemoryRegionOps aspeed_wdt_ops = { 189 .read = aspeed_wdt_read, 190 .write = aspeed_wdt_write, 191 .endianness = DEVICE_LITTLE_ENDIAN, 192 .valid.min_access_size = 4, 193 .valid.max_access_size = 4, 194 .valid.unaligned = false, 195 }; 196 197 static void aspeed_wdt_reset(DeviceState *dev) 198 { 199 AspeedWDTState *s = ASPEED_WDT(dev); 200 201 s->regs[WDT_STATUS] = 0x3EF1480; 202 s->regs[WDT_RELOAD_VALUE] = 0x03EF1480; 203 s->regs[WDT_RESTART] = 0; 204 s->regs[WDT_CTRL] = 0; 205 s->regs[WDT_RESET_WIDTH] = 0xFF; 206 207 timer_del(s->timer); 208 } 209 210 static void aspeed_wdt_timer_expired(void *dev) 211 { 212 AspeedWDTState *s = ASPEED_WDT(dev); 213 uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg; 214 215 /* Do not reset on SDRAM controller reset */ 216 if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) { 217 timer_del(s->timer); 218 s->regs[WDT_CTRL] = 0; 219 return; 220 } 221 222 qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n"); 223 watchdog_perform_action(); 224 timer_del(s->timer); 225 } 226 227 #define PCLK_HZ 24000000 228 229 static void aspeed_wdt_realize(DeviceState *dev, Error **errp) 230 { 231 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 232 AspeedWDTState *s = ASPEED_WDT(dev); 233 Error *err = NULL; 234 Object *obj; 235 236 obj = object_property_get_link(OBJECT(dev), "scu", &err); 237 if (!obj) { 238 error_propagate(errp, err); 239 error_prepend(errp, "required link 'scu' not found: "); 240 return; 241 } 242 s->scu = ASPEED_SCU(obj); 243 244 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); 245 246 /* FIXME: This setting should be derived from the SCU hw strapping 247 * register SCU70 248 */ 249 s->pclk_freq = PCLK_HZ; 250 251 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, 252 TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4); 253 sysbus_init_mmio(sbd, &s->iomem); 254 } 255 256 static void aspeed_wdt_class_init(ObjectClass *klass, void *data) 257 { 258 DeviceClass *dc = DEVICE_CLASS(klass); 259 260 dc->desc = "ASPEED Watchdog Controller"; 261 dc->realize = aspeed_wdt_realize; 262 dc->reset = aspeed_wdt_reset; 263 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 264 dc->vmsd = &vmstate_aspeed_wdt; 265 } 266 267 static const TypeInfo aspeed_wdt_info = { 268 .parent = TYPE_SYS_BUS_DEVICE, 269 .name = TYPE_ASPEED_WDT, 270 .instance_size = sizeof(AspeedWDTState), 271 .class_init = aspeed_wdt_class_init, 272 .class_size = sizeof(AspeedWDTClass), 273 .abstract = true, 274 }; 275 276 static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data) 277 { 278 DeviceClass *dc = DEVICE_CLASS(klass); 279 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 280 281 dc->desc = "ASPEED 2400 Watchdog Controller"; 282 awc->offset = 0x20; 283 awc->ext_pulse_width_mask = 0xff; 284 awc->reset_ctrl_reg = SCU_RESET_CONTROL1; 285 } 286 287 static const TypeInfo aspeed_2400_wdt_info = { 288 .name = TYPE_ASPEED_2400_WDT, 289 .parent = TYPE_ASPEED_WDT, 290 .instance_size = sizeof(AspeedWDTState), 291 .class_init = aspeed_2400_wdt_class_init, 292 }; 293 294 static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property) 295 { 296 if (property) { 297 if (property == WDT_ACTIVE_HIGH_MAGIC) { 298 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; 299 } else if (property == WDT_ACTIVE_LOW_MAGIC) { 300 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; 301 } else if (property == WDT_PUSH_PULL_MAGIC) { 302 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; 303 } else if (property == WDT_OPEN_DRAIN_MAGIC) { 304 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; 305 } 306 } 307 } 308 309 static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data) 310 { 311 DeviceClass *dc = DEVICE_CLASS(klass); 312 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 313 314 dc->desc = "ASPEED 2500 Watchdog Controller"; 315 awc->offset = 0x20; 316 awc->ext_pulse_width_mask = 0xfffff; 317 awc->reset_ctrl_reg = SCU_RESET_CONTROL1; 318 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; 319 } 320 321 static const TypeInfo aspeed_2500_wdt_info = { 322 .name = TYPE_ASPEED_2500_WDT, 323 .parent = TYPE_ASPEED_WDT, 324 .instance_size = sizeof(AspeedWDTState), 325 .class_init = aspeed_2500_wdt_class_init, 326 }; 327 328 static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) 329 { 330 DeviceClass *dc = DEVICE_CLASS(klass); 331 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 332 333 dc->desc = "ASPEED 2600 Watchdog Controller"; 334 awc->offset = 0x40; 335 awc->ext_pulse_width_mask = 0xfffff; /* TODO */ 336 awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; 337 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; 338 } 339 340 static const TypeInfo aspeed_2600_wdt_info = { 341 .name = TYPE_ASPEED_2600_WDT, 342 .parent = TYPE_ASPEED_WDT, 343 .instance_size = sizeof(AspeedWDTState), 344 .class_init = aspeed_2600_wdt_class_init, 345 }; 346 347 static void wdt_aspeed_register_types(void) 348 { 349 watchdog_add_model(&model); 350 type_register_static(&aspeed_wdt_info); 351 type_register_static(&aspeed_2400_wdt_info); 352 type_register_static(&aspeed_2500_wdt_info); 353 type_register_static(&aspeed_2600_wdt_info); 354 } 355 356 type_init(wdt_aspeed_register_types) 357