xref: /openbmc/qemu/hw/watchdog/wdt_aspeed.c (revision 64552b6b)
1 /*
2  * ASPEED Watchdog Controller
3  *
4  * Copyright (C) 2016-2017 IBM Corp.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #include "qemu/osdep.h"
11 
12 #include "qapi/error.h"
13 #include "qemu/log.h"
14 #include "qemu/module.h"
15 #include "qemu/timer.h"
16 #include "sysemu/watchdog.h"
17 #include "hw/misc/aspeed_scu.h"
18 #include "hw/sysbus.h"
19 #include "hw/watchdog/wdt_aspeed.h"
20 
21 #define WDT_STATUS                      (0x00 / 4)
22 #define WDT_RELOAD_VALUE                (0x04 / 4)
23 #define WDT_RESTART                     (0x08 / 4)
24 #define WDT_CTRL                        (0x0C / 4)
25 #define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
26 #define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
27 #define   WDT_CTRL_1MHZ_CLK             BIT(4)
28 #define   WDT_CTRL_WDT_EXT              BIT(3)
29 #define   WDT_CTRL_WDT_INTR             BIT(2)
30 #define   WDT_CTRL_RESET_SYSTEM         BIT(1)
31 #define   WDT_CTRL_ENABLE               BIT(0)
32 #define WDT_RESET_WIDTH                 (0x18 / 4)
33 #define   WDT_RESET_WIDTH_ACTIVE_HIGH   BIT(31)
34 #define     WDT_POLARITY_MASK           (0xFF << 24)
35 #define     WDT_ACTIVE_HIGH_MAGIC       (0xA5 << 24)
36 #define     WDT_ACTIVE_LOW_MAGIC        (0x5A << 24)
37 #define   WDT_RESET_WIDTH_PUSH_PULL     BIT(30)
38 #define     WDT_DRIVE_TYPE_MASK         (0xFF << 24)
39 #define     WDT_PUSH_PULL_MAGIC         (0xA8 << 24)
40 #define     WDT_OPEN_DRAIN_MAGIC        (0x8A << 24)
41 
42 #define WDT_TIMEOUT_STATUS              (0x10 / 4)
43 #define WDT_TIMEOUT_CLEAR               (0x14 / 4)
44 
45 #define WDT_RESTART_MAGIC               0x4755
46 
47 #define SCU_RESET_CONTROL1              (0x04 / 4)
48 #define    SCU_RESET_SDRAM              BIT(0)
49 
50 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
51 {
52     return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
53 }
54 
55 static bool is_ast2500(const AspeedWDTState *s)
56 {
57     switch (s->silicon_rev) {
58     case AST2500_A0_SILICON_REV:
59     case AST2500_A1_SILICON_REV:
60         return true;
61     case AST2400_A0_SILICON_REV:
62     case AST2400_A1_SILICON_REV:
63     default:
64         break;
65     }
66 
67     return false;
68 }
69 
70 static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
71 {
72     AspeedWDTState *s = ASPEED_WDT(opaque);
73 
74     offset >>= 2;
75 
76     switch (offset) {
77     case WDT_STATUS:
78         return s->regs[WDT_STATUS];
79     case WDT_RELOAD_VALUE:
80         return s->regs[WDT_RELOAD_VALUE];
81     case WDT_RESTART:
82         qemu_log_mask(LOG_GUEST_ERROR,
83                       "%s: read from write-only reg at offset 0x%"
84                       HWADDR_PRIx "\n", __func__, offset);
85         return 0;
86     case WDT_CTRL:
87         return s->regs[WDT_CTRL];
88     case WDT_RESET_WIDTH:
89         return s->regs[WDT_RESET_WIDTH];
90     case WDT_TIMEOUT_STATUS:
91     case WDT_TIMEOUT_CLEAR:
92         qemu_log_mask(LOG_UNIMP,
93                       "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
94                       __func__, offset);
95         return 0;
96     default:
97         qemu_log_mask(LOG_GUEST_ERROR,
98                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
99                       __func__, offset);
100         return 0;
101     }
102 
103 }
104 
105 static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk)
106 {
107     uint64_t reload;
108 
109     if (pclk) {
110         reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
111                           s->pclk_freq);
112     } else {
113         reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
114     }
115 
116     if (aspeed_wdt_is_enabled(s)) {
117         timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
118     }
119 }
120 
121 static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
122                              unsigned size)
123 {
124     AspeedWDTState *s = ASPEED_WDT(opaque);
125     bool enable = data & WDT_CTRL_ENABLE;
126 
127     offset >>= 2;
128 
129     switch (offset) {
130     case WDT_STATUS:
131         qemu_log_mask(LOG_GUEST_ERROR,
132                       "%s: write to read-only reg at offset 0x%"
133                       HWADDR_PRIx "\n", __func__, offset);
134         break;
135     case WDT_RELOAD_VALUE:
136         s->regs[WDT_RELOAD_VALUE] = data;
137         break;
138     case WDT_RESTART:
139         if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
140             s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
141             aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
142         }
143         break;
144     case WDT_CTRL:
145         if (enable && !aspeed_wdt_is_enabled(s)) {
146             s->regs[WDT_CTRL] = data;
147             aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK));
148         } else if (!enable && aspeed_wdt_is_enabled(s)) {
149             s->regs[WDT_CTRL] = data;
150             timer_del(s->timer);
151         }
152         break;
153     case WDT_RESET_WIDTH:
154     {
155         uint32_t property = data & WDT_POLARITY_MASK;
156 
157         if (property && is_ast2500(s)) {
158             if (property == WDT_ACTIVE_HIGH_MAGIC) {
159                 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH;
160             } else if (property == WDT_ACTIVE_LOW_MAGIC) {
161                 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH;
162             } else if (property == WDT_PUSH_PULL_MAGIC) {
163                 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL;
164             } else if (property == WDT_OPEN_DRAIN_MAGIC) {
165                 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL;
166             }
167         }
168         s->regs[WDT_RESET_WIDTH] &= ~s->ext_pulse_width_mask;
169         s->regs[WDT_RESET_WIDTH] |= data & s->ext_pulse_width_mask;
170         break;
171     }
172     case WDT_TIMEOUT_STATUS:
173     case WDT_TIMEOUT_CLEAR:
174         qemu_log_mask(LOG_UNIMP,
175                       "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
176                       __func__, offset);
177         break;
178     default:
179         qemu_log_mask(LOG_GUEST_ERROR,
180                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
181                       __func__, offset);
182     }
183     return;
184 }
185 
186 static WatchdogTimerModel model = {
187     .wdt_name = TYPE_ASPEED_WDT,
188     .wdt_description = "Aspeed watchdog device",
189 };
190 
191 static const VMStateDescription vmstate_aspeed_wdt = {
192     .name = "vmstate_aspeed_wdt",
193     .version_id = 0,
194     .minimum_version_id = 0,
195     .fields = (VMStateField[]) {
196         VMSTATE_TIMER_PTR(timer, AspeedWDTState),
197         VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
198         VMSTATE_END_OF_LIST()
199     }
200 };
201 
202 static const MemoryRegionOps aspeed_wdt_ops = {
203     .read = aspeed_wdt_read,
204     .write = aspeed_wdt_write,
205     .endianness = DEVICE_LITTLE_ENDIAN,
206     .valid.min_access_size = 4,
207     .valid.max_access_size = 4,
208     .valid.unaligned = false,
209 };
210 
211 static void aspeed_wdt_reset(DeviceState *dev)
212 {
213     AspeedWDTState *s = ASPEED_WDT(dev);
214 
215     s->regs[WDT_STATUS] = 0x3EF1480;
216     s->regs[WDT_RELOAD_VALUE] = 0x03EF1480;
217     s->regs[WDT_RESTART] = 0;
218     s->regs[WDT_CTRL] = 0;
219     s->regs[WDT_RESET_WIDTH] = 0xFF;
220 
221     timer_del(s->timer);
222 }
223 
224 static void aspeed_wdt_timer_expired(void *dev)
225 {
226     AspeedWDTState *s = ASPEED_WDT(dev);
227 
228     /* Do not reset on SDRAM controller reset */
229     if (s->scu->regs[SCU_RESET_CONTROL1] & SCU_RESET_SDRAM) {
230         timer_del(s->timer);
231         s->regs[WDT_CTRL] = 0;
232         return;
233     }
234 
235     qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
236     watchdog_perform_action();
237     timer_del(s->timer);
238 }
239 
240 #define PCLK_HZ 24000000
241 
242 static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
243 {
244     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
245     AspeedWDTState *s = ASPEED_WDT(dev);
246     Error *err = NULL;
247     Object *obj;
248 
249     obj = object_property_get_link(OBJECT(dev), "scu", &err);
250     if (!obj) {
251         error_propagate(errp, err);
252         error_prepend(errp, "required link 'scu' not found: ");
253         return;
254     }
255     s->scu = ASPEED_SCU(obj);
256 
257     if (!is_supported_silicon_rev(s->silicon_rev)) {
258         error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
259                 s->silicon_rev);
260         return;
261     }
262 
263     switch (s->silicon_rev) {
264     case AST2400_A0_SILICON_REV:
265     case AST2400_A1_SILICON_REV:
266         s->ext_pulse_width_mask = 0xff;
267         break;
268     case AST2500_A0_SILICON_REV:
269     case AST2500_A1_SILICON_REV:
270         s->ext_pulse_width_mask = 0xfffff;
271         break;
272     default:
273         g_assert_not_reached();
274     }
275 
276     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
277 
278     /* FIXME: This setting should be derived from the SCU hw strapping
279      * register SCU70
280      */
281     s->pclk_freq = PCLK_HZ;
282 
283     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
284                           TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
285     sysbus_init_mmio(sbd, &s->iomem);
286 }
287 
288 static Property aspeed_wdt_properties[] = {
289     DEFINE_PROP_UINT32("silicon-rev", AspeedWDTState, silicon_rev, 0),
290     DEFINE_PROP_END_OF_LIST(),
291 };
292 
293 static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
294 {
295     DeviceClass *dc = DEVICE_CLASS(klass);
296 
297     dc->realize = aspeed_wdt_realize;
298     dc->reset = aspeed_wdt_reset;
299     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
300     dc->vmsd = &vmstate_aspeed_wdt;
301     dc->props = aspeed_wdt_properties;
302 }
303 
304 static const TypeInfo aspeed_wdt_info = {
305     .parent = TYPE_SYS_BUS_DEVICE,
306     .name  = TYPE_ASPEED_WDT,
307     .instance_size  = sizeof(AspeedWDTState),
308     .class_init = aspeed_wdt_class_init,
309 };
310 
311 static void wdt_aspeed_register_types(void)
312 {
313     watchdog_add_model(&model);
314     type_register_static(&aspeed_wdt_info);
315 }
316 
317 type_init(wdt_aspeed_register_types)
318