1 /* 2 * ASPEED Watchdog Controller 3 * 4 * Copyright (C) 2016-2017 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 12 #include "qapi/error.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/timer.h" 16 #include "sysemu/watchdog.h" 17 #include "hw/misc/aspeed_scu.h" 18 #include "hw/qdev-properties.h" 19 #include "hw/sysbus.h" 20 #include "hw/watchdog/wdt_aspeed.h" 21 #include "migration/vmstate.h" 22 23 #define WDT_STATUS (0x00 / 4) 24 #define WDT_RELOAD_VALUE (0x04 / 4) 25 #define WDT_RESTART (0x08 / 4) 26 #define WDT_CTRL (0x0C / 4) 27 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) 28 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) 29 #define WDT_CTRL_1MHZ_CLK BIT(4) 30 #define WDT_CTRL_WDT_EXT BIT(3) 31 #define WDT_CTRL_WDT_INTR BIT(2) 32 #define WDT_CTRL_RESET_SYSTEM BIT(1) 33 #define WDT_CTRL_ENABLE BIT(0) 34 #define WDT_RESET_WIDTH (0x18 / 4) 35 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) 36 #define WDT_POLARITY_MASK (0xFF << 24) 37 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) 38 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) 39 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30) 40 #define WDT_DRIVE_TYPE_MASK (0xFF << 24) 41 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) 42 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) 43 #define WDT_RESET_MASK1 (0x1c / 4) 44 45 #define WDT_TIMEOUT_STATUS (0x10 / 4) 46 #define WDT_TIMEOUT_CLEAR (0x14 / 4) 47 48 #define WDT_RESTART_MAGIC 0x4755 49 50 #define AST2600_SCU_RESET_CONTROL1 (0x40 / 4) 51 #define SCU_RESET_CONTROL1 (0x04 / 4) 52 #define SCU_RESET_SDRAM BIT(0) 53 54 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) 55 { 56 return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; 57 } 58 59 static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) 60 { 61 AspeedWDTState *s = ASPEED_WDT(opaque); 62 63 offset >>= 2; 64 65 switch (offset) { 66 case WDT_STATUS: 67 return s->regs[WDT_STATUS]; 68 case WDT_RELOAD_VALUE: 69 return s->regs[WDT_RELOAD_VALUE]; 70 case WDT_RESTART: 71 qemu_log_mask(LOG_GUEST_ERROR, 72 "%s: read from write-only reg at offset 0x%" 73 HWADDR_PRIx "\n", __func__, offset); 74 return 0; 75 case WDT_CTRL: 76 return s->regs[WDT_CTRL]; 77 case WDT_RESET_WIDTH: 78 return s->regs[WDT_RESET_WIDTH]; 79 case WDT_RESET_MASK1: 80 return s->regs[WDT_RESET_MASK1]; 81 case WDT_TIMEOUT_STATUS: 82 case WDT_TIMEOUT_CLEAR: 83 qemu_log_mask(LOG_UNIMP, 84 "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", 85 __func__, offset); 86 return 0; 87 default: 88 qemu_log_mask(LOG_GUEST_ERROR, 89 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 90 __func__, offset); 91 return 0; 92 } 93 94 } 95 96 static void aspeed_wdt_reload(AspeedWDTState *s) 97 { 98 uint64_t reload; 99 100 if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) { 101 reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, 102 s->pclk_freq); 103 } else { 104 reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; 105 } 106 107 if (aspeed_wdt_is_enabled(s)) { 108 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); 109 } 110 } 111 112 static void aspeed_wdt_reload_1mhz(AspeedWDTState *s) 113 { 114 uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; 115 116 if (aspeed_wdt_is_enabled(s)) { 117 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); 118 } 119 } 120 121 static uint64_t aspeed_2400_sanitize_ctrl(uint64_t data) 122 { 123 return data & 0xffff; 124 } 125 126 static uint64_t aspeed_2500_sanitize_ctrl(uint64_t data) 127 { 128 return (data & ~(0xfUL << 8)) | WDT_CTRL_1MHZ_CLK; 129 } 130 131 static uint64_t aspeed_2600_sanitize_ctrl(uint64_t data) 132 { 133 return data & ~(0x7UL << 7); 134 } 135 136 static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, 137 unsigned size) 138 { 139 AspeedWDTState *s = ASPEED_WDT(opaque); 140 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s); 141 bool enable; 142 143 offset >>= 2; 144 145 switch (offset) { 146 case WDT_STATUS: 147 qemu_log_mask(LOG_GUEST_ERROR, 148 "%s: write to read-only reg at offset 0x%" 149 HWADDR_PRIx "\n", __func__, offset); 150 break; 151 case WDT_RELOAD_VALUE: 152 s->regs[WDT_RELOAD_VALUE] = data; 153 break; 154 case WDT_RESTART: 155 if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { 156 s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; 157 awc->wdt_reload(s); 158 } 159 break; 160 case WDT_CTRL: 161 data = awc->sanitize_ctrl(data); 162 enable = data & WDT_CTRL_ENABLE; 163 if (enable && !aspeed_wdt_is_enabled(s)) { 164 s->regs[WDT_CTRL] = data; 165 awc->wdt_reload(s); 166 } else if (!enable && aspeed_wdt_is_enabled(s)) { 167 s->regs[WDT_CTRL] = data; 168 timer_del(s->timer); 169 } else { 170 s->regs[WDT_CTRL] = data; 171 } 172 break; 173 case WDT_RESET_WIDTH: 174 if (awc->reset_pulse) { 175 awc->reset_pulse(s, data & WDT_POLARITY_MASK); 176 } 177 s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask; 178 s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; 179 break; 180 181 case WDT_RESET_MASK1: 182 /* TODO: implement */ 183 s->regs[WDT_RESET_MASK1] = data; 184 break; 185 186 case WDT_TIMEOUT_STATUS: 187 case WDT_TIMEOUT_CLEAR: 188 qemu_log_mask(LOG_UNIMP, 189 "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", 190 __func__, offset); 191 break; 192 default: 193 qemu_log_mask(LOG_GUEST_ERROR, 194 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 195 __func__, offset); 196 } 197 return; 198 } 199 200 static WatchdogTimerModel model = { 201 .wdt_name = TYPE_ASPEED_WDT, 202 .wdt_description = "Aspeed watchdog device", 203 }; 204 205 static const VMStateDescription vmstate_aspeed_wdt = { 206 .name = "vmstate_aspeed_wdt", 207 .version_id = 0, 208 .minimum_version_id = 0, 209 .fields = (VMStateField[]) { 210 VMSTATE_TIMER_PTR(timer, AspeedWDTState), 211 VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX), 212 VMSTATE_END_OF_LIST() 213 } 214 }; 215 216 static const MemoryRegionOps aspeed_wdt_ops = { 217 .read = aspeed_wdt_read, 218 .write = aspeed_wdt_write, 219 .endianness = DEVICE_LITTLE_ENDIAN, 220 .valid.min_access_size = 4, 221 .valid.max_access_size = 4, 222 .valid.unaligned = false, 223 }; 224 225 static void aspeed_wdt_reset(DeviceState *dev) 226 { 227 AspeedWDTState *s = ASPEED_WDT(dev); 228 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s); 229 230 s->regs[WDT_STATUS] = 0x3EF1480; 231 s->regs[WDT_RELOAD_VALUE] = 0x03EF1480; 232 s->regs[WDT_RESTART] = 0; 233 s->regs[WDT_CTRL] = awc->sanitize_ctrl(0); 234 s->regs[WDT_RESET_WIDTH] = 0xFF; 235 236 timer_del(s->timer); 237 } 238 239 static void aspeed_wdt_timer_expired(void *dev) 240 { 241 AspeedWDTState *s = ASPEED_WDT(dev); 242 uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg; 243 244 /* Do not reset on SDRAM controller reset */ 245 if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) { 246 timer_del(s->timer); 247 s->regs[WDT_CTRL] = 0; 248 return; 249 } 250 251 qemu_log_mask(CPU_LOG_RESET, "Watchdog timer %" HWADDR_PRIx " expired.\n", 252 s->iomem.addr); 253 watchdog_perform_action(); 254 timer_del(s->timer); 255 } 256 257 #define PCLK_HZ 24000000 258 259 static void aspeed_wdt_realize(DeviceState *dev, Error **errp) 260 { 261 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 262 AspeedWDTState *s = ASPEED_WDT(dev); 263 264 assert(s->scu); 265 266 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); 267 268 /* FIXME: This setting should be derived from the SCU hw strapping 269 * register SCU70 270 */ 271 s->pclk_freq = PCLK_HZ; 272 273 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, 274 TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4); 275 sysbus_init_mmio(sbd, &s->iomem); 276 } 277 278 static Property aspeed_wdt_properties[] = { 279 DEFINE_PROP_LINK("scu", AspeedWDTState, scu, TYPE_ASPEED_SCU, 280 AspeedSCUState *), 281 DEFINE_PROP_END_OF_LIST(), 282 }; 283 284 static void aspeed_wdt_class_init(ObjectClass *klass, void *data) 285 { 286 DeviceClass *dc = DEVICE_CLASS(klass); 287 288 dc->desc = "ASPEED Watchdog Controller"; 289 dc->realize = aspeed_wdt_realize; 290 dc->reset = aspeed_wdt_reset; 291 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 292 dc->vmsd = &vmstate_aspeed_wdt; 293 device_class_set_props(dc, aspeed_wdt_properties); 294 } 295 296 static const TypeInfo aspeed_wdt_info = { 297 .parent = TYPE_SYS_BUS_DEVICE, 298 .name = TYPE_ASPEED_WDT, 299 .instance_size = sizeof(AspeedWDTState), 300 .class_init = aspeed_wdt_class_init, 301 .class_size = sizeof(AspeedWDTClass), 302 .abstract = true, 303 }; 304 305 static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data) 306 { 307 DeviceClass *dc = DEVICE_CLASS(klass); 308 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 309 310 dc->desc = "ASPEED 2400 Watchdog Controller"; 311 awc->offset = 0x20; 312 awc->ext_pulse_width_mask = 0xff; 313 awc->reset_ctrl_reg = SCU_RESET_CONTROL1; 314 awc->wdt_reload = aspeed_wdt_reload; 315 awc->sanitize_ctrl = aspeed_2400_sanitize_ctrl; 316 } 317 318 static const TypeInfo aspeed_2400_wdt_info = { 319 .name = TYPE_ASPEED_2400_WDT, 320 .parent = TYPE_ASPEED_WDT, 321 .instance_size = sizeof(AspeedWDTState), 322 .class_init = aspeed_2400_wdt_class_init, 323 }; 324 325 static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property) 326 { 327 if (property) { 328 if (property == WDT_ACTIVE_HIGH_MAGIC) { 329 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; 330 } else if (property == WDT_ACTIVE_LOW_MAGIC) { 331 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; 332 } else if (property == WDT_PUSH_PULL_MAGIC) { 333 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; 334 } else if (property == WDT_OPEN_DRAIN_MAGIC) { 335 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; 336 } 337 } 338 } 339 340 static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data) 341 { 342 DeviceClass *dc = DEVICE_CLASS(klass); 343 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 344 345 dc->desc = "ASPEED 2500 Watchdog Controller"; 346 awc->offset = 0x20; 347 awc->ext_pulse_width_mask = 0xfffff; 348 awc->reset_ctrl_reg = SCU_RESET_CONTROL1; 349 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; 350 awc->wdt_reload = aspeed_wdt_reload_1mhz; 351 awc->sanitize_ctrl = aspeed_2500_sanitize_ctrl; 352 } 353 354 static const TypeInfo aspeed_2500_wdt_info = { 355 .name = TYPE_ASPEED_2500_WDT, 356 .parent = TYPE_ASPEED_WDT, 357 .instance_size = sizeof(AspeedWDTState), 358 .class_init = aspeed_2500_wdt_class_init, 359 }; 360 361 static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) 362 { 363 DeviceClass *dc = DEVICE_CLASS(klass); 364 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 365 366 dc->desc = "ASPEED 2600 Watchdog Controller"; 367 awc->offset = 0x40; 368 awc->ext_pulse_width_mask = 0xfffff; /* TODO */ 369 awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1; 370 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; 371 awc->wdt_reload = aspeed_wdt_reload_1mhz; 372 awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl; 373 } 374 375 static const TypeInfo aspeed_2600_wdt_info = { 376 .name = TYPE_ASPEED_2600_WDT, 377 .parent = TYPE_ASPEED_WDT, 378 .instance_size = sizeof(AspeedWDTState), 379 .class_init = aspeed_2600_wdt_class_init, 380 }; 381 382 static void wdt_aspeed_register_types(void) 383 { 384 watchdog_add_model(&model); 385 type_register_static(&aspeed_wdt_info); 386 type_register_static(&aspeed_2400_wdt_info); 387 type_register_static(&aspeed_2500_wdt_info); 388 type_register_static(&aspeed_2600_wdt_info); 389 } 390 391 type_init(wdt_aspeed_register_types) 392