xref: /openbmc/qemu/hw/watchdog/wdt_aspeed.c (revision 05caa062)
1 /*
2  * ASPEED Watchdog Controller
3  *
4  * Copyright (C) 2016-2017 IBM Corp.
5  *
6  * This code is licensed under the GPL version 2 or later. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #include "qemu/osdep.h"
11 
12 #include "qapi/error.h"
13 #include "qemu/log.h"
14 #include "qemu/module.h"
15 #include "qemu/timer.h"
16 #include "sysemu/watchdog.h"
17 #include "hw/qdev-properties.h"
18 #include "hw/sysbus.h"
19 #include "hw/watchdog/wdt_aspeed.h"
20 #include "migration/vmstate.h"
21 #include "trace.h"
22 
23 #define WDT_STATUS                      (0x00 / 4)
24 #define WDT_RELOAD_VALUE                (0x04 / 4)
25 #define WDT_RESTART                     (0x08 / 4)
26 #define WDT_CTRL                        (0x0C / 4)
27 #define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
28 #define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
29 #define   WDT_CTRL_1MHZ_CLK             BIT(4)
30 #define   WDT_CTRL_WDT_EXT              BIT(3)
31 #define   WDT_CTRL_WDT_INTR             BIT(2)
32 #define   WDT_CTRL_RESET_SYSTEM         BIT(1)
33 #define   WDT_CTRL_ENABLE               BIT(0)
34 #define WDT_RESET_WIDTH                 (0x18 / 4)
35 #define   WDT_RESET_WIDTH_ACTIVE_HIGH   BIT(31)
36 #define     WDT_POLARITY_MASK           (0xFF << 24)
37 #define     WDT_ACTIVE_HIGH_MAGIC       (0xA5 << 24)
38 #define     WDT_ACTIVE_LOW_MAGIC        (0x5A << 24)
39 #define   WDT_RESET_WIDTH_PUSH_PULL     BIT(30)
40 #define     WDT_DRIVE_TYPE_MASK         (0xFF << 24)
41 #define     WDT_PUSH_PULL_MAGIC         (0xA8 << 24)
42 #define     WDT_OPEN_DRAIN_MAGIC        (0x8A << 24)
43 #define WDT_RESET_MASK1                 (0x1c / 4)
44 #define WDT_RESET_MASK2                 (0x20 / 4)
45 
46 #define WDT_SW_RESET_CTRL               (0x24 / 4)
47 #define WDT_SW_RESET_MASK1              (0x28 / 4)
48 #define WDT_SW_RESET_MASK2              (0x2c / 4)
49 
50 #define WDT_TIMEOUT_STATUS              (0x10 / 4)
51 #define WDT_TIMEOUT_CLEAR               (0x14 / 4)
52 
53 #define WDT_RESTART_MAGIC               0x4755
54 
55 #define AST2600_SCU_RESET_CONTROL1      (0x40 / 4)
56 #define SCU_RESET_CONTROL1              (0x04 / 4)
57 #define    SCU_RESET_SDRAM              BIT(0)
58 
59 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
60 {
61     return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
62 }
63 
64 static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
65 {
66     AspeedWDTState *s = ASPEED_WDT(opaque);
67 
68     trace_aspeed_wdt_read(offset, size);
69 
70     offset >>= 2;
71 
72     switch (offset) {
73     case WDT_STATUS:
74         return s->regs[WDT_STATUS];
75     case WDT_RELOAD_VALUE:
76         return s->regs[WDT_RELOAD_VALUE];
77     case WDT_RESTART:
78         qemu_log_mask(LOG_GUEST_ERROR,
79                       "%s: read from write-only reg at offset 0x%"
80                       HWADDR_PRIx "\n", __func__, offset);
81         return 0;
82     case WDT_CTRL:
83         return s->regs[WDT_CTRL];
84     case WDT_RESET_WIDTH:
85         return s->regs[WDT_RESET_WIDTH];
86     case WDT_RESET_MASK1:
87         return s->regs[WDT_RESET_MASK1];
88     case WDT_TIMEOUT_STATUS:
89     case WDT_TIMEOUT_CLEAR:
90     case WDT_RESET_MASK2:
91     case WDT_SW_RESET_CTRL:
92     case WDT_SW_RESET_MASK1:
93     case WDT_SW_RESET_MASK2:
94         qemu_log_mask(LOG_UNIMP,
95                       "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
96                       __func__, offset);
97         return 0;
98     default:
99         qemu_log_mask(LOG_GUEST_ERROR,
100                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
101                       __func__, offset);
102         return 0;
103     }
104 
105 }
106 
107 static void aspeed_wdt_reload(AspeedWDTState *s)
108 {
109     uint64_t reload;
110 
111     if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) {
112         reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
113                           s->pclk_freq);
114     } else {
115         reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
116     }
117 
118     if (aspeed_wdt_is_enabled(s)) {
119         timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
120     }
121 }
122 
123 static void aspeed_wdt_reload_1mhz(AspeedWDTState *s)
124 {
125     uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
126 
127     if (aspeed_wdt_is_enabled(s)) {
128         timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
129     }
130 }
131 
132 static uint64_t aspeed_2400_sanitize_ctrl(uint64_t data)
133 {
134     return data & 0xffff;
135 }
136 
137 static uint64_t aspeed_2500_sanitize_ctrl(uint64_t data)
138 {
139     return (data & ~(0xfUL << 8)) | WDT_CTRL_1MHZ_CLK;
140 }
141 
142 static uint64_t aspeed_2600_sanitize_ctrl(uint64_t data)
143 {
144     return data & ~(0x7UL << 7);
145 }
146 
147 static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
148                              unsigned size)
149 {
150     AspeedWDTState *s = ASPEED_WDT(opaque);
151     AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
152     bool enable;
153 
154     trace_aspeed_wdt_write(offset, size, data);
155 
156     offset >>= 2;
157 
158     switch (offset) {
159     case WDT_STATUS:
160         qemu_log_mask(LOG_GUEST_ERROR,
161                       "%s: write to read-only reg at offset 0x%"
162                       HWADDR_PRIx "\n", __func__, offset);
163         break;
164     case WDT_RELOAD_VALUE:
165         s->regs[WDT_RELOAD_VALUE] = data;
166         break;
167     case WDT_RESTART:
168         if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
169             s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
170             awc->wdt_reload(s);
171         }
172         break;
173     case WDT_CTRL:
174         data = awc->sanitize_ctrl(data);
175         enable = data & WDT_CTRL_ENABLE;
176         if (enable && !aspeed_wdt_is_enabled(s)) {
177             s->regs[WDT_CTRL] = data;
178             awc->wdt_reload(s);
179         } else if (!enable && aspeed_wdt_is_enabled(s)) {
180             s->regs[WDT_CTRL] = data;
181             timer_del(s->timer);
182         } else {
183             s->regs[WDT_CTRL] = data;
184         }
185         break;
186     case WDT_RESET_WIDTH:
187         if (awc->reset_pulse) {
188             awc->reset_pulse(s, data & WDT_POLARITY_MASK);
189         }
190         s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask;
191         s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask;
192         break;
193 
194     case WDT_RESET_MASK1:
195         /* TODO: implement */
196         s->regs[WDT_RESET_MASK1] = data;
197         break;
198 
199     case WDT_TIMEOUT_STATUS:
200     case WDT_TIMEOUT_CLEAR:
201     case WDT_RESET_MASK2:
202     case WDT_SW_RESET_CTRL:
203     case WDT_SW_RESET_MASK1:
204     case WDT_SW_RESET_MASK2:
205         qemu_log_mask(LOG_UNIMP,
206                       "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
207                       __func__, offset);
208         break;
209     default:
210         qemu_log_mask(LOG_GUEST_ERROR,
211                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
212                       __func__, offset);
213     }
214     return;
215 }
216 
217 static const VMStateDescription vmstate_aspeed_wdt = {
218     .name = "vmstate_aspeed_wdt",
219     .version_id = 0,
220     .minimum_version_id = 0,
221     .fields = (const VMStateField[]) {
222         VMSTATE_TIMER_PTR(timer, AspeedWDTState),
223         VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
224         VMSTATE_END_OF_LIST()
225     }
226 };
227 
228 static const MemoryRegionOps aspeed_wdt_ops = {
229     .read = aspeed_wdt_read,
230     .write = aspeed_wdt_write,
231     .endianness = DEVICE_LITTLE_ENDIAN,
232     .valid.min_access_size = 4,
233     .valid.max_access_size = 4,
234     .valid.unaligned = false,
235 };
236 
237 static void aspeed_wdt_reset(DeviceState *dev)
238 {
239     AspeedWDTState *s = ASPEED_WDT(dev);
240     AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
241 
242     s->regs[WDT_STATUS] = awc->default_status;
243     s->regs[WDT_RELOAD_VALUE] = awc->default_reload_value;
244     s->regs[WDT_RESTART] = 0;
245     s->regs[WDT_CTRL] = awc->sanitize_ctrl(0);
246     s->regs[WDT_RESET_WIDTH] = 0xFF;
247 
248     timer_del(s->timer);
249 }
250 
251 static void aspeed_wdt_timer_expired(void *dev)
252 {
253     AspeedWDTState *s = ASPEED_WDT(dev);
254     uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg;
255 
256     /* Do not reset on SDRAM controller reset */
257     if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) {
258         timer_del(s->timer);
259         s->regs[WDT_CTRL] = 0;
260         return;
261     }
262 
263     qemu_log_mask(CPU_LOG_RESET, "Watchdog timer %" HWADDR_PRIx " expired.\n",
264                   s->iomem.addr);
265     watchdog_perform_action();
266     timer_del(s->timer);
267 }
268 
269 #define PCLK_HZ 24000000
270 
271 static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
272 {
273     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
274     AspeedWDTState *s = ASPEED_WDT(dev);
275     AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev);
276 
277     assert(s->scu);
278 
279     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
280 
281     /* FIXME: This setting should be derived from the SCU hw strapping
282      * register SCU70
283      */
284     s->pclk_freq = PCLK_HZ;
285 
286     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
287                           TYPE_ASPEED_WDT, awc->iosize);
288     sysbus_init_mmio(sbd, &s->iomem);
289 }
290 
291 static Property aspeed_wdt_properties[] = {
292     DEFINE_PROP_LINK("scu", AspeedWDTState, scu, TYPE_ASPEED_SCU,
293                      AspeedSCUState *),
294     DEFINE_PROP_END_OF_LIST(),
295 };
296 
297 static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
298 {
299     DeviceClass *dc = DEVICE_CLASS(klass);
300 
301     dc->desc = "ASPEED Watchdog Controller";
302     dc->realize = aspeed_wdt_realize;
303     dc->reset = aspeed_wdt_reset;
304     set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
305     dc->vmsd = &vmstate_aspeed_wdt;
306     device_class_set_props(dc, aspeed_wdt_properties);
307     dc->desc = "Aspeed watchdog device";
308 }
309 
310 static const TypeInfo aspeed_wdt_info = {
311     .parent = TYPE_SYS_BUS_DEVICE,
312     .name  = TYPE_ASPEED_WDT,
313     .instance_size  = sizeof(AspeedWDTState),
314     .class_init = aspeed_wdt_class_init,
315     .class_size    = sizeof(AspeedWDTClass),
316     .abstract      = true,
317 };
318 
319 static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
320 {
321     DeviceClass *dc = DEVICE_CLASS(klass);
322     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
323 
324     dc->desc = "ASPEED 2400 Watchdog Controller";
325     awc->iosize = 0x20;
326     awc->ext_pulse_width_mask = 0xff;
327     awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
328     awc->wdt_reload = aspeed_wdt_reload;
329     awc->sanitize_ctrl = aspeed_2400_sanitize_ctrl;
330     awc->default_status = 0x03EF1480;
331     awc->default_reload_value = 0x03EF1480;
332 }
333 
334 static const TypeInfo aspeed_2400_wdt_info = {
335     .name = TYPE_ASPEED_2400_WDT,
336     .parent = TYPE_ASPEED_WDT,
337     .instance_size = sizeof(AspeedWDTState),
338     .class_init = aspeed_2400_wdt_class_init,
339 };
340 
341 static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property)
342 {
343     if (property) {
344         if (property == WDT_ACTIVE_HIGH_MAGIC) {
345             s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH;
346         } else if (property == WDT_ACTIVE_LOW_MAGIC) {
347             s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH;
348         } else if (property == WDT_PUSH_PULL_MAGIC) {
349             s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL;
350         } else if (property == WDT_OPEN_DRAIN_MAGIC) {
351             s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL;
352         }
353     }
354 }
355 
356 static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
357 {
358     DeviceClass *dc = DEVICE_CLASS(klass);
359     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
360 
361     dc->desc = "ASPEED 2500 Watchdog Controller";
362     awc->iosize = 0x20;
363     awc->ext_pulse_width_mask = 0xfffff;
364     awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
365     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
366     awc->wdt_reload = aspeed_wdt_reload_1mhz;
367     awc->sanitize_ctrl = aspeed_2500_sanitize_ctrl;
368     awc->default_status = 0x014FB180;
369     awc->default_reload_value = 0x014FB180;
370 }
371 
372 static const TypeInfo aspeed_2500_wdt_info = {
373     .name = TYPE_ASPEED_2500_WDT,
374     .parent = TYPE_ASPEED_WDT,
375     .instance_size = sizeof(AspeedWDTState),
376     .class_init = aspeed_2500_wdt_class_init,
377 };
378 
379 static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
380 {
381     DeviceClass *dc = DEVICE_CLASS(klass);
382     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
383 
384     dc->desc = "ASPEED 2600 Watchdog Controller";
385     awc->iosize = 0x40;
386     awc->ext_pulse_width_mask = 0xfffff; /* TODO */
387     awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
388     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
389     awc->wdt_reload = aspeed_wdt_reload_1mhz;
390     awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
391     awc->default_status = 0x014FB180;
392     awc->default_reload_value = 0x014FB180;
393 }
394 
395 static const TypeInfo aspeed_2600_wdt_info = {
396     .name = TYPE_ASPEED_2600_WDT,
397     .parent = TYPE_ASPEED_WDT,
398     .instance_size = sizeof(AspeedWDTState),
399     .class_init = aspeed_2600_wdt_class_init,
400 };
401 
402 static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data)
403 {
404     DeviceClass *dc = DEVICE_CLASS(klass);
405     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
406 
407     dc->desc = "ASPEED 1030 Watchdog Controller";
408     awc->iosize = 0x80;
409     awc->ext_pulse_width_mask = 0xfffff; /* TODO */
410     awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
411     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
412     awc->wdt_reload = aspeed_wdt_reload_1mhz;
413     awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
414     awc->default_status = 0x014FB180;
415     awc->default_reload_value = 0x014FB180;
416 }
417 
418 static const TypeInfo aspeed_1030_wdt_info = {
419     .name = TYPE_ASPEED_1030_WDT,
420     .parent = TYPE_ASPEED_WDT,
421     .instance_size = sizeof(AspeedWDTState),
422     .class_init = aspeed_1030_wdt_class_init,
423 };
424 
425 static void aspeed_2700_wdt_class_init(ObjectClass *klass, void *data)
426 {
427     DeviceClass *dc = DEVICE_CLASS(klass);
428     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
429 
430     dc->desc = "ASPEED 2700 Watchdog Controller";
431     awc->iosize = 0x80;
432     awc->ext_pulse_width_mask = 0xfffff; /* TODO */
433     awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
434     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
435     awc->wdt_reload = aspeed_wdt_reload_1mhz;
436     awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
437     awc->default_status = 0x014FB180;
438     awc->default_reload_value = 0x014FB180;
439 }
440 
441 static const TypeInfo aspeed_2700_wdt_info = {
442     .name = TYPE_ASPEED_2700_WDT,
443     .parent = TYPE_ASPEED_WDT,
444     .instance_size = sizeof(AspeedWDTState),
445     .class_init = aspeed_2700_wdt_class_init,
446 };
447 
448 static void wdt_aspeed_register_types(void)
449 {
450     type_register_static(&aspeed_wdt_info);
451     type_register_static(&aspeed_2400_wdt_info);
452     type_register_static(&aspeed_2500_wdt_info);
453     type_register_static(&aspeed_2600_wdt_info);
454     type_register_static(&aspeed_2700_wdt_info);
455     type_register_static(&aspeed_1030_wdt_info);
456 }
457 
458 type_init(wdt_aspeed_register_types)
459