1 /*
2  * ARM CMSDK APB watchdog emulation
3  *
4  * Copyright (c) 2018 Linaro Limited
5  * Written by Peter Maydell
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License version 2 or
9  *  (at your option) any later version.
10  */
11 
12 /*
13  * This is a model of the "APB watchdog" which is part of the Cortex-M
14  * System Design Kit (CMSDK) and documented in the Cortex-M System
15  * Design Kit Technical Reference Manual (ARM DDI0479):
16  * https://developer.arm.com/documentation/ddi0479/
17  *
18  * We also support the variant of this device found in the TI
19  * Stellaris/Luminary boards and documented in:
20  * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
21  */
22 
23 #include "qemu/osdep.h"
24 #include "qemu/log.h"
25 #include "trace.h"
26 #include "qapi/error.h"
27 #include "qemu/module.h"
28 #include "sysemu/watchdog.h"
29 #include "hw/sysbus.h"
30 #include "hw/irq.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/registerfields.h"
33 #include "hw/qdev-clock.h"
34 #include "hw/watchdog/cmsdk-apb-watchdog.h"
35 #include "migration/vmstate.h"
36 
37 REG32(WDOGLOAD, 0x0)
38 REG32(WDOGVALUE, 0x4)
39 REG32(WDOGCONTROL, 0x8)
40     FIELD(WDOGCONTROL, INTEN, 0, 1)
41     FIELD(WDOGCONTROL, RESEN, 1, 1)
42 #define R_WDOGCONTROL_VALID_MASK (R_WDOGCONTROL_INTEN_MASK | \
43                                   R_WDOGCONTROL_RESEN_MASK)
44 REG32(WDOGINTCLR, 0xc)
45 REG32(WDOGRIS, 0x10)
46     FIELD(WDOGRIS, INT, 0, 1)
47 REG32(WDOGMIS, 0x14)
48 REG32(WDOGTEST, 0x418) /* only in Stellaris/Luminary version of the device */
49 REG32(WDOGLOCK, 0xc00)
50 #define WDOG_UNLOCK_VALUE 0x1ACCE551
51 REG32(WDOGITCR, 0xf00)
52     FIELD(WDOGITCR, ENABLE, 0, 1)
53 #define R_WDOGITCR_VALID_MASK R_WDOGITCR_ENABLE_MASK
54 REG32(WDOGITOP, 0xf04)
55     FIELD(WDOGITOP, WDOGRES, 0, 1)
56     FIELD(WDOGITOP, WDOGINT, 1, 1)
57 #define R_WDOGITOP_VALID_MASK (R_WDOGITOP_WDOGRES_MASK | \
58                                R_WDOGITOP_WDOGINT_MASK)
59 REG32(PID4, 0xfd0)
60 REG32(PID5, 0xfd4)
61 REG32(PID6, 0xfd8)
62 REG32(PID7, 0xfdc)
63 REG32(PID0, 0xfe0)
64 REG32(PID1, 0xfe4)
65 REG32(PID2, 0xfe8)
66 REG32(PID3, 0xfec)
67 REG32(CID0, 0xff0)
68 REG32(CID1, 0xff4)
69 REG32(CID2, 0xff8)
70 REG32(CID3, 0xffc)
71 
72 /* PID/CID values */
73 static const uint32_t cmsdk_apb_watchdog_id[] = {
74     0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
75     0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
76     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
77 };
78 
79 static const uint32_t luminary_watchdog_id[] = {
80     0x00, 0x00, 0x00, 0x00, /* PID4..PID7 */
81     0x05, 0x18, 0x18, 0x01, /* PID0..PID3 */
82     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
83 };
84 
85 static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s)
86 {
87     /* Return masked interrupt status */
88     return s->intstatus && (s->control & R_WDOGCONTROL_INTEN_MASK);
89 }
90 
91 static bool cmsdk_apb_watchdog_resetstatus(CMSDKAPBWatchdog *s)
92 {
93     /* Return masked reset status */
94     return s->resetstatus && (s->control & R_WDOGCONTROL_RESEN_MASK);
95 }
96 
97 static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s)
98 {
99     bool wdogint;
100     bool wdogres;
101 
102     if (s->itcr) {
103         /*
104          * Not checking that !s->is_luminary since s->itcr can't be written
105          * when s->is_luminary in the first place.
106          */
107         wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK;
108         wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK;
109     } else {
110         wdogint = cmsdk_apb_watchdog_intstatus(s);
111         wdogres = cmsdk_apb_watchdog_resetstatus(s);
112     }
113 
114     qemu_set_irq(s->wdogint, wdogint);
115     if (wdogres) {
116         watchdog_perform_action();
117     }
118 }
119 
120 static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset,
121                                         unsigned size)
122 {
123     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
124     uint64_t r;
125 
126     switch (offset) {
127     case A_WDOGLOAD:
128         r = ptimer_get_limit(s->timer);
129         break;
130     case A_WDOGVALUE:
131         r = ptimer_get_count(s->timer);
132         break;
133     case A_WDOGCONTROL:
134         r = s->control;
135         break;
136     case A_WDOGRIS:
137         r = s->intstatus;
138         break;
139     case A_WDOGMIS:
140         r = cmsdk_apb_watchdog_intstatus(s);
141         break;
142     case A_WDOGLOCK:
143         r = s->lock;
144         break;
145     case A_WDOGITCR:
146         if (s->is_luminary) {
147             goto bad_offset;
148         }
149         r = s->itcr;
150         break;
151     case A_PID4 ... A_CID3:
152         r = s->id[(offset - A_PID4) / 4];
153         break;
154     case A_WDOGINTCLR:
155     case A_WDOGITOP:
156         if (s->is_luminary) {
157             goto bad_offset;
158         }
159         qemu_log_mask(LOG_GUEST_ERROR,
160                       "CMSDK APB watchdog read: read of WO offset %x\n",
161                       (int)offset);
162         r = 0;
163         break;
164     case A_WDOGTEST:
165         if (!s->is_luminary) {
166             goto bad_offset;
167         }
168         qemu_log_mask(LOG_UNIMP,
169                       "Luminary watchdog read: stall not implemented\n");
170         r = 0;
171         break;
172     default:
173 bad_offset:
174         qemu_log_mask(LOG_GUEST_ERROR,
175                       "CMSDK APB watchdog read: bad offset %x\n", (int)offset);
176         r = 0;
177         break;
178     }
179     trace_cmsdk_apb_watchdog_read(offset, r, size);
180     return r;
181 }
182 
183 static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
184                                      uint64_t value, unsigned size)
185 {
186     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
187 
188     trace_cmsdk_apb_watchdog_write(offset, value, size);
189 
190     if (s->lock && offset != A_WDOGLOCK) {
191         /* Write access is disabled via WDOGLOCK */
192         qemu_log_mask(LOG_GUEST_ERROR,
193                       "CMSDK APB watchdog write: write to locked watchdog\n");
194         return;
195     }
196 
197     switch (offset) {
198     case A_WDOGLOAD:
199         /* Reset the load value and the current count. */
200         ptimer_transaction_begin(s->timer);
201         ptimer_set_limit(s->timer, value, 1);
202         ptimer_transaction_commit(s->timer);
203         break;
204     case A_WDOGCONTROL: {
205         uint32_t prev_control = s->control;
206         if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) {
207             /*
208              * The Luminary version of this device ignores writes to
209              * this register after the guest has enabled interrupts
210              * (so they can only be disabled again via reset).
211              */
212             break;
213         }
214         s->control = value & R_WDOGCONTROL_VALID_MASK;
215         if (R_WDOGCONTROL_INTEN_MASK & (s->control ^ prev_control)) {
216             ptimer_transaction_begin(s->timer);
217             if (R_WDOGCONTROL_INTEN_MASK & s->control) {
218                 /*
219                  * Set HIGH to enable the counter and the interrupt. Reloads
220                  * the counter from the value in WDOGLOAD when the interrupt
221                  * is enabled, after previously being disabled.
222                  */
223                 ptimer_set_count(s->timer, ptimer_get_limit(s->timer));
224                 ptimer_run(s->timer, 0);
225             } else {
226                 /* Or LOW to disable the counter and interrupt. */
227                 ptimer_stop(s->timer);
228             }
229             ptimer_transaction_commit(s->timer);
230         }
231         cmsdk_apb_watchdog_update(s);
232         break;
233     }
234     case A_WDOGINTCLR:
235         s->intstatus = 0;
236         ptimer_transaction_begin(s->timer);
237         ptimer_set_count(s->timer, ptimer_get_limit(s->timer));
238         ptimer_transaction_commit(s->timer);
239         cmsdk_apb_watchdog_update(s);
240         break;
241     case A_WDOGLOCK:
242         s->lock = (value != WDOG_UNLOCK_VALUE);
243         trace_cmsdk_apb_watchdog_lock(s->lock);
244         break;
245     case A_WDOGITCR:
246         if (s->is_luminary) {
247             goto bad_offset;
248         }
249         s->itcr = value & R_WDOGITCR_VALID_MASK;
250         cmsdk_apb_watchdog_update(s);
251         break;
252     case A_WDOGITOP:
253         if (s->is_luminary) {
254             goto bad_offset;
255         }
256         s->itop = value & R_WDOGITOP_VALID_MASK;
257         cmsdk_apb_watchdog_update(s);
258         break;
259     case A_WDOGVALUE:
260     case A_WDOGRIS:
261     case A_WDOGMIS:
262     case A_PID4 ... A_CID3:
263         qemu_log_mask(LOG_GUEST_ERROR,
264                       "CMSDK APB watchdog write: write to RO offset 0x%x\n",
265                       (int)offset);
266         break;
267     case A_WDOGTEST:
268         if (!s->is_luminary) {
269             goto bad_offset;
270         }
271         qemu_log_mask(LOG_UNIMP,
272                       "Luminary watchdog write: stall not implemented\n");
273         break;
274     default:
275 bad_offset:
276         qemu_log_mask(LOG_GUEST_ERROR,
277                       "CMSDK APB watchdog write: bad offset 0x%x\n",
278                       (int)offset);
279         break;
280     }
281 }
282 
283 static const MemoryRegionOps cmsdk_apb_watchdog_ops = {
284     .read = cmsdk_apb_watchdog_read,
285     .write = cmsdk_apb_watchdog_write,
286     .endianness = DEVICE_LITTLE_ENDIAN,
287     /* byte/halfword accesses are just zero-padded on reads and writes */
288     .impl.min_access_size = 4,
289     .impl.max_access_size = 4,
290     .valid.min_access_size = 1,
291     .valid.max_access_size = 4,
292 };
293 
294 static void cmsdk_apb_watchdog_tick(void *opaque)
295 {
296     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
297 
298     if (!s->intstatus) {
299         /* Count expired for the first time: raise interrupt */
300         s->intstatus = R_WDOGRIS_INT_MASK;
301     } else {
302         /* Count expired for the second time: raise reset and stop clock */
303         s->resetstatus = 1;
304         ptimer_stop(s->timer);
305     }
306     cmsdk_apb_watchdog_update(s);
307 }
308 
309 static void cmsdk_apb_watchdog_reset(DeviceState *dev)
310 {
311     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
312 
313     trace_cmsdk_apb_watchdog_reset();
314     s->control = 0;
315     s->intstatus = 0;
316     s->lock = 0;
317     s->itcr = 0;
318     s->itop = 0;
319     s->resetstatus = 0;
320     /* Set the limit and the count */
321     ptimer_transaction_begin(s->timer);
322     /*
323      * We need to stop the ptimer before setting its limit reset value. If the
324      * order is the opposite when the code executes the stop after setting a new
325      * limit it may want to recalculate the count based on the current time (if
326      * the timer was currently running) and it won't get the proper reset value.
327      */
328     ptimer_stop(s->timer);
329     ptimer_set_limit(s->timer, 0xffffffff, 1);
330     ptimer_transaction_commit(s->timer);
331 }
332 
333 static void cmsdk_apb_watchdog_clk_update(void *opaque, ClockEvent event)
334 {
335     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
336 
337     ptimer_transaction_begin(s->timer);
338     ptimer_set_period_from_clock(s->timer, s->wdogclk, 1);
339     ptimer_transaction_commit(s->timer);
340 }
341 
342 static void cmsdk_apb_watchdog_init(Object *obj)
343 {
344     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
345     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
346 
347     memory_region_init_io(&s->iomem, obj, &cmsdk_apb_watchdog_ops,
348                           s, "cmsdk-apb-watchdog", 0x1000);
349     sysbus_init_mmio(sbd, &s->iomem);
350     sysbus_init_irq(sbd, &s->wdogint);
351     s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK",
352                                     cmsdk_apb_watchdog_clk_update, s,
353                                     ClockUpdate);
354 
355     s->is_luminary = false;
356     s->id = cmsdk_apb_watchdog_id;
357 }
358 
359 static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
360 {
361     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
362 
363     if (!clock_has_source(s->wdogclk)) {
364         error_setg(errp,
365                    "CMSDK APB watchdog: WDOGCLK clock must be connected");
366         return;
367     }
368 
369     s->timer = ptimer_init(cmsdk_apb_watchdog_tick, s,
370                            PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
371                            PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
372                            PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
373                            PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
374 
375     ptimer_transaction_begin(s->timer);
376     ptimer_set_period_from_clock(s->timer, s->wdogclk, 1);
377     ptimer_transaction_commit(s->timer);
378 }
379 
380 static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
381     .name = "cmsdk-apb-watchdog",
382     .version_id = 2,
383     .minimum_version_id = 2,
384     .fields = (const VMStateField[]) {
385         VMSTATE_CLOCK(wdogclk, CMSDKAPBWatchdog),
386         VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),
387         VMSTATE_UINT32(control, CMSDKAPBWatchdog),
388         VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),
389         VMSTATE_UINT32(lock, CMSDKAPBWatchdog),
390         VMSTATE_UINT32(itcr, CMSDKAPBWatchdog),
391         VMSTATE_UINT32(itop, CMSDKAPBWatchdog),
392         VMSTATE_UINT32(resetstatus, CMSDKAPBWatchdog),
393         VMSTATE_END_OF_LIST()
394     }
395 };
396 
397 static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
398 {
399     DeviceClass *dc = DEVICE_CLASS(klass);
400 
401     dc->realize = cmsdk_apb_watchdog_realize;
402     dc->vmsd = &cmsdk_apb_watchdog_vmstate;
403     device_class_set_legacy_reset(dc, cmsdk_apb_watchdog_reset);
404 }
405 
406 static const TypeInfo cmsdk_apb_watchdog_info = {
407     .name = TYPE_CMSDK_APB_WATCHDOG,
408     .parent = TYPE_SYS_BUS_DEVICE,
409     .instance_size = sizeof(CMSDKAPBWatchdog),
410     .instance_init = cmsdk_apb_watchdog_init,
411     .class_init = cmsdk_apb_watchdog_class_init,
412 };
413 
414 static void luminary_watchdog_init(Object *obj)
415 {
416     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
417 
418     s->is_luminary = true;
419     s->id = luminary_watchdog_id;
420 }
421 
422 static const TypeInfo luminary_watchdog_info = {
423     .name = TYPE_LUMINARY_WATCHDOG,
424     .parent = TYPE_CMSDK_APB_WATCHDOG,
425     .instance_init = luminary_watchdog_init
426 };
427 
428 static void cmsdk_apb_watchdog_register_types(void)
429 {
430     type_register_static(&cmsdk_apb_watchdog_info);
431     type_register_static(&luminary_watchdog_info);
432 }
433 
434 type_init(cmsdk_apb_watchdog_register_types);
435